//Copyright (C)2014-2025 GOWIN Semiconductor Corporation.
//All rights reserved.
//File Title: Timing Constraints file
//Tool Version: V1.9.11.02 (64-bit) 
//Created Time: 2025-06-11 14:43:55
create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
create_clock -name Sck_i -period 16.667 -waveform {0 8.334} [get_ports {Sck_i}]
create_generated_clock -name clk50 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 12 -multiply_by 25 [get_nets {clk50}]
create_generated_clock -name clk210 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 4 -multiply_by 35 [get_nets {ClkGen/clk210Mhz}]
create_generated_clock -name clk5 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 120 -multiply_by 25 [get_nets {clk5}]
# create_generated_clock -name clk60 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 14 -multiply_by 35 [get_nets {clk60}]
create_generated_clock -name clk26dot25 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 32 -multiply_by 35 [get_nets {clk26dot25}]
create_generated_clock -name clk20 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 30 -multiply_by 25 [get_nets {clk20}]
create_generated_clock -name clk100 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 6 -multiply_by 25 [get_nets {ClkGen/clk100Mhz}]
set_clock_groups -asynchronous -group [get_clocks {Sck_i}] -group [get_clocks {Clk_i}]
set_false_path -from [get_regs {InitRst/signal_o_s1}] 
# report_timing -setup -from_clock [get_clocks {clk50}] -to_clock [get_clocks {clk60}] -max_paths 250 -max_common_paths 1
# report_timing -setup -from_clock [get_clocks {clk60}] -to_clock [get_clocks {clk50}] -max_paths 250 -max_common_paths 1
report_timing -setup -from_clock [get_clocks {clk50}] -to_clock [get_clocks {clk50}] -max_paths 100 -max_common_paths 1
# report_timing -setup -from_clock [get_clocks {clk60}] -to_clock [get_clocks {clk60}] -max_paths 100 -max_common_paths 1
