// module Sync1bit #(
//     parameter WIDTH = 1,
//     parameter STAGES = 2
// )
// (
//     input ClkFast_i,
//     input ClkSlow_i,
//     input Signal_i,

//     output [WIDTH-1:0] Signal_o

// );

// //lauch registers 
// reg signalReg;
// // capture registers
// (* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] signalReg_c;

// assign Signal_o = signalReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];

// always @(posedge ClkFast_i) begin
//     signalReg <= Signal_i;
// end

// always @(posedge ClkSlow_i) begin 
//     signalReg_c <= {signalReg_c[(STAGES-1)*WIDTH-1:0], signalReg};
// end

// endmodule
module Sync1bit (
    input ClkFast_i,
    input ClkSlow_i,
    input Rst_i,
    input Ss_i,
    input Signal_i,

    output Signal_o
);

//================================================================================
//  REG/WIRE
reg plsToggle;
reg plsToggleSyncA;
reg plsToggleSyncB;
reg plsToggleSyncC;

//================================================================================
//  ASSIGNMENTS
//================================================================================
assign Signal_o = plsToggleSyncB^plsToggleSyncA;
//================================================================================
//	CODING
//================================================================================
always @(posedge ClkFast_i) begin 
    if (Rst_i) begin 
        plsToggle <= 1'b0;
    end
    else begin 
        if (Signal_i) begin 
            plsToggle <= ~plsToggle;
        end
        else begin 
            plsToggle <= plsToggle;
        end
    end
end

// always @(posedge Ss_i or posedge Rst_i) begin
//     if (Rst_i) begin 
//         plsToggle <= 1'b0;
//     end
//     else begin 
//         if (Ss_i) begin 
//             plsToggle <= ~plsToggle;
//         end
//         else begin 
//             plsToggle <= plsToggle;
//         end
//     end
// end

always @(posedge ClkSlow_i) begin 
    if (Rst_i) begin 
        plsToggleSyncA <= 1'b0;
        plsToggleSyncB <= 1'b0;
    end
    else begin 
        plsToggleSyncA <= plsToggle;
        plsToggleSyncB <= plsToggleSyncA;
    end
end

always @(posedge ClkSlow_i) begin 
    if (Rst_i) begin 
        plsToggleSyncC <= 1'b0;
    end
    else begin
        plsToggleSyncC <= plsToggleSyncB;
    end
end


endmodule
