////////////////////////////////////////////////////////////////////////////////////////////
// Company:			TAIR
// Engineer:		Zaytsev Mikhail
// 
// Create Date:		26/04/2024 
// Design Name: 
// Module Name:		Gpio1CtrlTb 
// Project Name:	SB_TMSG44V1_FPGA
// Target Devices:	Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
// Tool versions:
// Description:		The module simulates three 4Mosi GPIO register writes 
//					and three 1Mosi GPIO register writes.
//
// Dependencies:	
// Revision: 
// Revision 1.0 - File Created
// Additional Comments: 
//
////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ns

module Gpio1CtrlTb();

reg Clk;
reg Rst;
reg [4:0] cnt;
reg [4:0] state;

reg [23:0] DataGpio;
reg ValData;

reg FlagDirectGpio1;
reg ValDataFromSpi;

always #5 Clk = ~Clk;

initial begin
	Clk	=	1'b1;
	Rst = 	1'b1;
	#100
	Rst = 	1'b0;
end

always @(posedge Clk) begin
	if(Rst) begin
		DataGpio <= 0;
		cnt <= 0;
		state <= 0;
		ValData <= 0;
		FlagDirectGpio1 <= 0;
		ValDataFromSpi <= 0;
	end 
	else begin
		case (state)
			0: begin
				DataGpio <= 23'h3FFFFF;

				if (cnt == 6) begin
					cnt <= 0;
					ValData <= 1;
					state <= state + 1;
				end
				else begin
					ValData = 0;
					cnt <= cnt + 1;
					state <= state;
				end
			end
			1: begin
				DataGpio <= 23'h311111;

				if (cnt == 6) begin
					cnt <= 0;
					ValData <= 1;
					state <= state + 1;
				end
				else begin
					ValData = 0;
					cnt <= cnt + 1;
					state <= state;
				end
			end
			2: begin
				DataGpio <= 23'h3AAAAA;

				if (cnt == 6) begin
					cnt <= 0;
					ValData <= 1;
					state <= state + 1;
				end
				else begin
					ValData = 0;
					cnt <= cnt + 1;
					state <= state;
				end
			end
			3: begin
				ValData = 0;
				state = state + 1;
			end
			4: begin
				DataGpio <= 23'h3FFFFA;

				if (cnt == 6) begin
					cnt <= 0;
					ValDataFromSpi <= 1;
					state <= state + 1;
				end
				else begin
					FlagDirectGpio1 <= 1;
					ValDataFromSpi = 0;
					cnt <= cnt + 1;
					state <= state;
				end
			end
			5: begin
				DataGpio <= 23'h31111A;

				if (cnt == 6) begin
					cnt <= 0;
					ValDataFromSpi <= 1;
					state <= state + 1;
				end
				else begin
					ValDataFromSpi = 0;
					cnt <= cnt + 1;
					state <= state;
				end
			end
			6: begin
				DataGpio <= 23'h3AAAAF;

				if (cnt == 6) begin
					cnt <= 0;
					ValDataFromSpi <= 1;
					state <= state + 1;
				end
				else begin
					ValDataFromSpi = 0;
					cnt <= cnt + 1;
					state <= state;
				end
			end
			7: begin
				ValDataFromSpi = 0;
				state = state + 1;
			end

			8: begin
				FlagDirectGpio1 <= 0;
			end
		endcase
	end
end

Gpio1Ctrl DUT(
	.Clk_i					(Clk),
	.Rst_i					(Rst),

	.ValGpioDataToFifo_i	(ValData),
	.Data_i					(DataGpio),
	.ValDataFromSpi_i		(ValDataFromSpi),

	.FlagDirectGpio1_i		(FlagDirectGpio1),

	.GpioReg_o				()
);

endmodule