////////////////////////////////////////////////////////////////////////////////////////////
// Company:			TAIR
// Engineer:		Zaytsev Mikhail
// 
// Create Date:		24/04/2024 
// Design Name: 
// Module Name:		Gpio1Ctrl 
// Project Name:	SB_TMSG44V1_FPGA
// Target Devices:	Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
// Tool versions:
// Description:		The module saves data to the register by validity signal for GPIO devices.
//
// Dependencies:	
// Revision: 
// Revision 1.0 - File Created
// Additional Comments: 
//
////////////////////////////////////////////////////////////////////////////////////////////
module Gpio1Ctrl (
	input Clk_i,
	
	input ValGpioDataToFifo_i,
	input [23:0] Data_i,
	input ValDataFromSpi_i,

	input FlagDirectGpio1_i,

	output reg [21:0] GpioReg_o
);

always @(posedge Clk_i) begin 
	if (ValGpioDataToFifo_i || (FlagDirectGpio1_i && ValDataFromSpi_i)) begin 
		GpioReg_o <= Data_i[21:0];
	end
end

endmodule