// Company:         TAIR
// Engineer:        Chigrinskiy A.  
// 
// Create Date:     18/04/2024 
// Design Name: 
// Module Name:     LmxWrapper
// Project Name:    SB_TMSG44V1_FPGA
// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
// Tool versions:
// Description:    This module is a wrapper for the LMX Fifo, LMX Fifo Controller and SPI Master modules.
//
// Dependencies:  
// Revision: 
// Revision 1.0 - File Created
// Additional Comments: 
//
////////////////////////////////////////////////////////////////////////////////////////////
module LmxWrapper #(
    parameter IN_WIDTH = 24,
    parameter WR_NUM = 1,
    parameter OUT_WIDTH = 24,
    parameter DATA_WIDTH = 24
)(
    input WrClk_i,
    input RdClk_i,
    input Rst_i,
    input [IN_WIDTH-1:0] Data_i,
    input Val_i,

	input [3:0] LmxWordNum_i,
	input [2:0] DdsWordNumReg_i,
	input DdsCs_i,
	input DdsBusy_i,
	input LmxDirectFlag_i,
	input LmxWordNumVal_i,

	output reg PllVtuneCtrl_o,
	output [3:0] LmxWordNumReg_o,

    output Ss_o,
    output Sck_o,
    output Mosi_o

);
//================================================================================
//	                                REG/WIRE
//================================================================================    
wire [OUT_WIDTH-1:0] dataFromLmxFifoCtrl;
wire [OUT_WIDTH-1:0] dataFromLmxFifo;
wire readEnLmx;
wire writeEnLmx;
wire valRdDataLMX;
wire busySpiMLmx;
wire lmxFifoFull;
wire lmxFifoEmpty;
wire lmxWordNumValSync;

reg plsToggle;
reg plsToggleSyncA;
reg plsToggleSyncB;

reg ssR;
reg ssReg;
reg ssRegDds;
reg [3:0] lmxWordNumReg; 
reg [3:0] lmxWordNumRegR;
reg [2:0] ddsWordNumRegSync;
//==========================================================================//
//									ASSIGNMENTS								//
//==========================================================================//
assign lmxWordNumValSync = plsToggleSyncB^plsToggleSyncA;
assign LmxWordNumReg_o = lmxWordNumReg;
//==========================================================================//
//									CODING									//
//==========================================================================//
always @(posedge WrClk_i) begin
	if (Rst_i) begin 
		plsToggle <= 1'b0;
	end
	else if (LmxWordNumVal_i) begin 
		plsToggle <= ~plsToggle;
	end
	else begin 
		plsToggle <= plsToggle;
	end
end

always @(posedge RdClk_i) begin 
	if (Rst_i) begin 
		plsToggleSyncA <= 1'b0;
		plsToggleSyncB <= 1'b0;
	end
	else begin 
		plsToggleSyncA <= plsToggle;
		plsToggleSyncB <= plsToggleSyncA;
	end
end

always @(posedge WrClk_i) begin
	if (Rst_i) begin 
		ssR <= 1'b0;
	end
	else begin 
		ssR <= Ss_o;
	end
end

always @(posedge RdClk_i) begin 
	if (Rst_i) begin 
		ssReg <= 1'b0;
	end
	else begin 
		ssReg <= Ss_o;
	end
end

always @(posedge RdClk_i) begin 
	if (Rst_i) begin 
		ssRegDds <= 1'b0;
	end
	else begin 
		ssRegDds <= DdsCs_i;
	end
end

always @(posedge RdClk_i) begin
	if (Rst_i) begin 
		lmxWordNumReg <= 3'h0;
	end
	else begin 
		if (lmxWordNumValSync) begin 
			lmxWordNumReg <= LmxWordNum_i;
		end
		else begin 
			if (Ss_o && !ssReg && lmxWordNumReg != 0) begin 
				lmxWordNumReg <= lmxWordNumReg-1;
			end
		end
	end
end

always @(posedge RdClk_i) begin 
	if (Rst_i) begin 
		ddsWordNumRegSync <= 3'h0;
	end
	else begin 
		ddsWordNumRegSync <= DdsWordNumReg_i;
	end
end

always @(posedge RdClk_i) begin 
	if (Rst_i) begin 
		PllVtuneCtrl_o <=1'b0;
	end
	else begin
		if (!LmxDirectFlag_i) begin  
			if ((lmxWordNumReg == 0) && (ddsWordNumRegSync == 0) ) begin
				PllVtuneCtrl_o <= 1'b1;
			end
			else if ((!DdsCs_i && ssRegDds) && (ddsWordNumRegSync != 0)) begin 
				PllVtuneCtrl_o <= 1'b0;
			end
			else if ((!Ss_o && ssReg) && (lmxWordNumReg != 0) ) begin 
				PllVtuneCtrl_o <= 1'b0;
			end
		end
		else begin 
			PllVtuneCtrl_o <= 1'b1;
		end
	end
end

FifoCtrl #(
	.IN_WIDTH		(IN_WIDTH),
	.WR_NUM			(WR_NUM),
	.OUT_WIDTH		(OUT_WIDTH)
) FifoCtrlLmx
(
	.WrClk_i		(WrClk_i),
	.RdClk_i		(RdClk_i),
	.Rst_i			(Rst_i),
	.Data_i			(Data_i),
	.Val_i			(Val_i),
	.BusySpiM_i		(busySpiMLmx | DdsBusy_i),
	.FifoFull_i		(lmxFifoFull),
	.FifoEmpty_i	(lmxFifoEmpty),
	.Data_o			(dataFromLmxFifoCtrl),
	.ReadEn_o		(readEnLmx),
	.WriteEn_o		(writeEnLmx),
	.ValRdData_o	(valRdDataLMX)
);

FifoLMX FifoLMX_inst (
	.Data	(dataFromLmxFifoCtrl),
	.WrClk	(WrClk_i),
	.RdClk	(RdClk_i),
	.Reset	(Rst_i),
	.WrEn	(writeEnLmx),
	.RdEn	(readEnLmx),
	.Full	(lmxFifoFull),
	.Empty	(lmxFifoEmpty),
	.Q		(dataFromLmxFifo)
);

SpiM #(
	.DATA_WIDTH	(DATA_WIDTH)
)SpiMLmx(
	.Clk_i		(RdClk_i),
	.Rst_i		(Rst_i),
	.Val_i		(valRdDataLMX),
	.SpiData_i	(dataFromLmxFifo),
	.Busy_o	    (busySpiMLmx),
	.Ss_o		(Ss_o),
	.Mosi_o		(Mosi_o),
	.Sck_o		(Sck_o)
);

endmodule