Промежуточные изменения

src/constr/SbTmsg.sdc

@@ -2,13 +2,11 @@
 //All rights reserved.
 //File Title: Timing Constraints file
 //Tool Version: V1.9.9.03 (64-bit) 
-//Created Time: 2024-05-27 16:53:57
+//Created Time: 2024-05-29 16:56:41
+create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
+//create_clock -name clk100 -period 10 -waveform {0 5} [get_nets {gclk100}]
 create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
 create_clock -name clk5 -period 200 -waveform {0 100} [get_nets {clk5}]
-//create_clock -name clk100 -period 10 -waveform {0 5} [get_nets {gclk100}]
-//create_clock -name clk50 -period 20 -waveform {0 10} [get_nets {clk50}]
-create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
 set_clock_groups -asynchronous -group [get_clocks {Clk_i}] -group [get_clocks {Sck_i}]
 set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Clk_i}] 
 set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Sck_i}] 
-//report_timing -setup -from_clock [get_clocks {clk100}] -mod_ins {SpiSlaveArbiter}

src/src/CDC/Sync1bit.v

@@ -0,0 +1,103 @@
+// module Sync1bit #(
+//     parameter WIDTH = 1,
+//     parameter STAGES = 2
+// )
+// (
+//     input ClkFast_i,
+//     input ClkSlow_i,
+//     input Signal_i,
+
+//     output [WIDTH-1:0] Signal_o
+
+// );
+
+// //lauch registers 
+// reg signalReg;
+// // capture registers
+// (* ASYNC_REG = "TRUE" *) reg [STAGES*WIDTH-1:0] signalReg_c;
+
+// assign Signal_o = signalReg_c[STAGES*WIDTH-1:(STAGES-1)*WIDTH];
+
+// always @(posedge ClkFast_i) begin
+//     signalReg <= Signal_i;
+// end
+
+// always @(posedge ClkSlow_i) begin 
+//     signalReg_c <= {signalReg_c[(STAGES-1)*WIDTH-1:0], signalReg};
+// end
+
+// endmodule
+module Sync1bit (
+    input ClkFast_i,
+    input ClkSlow_i,
+    input Rst_i,
+    input Ss_i,
+    input Signal_i,
+
+    output Signal_o
+);
+
+//================================================================================
+//  REG/WIRE
+reg plsToggle;
+reg plsToggleSyncA;
+reg plsToggleSyncB;
+reg plsToggleSyncC;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign Signal_o = plsToggleSyncA^plsToggle;
+//================================================================================
+//	CODING
+//================================================================================
+always @(posedge ClkFast_i) begin 
+    if (Rst_i) begin 
+        plsToggle <= 1'b0;
+    end
+    else begin 
+        if (Signal_i) begin 
+            plsToggle <= ~plsToggle;
+        end
+        else begin 
+            plsToggle <= plsToggle;
+        end
+    end
+end
+
+// always @(posedge Ss_i or posedge Rst_i) begin
+//     if (Rst_i) begin 
+//         plsToggle <= 1'b0;
+//     end
+//     else begin 
+//         if (Ss_i) begin 
+//             plsToggle <= ~plsToggle;
+//         end
+//         else begin 
+//             plsToggle <= plsToggle;
+//         end
+//     end
+// end
+
+always @(posedge ClkSlow_i) begin 
+    if (Rst_i) begin 
+        plsToggleSyncA <= 1'b0;
+        plsToggleSyncB <= 1'b0;
+    end
+    else begin 
+        plsToggleSyncA <= plsToggle;
+        plsToggleSyncB <= plsToggleSyncA;
+    end
+end
+
+always @(posedge ClkSlow_i) begin 
+    if (Rst_i) begin 
+        plsToggleSyncC <= 1'b0;
+    end
+    else begin
+        plsToggleSyncC <= plsToggleSyncB;
+    end
+end
+
+
+endmodule

src/src/Top/ExtSpiMEmul.v

@@ -148,7 +148,7 @@ module ExtSpiMEmul (
         end
         else begin
             if (SelSt_i) begin 
-                if (ssPol && !ssR) begin 
+                if (Ss && !ssR) begin 
                     stopFlag <= 1'b1;
                 end
                 else if ( delayCnt == Stop_i) begin 
@@ -156,7 +156,7 @@ module ExtSpiMEmul (
                 end
             end
             else begin 
-                if (!ssPol && ssR) begin 
+                if (!Ss && ssR) begin 
                     stopFlag <= 1'b1;
                 end
                 else if (delayCnt == Stop_i) begin 

src/src/Top/TopSbTmsg.v

@@ -120,6 +120,7 @@ module TopSbTmsg
 	wire clk60;
 
 	wire spiDataVal;
+	wire spiDataValSync;
 	wire [WORDWIDTH-1:0] spiData;
 	wire [21:0] gpio1CtrlData;
 	
@@ -351,7 +352,7 @@ InterfaceArbiter
 SpiSlaveArbiter
 (
 	.Rst_i		(Rst_i),
-	.Clk_i		(clk50),
+	.Clk_i		(clk60),
 	
 	.Sck_i		(Sck_i),
 	.Ss_i		(Ss_i),
@@ -366,13 +367,22 @@ SpiSlaveArbiter
 	.Data_o		(spiData)
 );
 
+Sync1bit SyncPulse(
+	.ClkFast_i	(gclk100),
+	.ClkSlow_i	(clk60),
+	.Signal_i	(spiDataVal),
+	.Ss_i		(Ss_i),
+	.Rst_i		(initRst),
+	.Signal_o	(spiDataValSync)	
+);
+
 PacketAnalyzer4Mosi PacketAnalyzer4Mosi
 (
-	.Clk_i					(clk50),
+	.Clk_i					(clk60),
 	.Rst_i					(Rst_i),
 
 	.DataFromSpi_i			(spiData),
-	.ValDataFromSpi_i		(spiDataVal),
+	.ValDataFromSpi_i		(spiDataValSync),
 
 	.BusyMosi1_i			(busyMosi1),
 
@@ -394,11 +404,11 @@ PacketAnalyzer4Mosi PacketAnalyzer4Mosi
 
 PacketAnalyzer1Mosi	PacketAnalyzer1Mosi
 (
-	.Clk_i					(clk50),
+	.Clk_i					(clk60),
 	.Rst_i					(Rst_i),
 	
 	.DataFromSpi_i			(spiData),
-	.ValDataFromSpi_i		(spiDataVal),
+	.ValDataFromSpi_i		(spiDataValSync),
 	
 	.BusyMosi4_i			(busyMosi4),
 	
@@ -422,7 +432,7 @@ LmxWrapper #(
 	.OUT_WIDTH			(24),
 	.DATA_WIDTH			(24)
 ) LmxWrapper(
-	.WrClk_i			(clk50),
+	.WrClk_i			(clk60),
 	.RdClk_i			(clk5),
 	.Rst_i				(initRst),
 	.Data_i				(spiData),
@@ -442,7 +452,7 @@ DDSWrapper #(
 	.OUT_WIDTH			(80),
 	.DATA_WIDTH			(80)
 ) DDSWrapper(
-	.WrClk_i			(clk50),
+	.WrClk_i			(clk60),
 	.RdClk_i			(clk5),
 	.Rst_i				(initRst),
 	.DdsWordNum_i		(ddsWordNum),
@@ -462,7 +472,7 @@ PotWrapper #(
 	.OUT_WIDTH		(16),
 	.DATA_WIDTH		(16)
 ) PotWrapper(
-	.WrClk_i		(clk50),
+	.WrClk_i		(clk60),
 	.RdClk_i		(clk5),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
@@ -478,7 +488,7 @@ DacWrapper #(
 	.OUT_WIDTH		(16),
 	.DATA_WIDTH		(16)
 ) DacWrapper(
-	.WrClk_i		(clk50),
+	.WrClk_i		(clk60),
 	.RdClk_i		(clk5),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
@@ -494,7 +504,7 @@ AttenuatorWrapper #(
 	.OUT_WIDTH		(16),
 	.DATA_WIDTH		(16)
 ) AttenuatorWrapper(
-	.WrClk_i		(clk50),
+	.WrClk_i		(clk60),
 	.RdClk_i		(clk5),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
@@ -510,7 +520,7 @@ ShiftRegWrapper #(
 	.OUT_WIDTH		(8),
 	.DATA_WIDTH		(8)
 ) ShiftRegWrapper(
-	.WrClk_i		(clk50),
+	.WrClk_i		(clk60),
 	.RdClk_i		(clk5),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
@@ -526,7 +536,7 @@ Max2870Wrapper #(
 	.OUT_WIDTH		(32),
 	.DATA_WIDTH		(32)
 ) Max2870Wrapper(
-	.WrClk_i		(clk50),
+	.WrClk_i		(clk60),
 	.RdClk_i		(clk5),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
@@ -548,16 +558,16 @@ TempRead TempRead (
 
 Gpio1Ctrl Gpio1Ctrl
 (
-	.Clk_i					(clk50),
+	.Clk_i					(clk60),
 	.ValGpioDataToFifo_i	(valGpioDataToFifo),
-	.ValDataFromSpi_i		(spiDataVal),
+	.ValDataFromSpi_i		(spiDataValSync),
 	.FlagDirectGpio1_i		(flagDirectGpio1),
 	.Data_i					(spiData),
 	.GpioReg_o				(gpio1CtrlData)
 );
 
 Gpio2Read Gpio2Read (
-	.Clk_i				(clk50),
+	.Clk_i				(clk60),
 	.Rst_i				(Rst_i),
 	.ClkSpi_i			(Sck_i),
 	.LdMax_i			(MisoLdMax2870_i),