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@@ -0,0 +1,102 @@
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+set DSN_ROOT [file normalize [file join [file dirname [info script]] "."]]
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+create_project -name SB_TMSG44V1_FPGA -dir $::DSN_ROOT/SB_TMSG44V1_FPGA_PROJ -pn GW1N-LV9PG256C6/I5 -device_version C -force
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+
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+
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+#add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/Top/RFTop.v"
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+#add_file -type cst "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/constr/RF_FPGA.cst"
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+#add_file -type sdc "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/constr/RF_FPGA.sdc"
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+
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+
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+
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+
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+set_option -synthesis_tool gowinsynthesis
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+set_option -output_base_name SB_TMSG44V1_FPGA
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+set_option -top_module TopSbtmsg
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+set_option -gen_verilog_sim_netlist 1
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+
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+set_option -print_all_synthesis_warning 0
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+set_option -allow_duplicate_modules 0
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+set_option -multi_file_compilation_unit 1
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+set_option -auto_constraint_io 0
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+set_option -default_enum_encoding default
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+set_option -compiler_compatible 1
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+set_option -disable_io_insertion 0
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+set_option -fix_gated_and_generated_clocks 1
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+set_option -frequency Auto
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+set_option -looplimit 2000
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+set_option -maxfan 10000
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+set_option -pipe 1
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+set_option -resolve_multiple_driver 0
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+set_option -resource_sharing 1
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+set_option -retiming 0
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+set_option -run_prop_extract 1
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+set_option -rw_check_on_ram 0
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+set_option -supporttypedflt 0
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+set_option -symbolic_fsm_compiler 1
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+set_option -synthesis_onoff_pragma 0
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+set_option -update_models_cp 0
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+set_option -write_apr_constraint 1
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+set_option -gen_sdf 0
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+set_option -gen_io_cst 0
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+set_option -vccaux 3.3
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+set_option -gen_ibis 0
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+set_option -gen_posp 0
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+set_option -gen_text_timing_rpt 0
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+set_option -gen_verilog_sim_netlist 1
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+set_option -gen_vhdl_sim_netlist 0
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+set_option -show_init_in_vo 0
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+set_option -show_all_warn 0
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+set_option -timing_driven 1
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+set_option -ireg_in_iob 1
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+set_option -oreg_in_iob 1
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+set_option -ioreg_in_iob 1
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+set_option -replicate_resources 0
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+set_option -cst_warn_to_error 1
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+set_option -rpt_auto_place_io_info 0
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+set_option -correct_hold_violation 1
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+set_option -place_option 0
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+set_option -route_option 0
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+set_option -clock_route_order 0
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+set_option -route_maxfan 23
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+set_option -use_jtag_as_gpio 0
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+set_option -use_sspi_as_gpio 1
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+set_option -use_mspi_as_gpio 0
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+set_option -use_ready_as_gpio 1
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+set_option -use_done_as_gpio 0
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+set_option -use_reconfign_as_gpio 0
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+set_option -use_mode_as_gpio 0
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+set_option -use_i2c_as_gpio 0
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+set_option -use_cpu_as_gpio 0
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+set_option -power_on_reset_monitor 1
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+set_option -bit_format bin
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+set_option -bit_crc_check 1
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+set_option -bit_compress 0
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+set_option -bit_encrypt 0
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+set_option -bit_encrypt_key 00000000000000000000000000000000
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+set_option -bit_security 1
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+set_option -bit_incl_bsram_init 1
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+set_option -bg_programming off
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+set_option -hotboot 0
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+set_option -i2c_slave_addr 00
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+set_option -secure_mode 0
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+set_option -loading_rate default
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+set_option -program_done_bypass 0
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+set_option -wakeup_mode 0
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+set_option -user_code default
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+set_option -unused_pin default
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+set_option -multi_boot 1
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+set_option -multiboot_address_width 24
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+set_option -multiboot_mode normal
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+set_option -multiboot_spi_flash_address 00000000
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+set_option -mspi_jump 0
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+set_option -turn_off_bg 0
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+set_option -vccx 3.3
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+set_option -seu_handler 0
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+set_option -seu_handler_checksum 0
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+set_option -seu_handler_mode auto
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+set_option -error_detection false
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+set_option -error_detection_correction false
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+set_option -stop_seu_handler false
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+set_option -error_injection false
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+set_option -ext_cclk false
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+set_option -ext_cclk_div
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Mihail Zaytsev