Merge branch 'Stepan/Feature_InterfaceArbiter' of zaytsev.mikhail/SB_TMSG44V1_FPGA into dev

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src/src/InterfaceArbiter/InterfaceArbiter.v

@@ -0,0 +1,259 @@
+`timescale 1ns / 1ps
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company: Tair
+// Engineer: Churbanov S.
+// 
+// Create Date:     
+// Design Name: 
+// Module Name:    InterfaceArbiter
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module InterfaceArbiter 
+#(	
+	parameter OutWordWith = 24,
+	parameter SingleSpiWordWith = 24,
+	parameter QuadSpiWordWith = 6
+)
+(
+	input Rst_i,
+	input Clk_i,
+	
+	input Sck_i,
+	input Ss_i,
+	
+	input Mosi0_i,
+	input Mosi1_i,
+	input Mosi2_i,
+	input Mosi3_i,
+	
+	
+	input DataVal_o,
+	input [OutWordWith-1:0] Data_o
+);
+
+//================================================================================
+//  REG/WIRE
+
+	localparam [1:0] IDLE = 0;
+	localparam [1:0] DATARX = 1;
+	
+	reg [OutWordWith-1:0] dataRegSSpi;
+	reg [OutWordWith-1:0] dataRegQSpi;
+	
+	reg [OutWordWith-1:0] captRegSspi;
+	
+	reg [QuadSpiWordWith-1:0] captReg0;
+	reg [QuadSpiWordWith-1:0] captReg1;
+	reg [QuadSpiWordWith-1:0] captReg2;
+	reg [QuadSpiWordWith-1:0] captReg3;
+	
+	reg ssReg;
+	reg ssRegR;
+	reg ssRegRR;
+	
+	reg spiMode;
+	
+	wire ssPos;
+	reg ssPosR;
+	
+	reg dataValReg;
+	
+	reg [OutWordWith/4-1:0] ssCnt;
+	reg [OutWordWith/4-1:0] wordsCnt;
+	wire [OutWordWith/4-1:0] ssCntRstThresh = (spiMode) ? QuadSpiWordWith-1:SingleSpiWordWith-1;
+	
+	reg [16:0] wordsNum;
+	
+	reg [1:0] nextState;
+	reg [1:0] currState;
+	
+	reg rxDone;
+//================================================================================
+//  ASSIGNMENTS
+	assign ssPos = ssRegR & !ssRegRR;
+
+	
+	assign DataVal_o = dataValReg;
+	assign Data_o = (spiMode)? dataRegQSpi:dataRegSSpi;
+	
+//================================================================================
+//  CODING
+	always @(posedge Sck_i) begin
+		if (!Rst_i) begin
+			if (!Ss_i) begin
+				captRegSspi <= {captRegSspi[OutWordWith-2:0], Mosi0_i};
+				
+				captReg0 <= {captReg0[QuadSpiWordWith-2:0], Mosi0_i};
+				captReg1 <= {captReg1[QuadSpiWordWith-2:0], Mosi1_i};
+				captReg2 <= {captReg2[QuadSpiWordWith-2:0], Mosi2_i};
+				captReg3 <= {captReg3[QuadSpiWordWith-2:0], Mosi3_i};
+			end
+		end else begin
+			captRegSspi <= 0;
+				
+			captReg0 <= 0;
+			captReg1 <= 0;
+			captReg2 <= 0;
+			captReg3 <= 0;
+		end
+	end
+	
+	always @(posedge Sck_i) begin
+		if (!Rst_i) begin
+			if (!Ss_i) begin
+				if (ssCnt == ssCntRstThresh) begin
+					ssCnt <= 0;
+				end else begin
+					ssCnt <= ssCnt+1;
+				end
+			end
+		end else begin
+			ssCnt <= 0;
+		end
+	end
+	
+	always @(posedge Clk_i) begin
+		if (!Rst_i) begin
+			if (currState == DATARX) begin
+				if (ssPos) begin
+					if (wordsCnt == wordsNum-1) begin
+						wordsCnt <= 0;
+						rxDone <= 1'b1;
+					end else begin
+						wordsCnt <= wordsCnt+1;
+						rxDone <= 1'b0;
+					end
+				end
+			end else begin
+				wordsCnt <= 0;
+				rxDone <= 1'b0;
+			end
+		end else begin
+			wordsCnt <= 0;
+			rxDone <= 1'b0;
+		end
+	end
+	
+	always @(posedge Clk_i) begin
+		if (!Rst_i) begin
+			if (currState == IDLE) begin
+				if (ssCnt == 1) begin
+					if (captRegSspi[0]) begin
+						spiMode <= 1'b1;	//quad
+					end else begin
+						spiMode <= 1'b0;	//single
+					end
+				end
+			end
+		end else begin
+			spiMode <= 1'b0;
+		end
+	end 
+	
+	always @(posedge Clk_i) begin
+		if (!Rst_i) begin
+			if (currState == IDLE) begin
+				// if (ssPos) begin
+					if (!spiMode) begin
+						wordsNum <= dataRegSSpi[17:1];
+					end else begin
+						wordsNum <= dataRegQSpi[22:19]+dataRegQSpi[18:17]+dataRegQSpi[16]+dataRegQSpi[15]+dataRegQSpi[14]+dataRegQSpi[13:12]+dataRegQSpi[11:9]+dataRegQSpi[8:7];
+					end 
+				// end
+			end
+		end else begin
+			wordsNum <= 0;
+		end
+	end 
+	
+	always @(posedge Clk_i) begin
+		if (!Rst_i) begin
+			ssReg <= Ss_i;
+			ssRegR <= ssReg;
+			ssRegRR <= ssRegR;
+			ssPosR <= ssPos;
+		end else begin
+			ssReg <= 1;
+			ssRegR <= 1;
+			ssRegRR <= 1;
+			ssPosR <= 0;
+		end
+	end 
+	
+	always @(posedge Clk_i) begin
+		if (!Rst_i) begin
+			if (ssPos) begin
+				dataRegSSpi <= captRegSspi;
+				dataRegQSpi <= {captReg0,captReg1,captReg2,captReg3};
+				dataValReg <= 1'b1;
+			end else begin
+				dataValReg <= 1'b0;
+			end
+		end else begin
+			dataRegSSpi <= 0;
+			dataRegQSpi <= 0;
+			dataValReg <= 0;
+		end
+	end
+
+	always	@(posedge	Clk_i)	begin
+		if	(Rst_i)	begin
+			currState	<=	IDLE;
+		end	else	begin
+			currState	<=	nextState;
+		end
+	end
+
+	always @(*) begin
+		nextState	=	IDLE;
+		case(currState)
+		IDLE		:begin
+						if (ssPosR)	begin
+							nextState = DATARX;
+						end	else begin
+							nextState = IDLE;
+						end
+					end
+
+		DATARX		:begin
+						if (rxDone) begin
+							nextState  = IDLE;
+						end	else begin
+							nextState  = DATARX;
+						end
+					end
+		endcase
+	end
+
+endmodule
+
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+

src/src/InterfaceArbiter/InterfaceArbiterTb.v

@@ -0,0 +1,266 @@
+`timescale 1ns / 1ps
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company: Tair
+// Engineer: Churbanov S.
+// 
+// Create Date:     
+// Design Name: 
+// Module Name:    InterfaceArbiter
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module InterfaceArbiterTb();
+
+//================================================================================
+//  REG/WIRE
+	
+	parameter OutWordWith = 24;
+	parameter SingleSpiWordWith = 24;
+	parameter QuadSpiWordWith = 6;
+	
+	localparam [1:0] IDLE = 0;
+	localparam [1:0] SINGLE = 1;
+	localparam [1:0] DELAY = 2;
+	localparam [1:0] QUAD = 3;
+	
+	reg SPIMODE = 1'b0; //0 - single 1- quad
+	
+	reg [31:0] tbCnt;
+	reg [31:0] delCnt;
+	reg stateCnt;
+	
+	reg Clk100;
+	reg Clk10;
+	
+	reg [1:0] currState;
+	reg [1:0] nextState;
+	
+	reg rst;
+	
+	wire txStart = (tbCnt == 100 | tbCnt == 3000);
+	wire txDoneS;
+	wire txDoneQ;
+	
+	
+	wire sckS;
+	wire sckQ;
+	wire ssS;
+	wire ssQ;
+	
+	wire ss;
+	wire sck;
+	
+	wire mosi0S;
+	wire mosi0Q;
+	wire mosi1Q;
+	wire mosi2Q;
+	wire mosi3Q;
+	
+	wire delDone = (delCnt == 500);
+//================================================================================
+//  ASSIGNMENTS
+	
+	assign sck = (currState==SINGLE) ? sckS:sckQ;
+	assign ss = (currState==SINGLE) ? ssS:ssQ;
+	assign mosi0 = (currState==SINGLE) ? mosi0S:mosi0Q;
+	assign mosi1 = (currState==SINGLE) ? 1'b1:mosi1Q;
+	assign mosi2 = (currState==SINGLE) ? 1'b1:mosi2Q;
+	assign mosi3 = (currState==SINGLE) ? 1'b1:mosi3Q;
+//================================================================================
+//clocks gen
+	always	#5 Clk100	=	~Clk100;	
+	always	#50 Clk10	=	~Clk10;	
+	
+	
+//================================================================================
+//  CODING
+
+initial begin
+	Clk100	=	1'b1;
+	Clk10	=	1'b1;
+	rst		=	1'b1;
+#100;
+	rst		=	1'b0;
+end	
+	
+always	@(negedge	Clk100)	begin
+	if	(!rst)		begin
+		tbCnt	<=	tbCnt+1;
+	end	else	begin
+		tbCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk100)	begin
+	if	(!rst)		begin
+		if (currState == DELAY) begin
+			delCnt	<=	delCnt+1;
+		end	else	begin
+			delCnt	<=	0;
+		end
+	end else	begin
+		delCnt	<=	0;
+	end
+end
+
+always	@(negedge	Clk10)	begin
+	if	(!rst)		begin
+		if (txDoneS|txDoneQ) begin
+			stateCnt	<=	stateCnt+1;
+		end	
+	end else begin
+		stateCnt <= 0;
+	end
+end
+
+always	@(posedge	Clk100)	begin
+	if	(!rst)		begin
+		case (stateCnt)
+			0:	begin
+					SPIMODE <= 1'b0;
+				end
+			1:	begin
+					SPIMODE <= 1'b1;
+				end
+			default:begin
+						SPIMODE <= 1'b0;
+					end
+		endcase
+	end else begin
+		SPIMODE <= 1'b0;
+	end
+end
+
+always	@(posedge	Clk100)	begin
+	if	(rst)	begin
+		currState	<=	IDLE;
+	end	else	begin
+		currState	<=	nextState;
+	end
+end
+
+
+always @(*) begin
+	nextState	=	IDLE;
+	case(currState)
+	IDLE	:	begin
+					if (txStart)	begin
+						case (SPIMODE)
+							1'b0:	begin
+											nextState = SINGLE;
+										end
+							1'b1:		begin
+											nextState = QUAD;
+										end
+						endcase
+					end	else begin
+						nextState = IDLE;
+					end
+				end
+				
+	SINGLE	:	begin
+					if (txDoneS)	begin
+						nextState = DELAY;
+					end	else begin
+						nextState = SINGLE;
+					end
+				end
+				
+	DELAY	:	begin
+					if (delDone)	begin
+						nextState = QUAD;
+					end	else begin
+						nextState = DELAY;
+					end
+				end
+				
+	QUAD		:	begin
+					if (txDoneQ) begin
+						nextState  = IDLE;
+					end	else begin
+						nextState  = QUAD;
+					end
+				end
+	endcase
+end
+
+SingleSm SingleSpiSm
+(
+	.Rst_i		(rst),
+	.Clk_i		(Clk10),
+	
+	.Start_i	((currState==SINGLE)),
+	.TxDone_o	(txDoneS),
+	
+	.Sck_o		(sckS),
+	.Ss_o		(ssS),
+	.Mosi_o		(mosi0S)
+	
+);
+
+QuadSm QuadSpiSm
+(
+	.Rst_i		(rst),
+	.Clk_i		(Clk10),
+	
+	.Start_i	((currState==QUAD)),
+	.TxDone_o	(txDoneQ),
+	
+	.Sck_o		(sckQ),
+	.Ss_o		(ssQ),
+	.Mosi0_o	(mosi0Q),
+	.Mosi1_o	(mosi1Q),
+	.Mosi2_o	(mosi2Q),
+	.Mosi3_o	(mosi3Q)
+	
+);
+
+InterfaceArbiter InterfaceArbiter
+(
+	.Rst_i		(rst),
+	.Clk_i		(Clk100),
+	
+	.Sck_i		(sck),
+	.Ss_i		(ss),
+	
+	.Mosi0_i	(mosi0),
+	.Mosi1_i	(mosi1),
+	.Mosi2_i	(mosi2),
+	.Mosi3_i	(mosi3),
+	
+	
+	.DataVal_o	(),
+	.Data_o		()
+);
+
+endmodule
+
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+

src/src/InterfaceArbiter/QuadSm.v

@@ -0,0 +1,233 @@
+`timescale 1ns / 1ps
+
+module QuadSm 
+(
+	input Rst_i,
+	input Clk_i,
+	
+	input Start_i,
+	output TxDone_o,
+	
+	output Sck_o,
+	output reg Ss_o,
+	output reg Mosi0_o,
+	output reg Mosi1_o,
+	output reg Mosi2_o,
+	output reg Mosi3_o
+);
+
+//================================================================================
+//  PARAMETERS
+	localparam [1:0] IDLE = 0;
+	localparam [1:0] CMD = 1;
+	localparam [1:0] TX = 2;
+	localparam [1:0] PAUSE = 3;
+
+	parameter MODE = 1'h1;
+	parameter [3:0] LMX = 4'h1;
+	parameter [1:0] DDS = 2'h1;
+	parameter POT = 1'h1;
+	parameter DAC = 1'h1;
+	parameter ATT = 1'h1;
+	parameter [1:0] SHREG = 2'h1;
+	parameter [2:0] MAX2870 = 3'h1;
+	parameter [1:0] GPIO = 2'h1;
+	parameter [5:0] RESERVED = 6'h1;
+	parameter EOPBIT = 1'b1;
+	
+//================================================================================
+//  REG/WIRE
+	reg [1:0] currState;
+	reg [1:0] nextState;
+	
+	reg	[6:0]	txCnt;
+	reg	[6:0]	cmdCnt;
+	reg	[3:0]	pauseCnt;
+
+	wire	txStop	=	(cmdCnt	>=	LMX+DDS+POT+DAC+ATT+SHREG+MAX2870+GPIO+1);
+	
+	reg [23:0] headerCmd = {MODE,LMX,DDS,POT,DAC,ATT,SHREG,MAX2870,GPIO,RESERVED,EOPBIT};
+	reg [23:0] spiData;
+	
+	reg	[23:0]	dspSpiData;
+	
+	reg sckFlag;
+//================================================================================
+//  ASSIGNMENTS
+
+assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b1;
+assign	TxDone_o	=	(txStop & (currState== CMD));
+
+//================================================================================
+//  CODING
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	CMD)	begin
+			if	(!txStop)	begin
+				cmdCnt	<=	cmdCnt+1;
+			end else begin
+				cmdCnt <= 0;
+			end
+		end
+	end	else	begin
+		cmdCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	TX)	begin
+			txCnt	<=	txCnt+1;
+		end	else	begin
+			txCnt	<=	0;
+		end
+	end	else	begin
+		txCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	PAUSE)	begin
+			pauseCnt	<=	pauseCnt+1;
+		end	else	begin
+			pauseCnt	<=	0;
+		end
+	end	else	begin
+		pauseCnt	<=	0;
+	end
+end
+	
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	CMD)	begin
+			spiData	<=	spiData+cmdCnt;
+		end
+	end	else	begin
+		spiData	<=	24'hab;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(currState	==	CMD)	begin
+		if	(cmdCnt	==	0)	begin
+			dspSpiData		<=	headerCmd;
+		end	else	begin
+			dspSpiData		<=	spiData;
+		end	
+	end	else	if	(currState	==	TX)	begin
+		dspSpiData	<=	dspSpiData<<1;
+	end if	(currState	==	IDLE)	begin
+		dspSpiData	<=	0;
+	end
+end
+
+always	@(posedge Clk_i)	begin
+	if	(currState	==	TX)	begin
+		if	(txCnt	>=	7'd0)	begin
+			Mosi0_o	<=	dspSpiData[23];
+			Mosi1_o	<=	dspSpiData[17];
+			Mosi2_o	<=	dspSpiData[11];
+			Mosi3_o	<=	dspSpiData[5];
+		end	else	begin
+			Mosi0_o	<=	1'b1;
+			Mosi1_o	<=	1'b1;
+			Mosi2_o	<=	1'b1;
+			Mosi3_o	<=	1'b1;
+		end
+	end	else	begin
+		Mosi0_o	<=	1'b1;
+		Mosi1_o	<=	1'b1;
+		Mosi2_o	<=	1'b1;
+		Mosi3_o	<=	1'b1;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(currState	==	TX)	begin
+		Ss_o	<=	1'b0;
+		sckFlag	<=	1'b1;
+	end	else	begin
+		Ss_o	<=	1'b1;
+		sckFlag	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(Rst_i)	begin
+		currState	<=	IDLE;
+	end	else	begin
+		currState	<=	nextState;
+	end
+end
+
+
+always	@(posedge	Clk_i)	begin
+	if	(Rst_i)	begin
+		currState	<=	IDLE;
+	end	else	begin
+		currState	<=	nextState;
+	end
+end
+
+
+always @(*) begin
+	nextState	=	IDLE;
+	case(currState)
+	IDLE	:	begin
+					if (Start_i)	begin
+						nextState = CMD;
+					end	else begin
+						nextState = IDLE;
+					end
+				end
+				
+	CMD	:		begin
+					if (!txStop)	begin
+						nextState = TX;
+					end	else begin
+						nextState = IDLE;
+					end
+				end
+
+	TX		:	begin
+					if (txCnt==6'd5) begin
+						nextState  = PAUSE;
+					end	else begin
+						nextState  = TX;
+					end
+				end
+        
+	PAUSE	:	begin
+					if (pauseCnt==4'd2) begin
+						nextState  = CMD;
+					end	else begin
+						nextState  = PAUSE;
+					end
+				end
+	endcase
+end
+
+
+
+endmodule
+
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+

src/src/InterfaceArbiter/SingleSm.v

@@ -0,0 +1,205 @@
+`timescale 1ns / 1ps
+
+module SingleSm 
+(
+	input Rst_i,
+	input Clk_i,
+	
+	input Start_i,
+	output TxDone_o,
+	
+	output Sck_o,
+	output reg Ss_o,
+	output reg Mosi_o
+	
+);
+
+//================================================================================
+//  PARAMETERS
+	localparam [1:0] IDLE = 0;
+	localparam [1:0] CMD = 1;
+	localparam [1:0] TX = 2;
+	localparam [1:0] PAUSE = 3;
+
+	parameter MODE = 1'h0;
+	parameter [4:0] DEVID = 5'h1;
+	parameter [16:0] WORDSNUM = 17'h3;
+	parameter EOPBIT = 1'b1;
+	
+//================================================================================
+//  REG/WIRE
+	reg [1:0] currState;
+	reg [1:0] nextState;
+	
+	reg	[6:0]	txCnt;
+	reg	[6:0]	cmdCnt;
+	reg	[3:0]	pauseCnt;
+
+	wire	txStop	=	(cmdCnt	>=	WORDSNUM+1);
+	
+	reg [23:0] headerCmd = {MODE,DEVID,WORDSNUM,EOPBIT};
+	reg [23:0] spiData;
+	
+	reg	[23:0]	dspSpiData;
+	
+	reg sckFlag;
+//================================================================================
+//  ASSIGNMENTS
+
+assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b1;
+assign	TxDone_o	=	(txStop & (currState== CMD));
+
+//================================================================================
+//  CODING
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	CMD)	begin
+			if	(!txStop)	begin
+				cmdCnt	<=	cmdCnt+1;
+			end else begin
+				cmdCnt <= 0;
+			end
+		end
+	end	else	begin
+		cmdCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	TX)	begin
+			txCnt	<=	txCnt+1;
+		end	else	begin
+			txCnt	<=	0;
+		end
+	end	else	begin
+		txCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	PAUSE)	begin
+			pauseCnt	<=	pauseCnt+1;
+		end	else	begin
+			pauseCnt	<=	0;
+		end
+	end	else	begin
+		pauseCnt	<=	0;
+	end
+end
+	
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	CMD)	begin
+			spiData	<=	spiData+cmdCnt;
+		end
+	end	else	begin
+		spiData	<=	24'hab;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(currState	==	CMD)	begin
+		if	(cmdCnt	==	0)	begin
+			dspSpiData		<=	headerCmd;
+		end	else	begin
+			dspSpiData		<=	spiData;
+		end	
+	end	else	if	(currState	==	TX)	begin
+		dspSpiData	<=	dspSpiData<<1;
+	end if	(currState	==	IDLE)	begin
+		dspSpiData	<=	0;
+	end
+end
+
+always	@(posedge Clk_i)	begin
+	if	(currState	==	TX)	begin
+		if	(txCnt	>=	7'd0)	begin
+			Mosi_o	<=	dspSpiData[23];
+		end	else	begin
+			Mosi_o	<=	1'b1;
+		end
+	end	else	begin
+		Mosi_o	<=	1'b1;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(currState	==	TX)	begin
+		Ss_o	<=	1'b0;
+		sckFlag	<=	1'b1;
+	end	else	begin
+		Ss_o	<=	1'b1;
+		sckFlag	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(Rst_i)	begin
+		currState	<=	IDLE;
+	end	else	begin
+		currState	<=	nextState;
+	end
+end
+
+always @(*) begin
+	nextState	=	IDLE;
+	case(currState)
+	IDLE	:	begin
+					if (Start_i)	begin
+						nextState = CMD;
+					end	else begin
+						nextState = IDLE;
+					end
+				end
+				
+	CMD	:		begin
+					if (!txStop)	begin
+						nextState = TX;
+					end	else begin
+						nextState = IDLE;
+					end
+				end
+
+	TX		:	begin
+					if (txCnt==6'd23) begin
+						nextState  = PAUSE;
+					end	else begin
+						nextState  = TX;
+					end
+				end
+        
+	PAUSE	:	begin
+					if (pauseCnt==4'd2) begin
+						nextState  = CMD;
+					end	else begin
+						nextState  = PAUSE;
+					end
+				end
+	endcase
+end
+
+
+
+endmodule
+
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