Добавлена папка WrapFifoChain, в которую перемещены файлы для FIFO и обёртки. Актуализирован top-модуль и тестбенч.

src/src/Top/ExtSpiMEmul.v

@@ -1,205 +1,536 @@
-`timescale 1ns / 1ps
-
-module ExtSpiMEmul 
-(
-	input Rst_i,
-	input Clk_i,
-	
-	input Start_i,
-	output TxDone_o,
-	
-	output Sck_o,
-	output reg Ss_o,
-	output reg Mosi_o
-	
+module ExtSpiMEmul (
+    input Clk_i,
+    input Rst_i,
+    input Start_i,
+    input EmptyFlag_i,
+    input ClockPhase_i,
+    input [31:0] SpiData_i,
+    input SelSt_i,
+    input [1:0] WidthSel_i,
+    input  Lag_i,
+    input  Lead_i,
+    input EndianSel_i,
+    input [5:0] Stop_i,
+    input PulsePol_i,
+
+
+    output reg Mosi0_o,
+    output reg Sck_o,
+    output  Ss_o,
+    output reg  Val_o
 );
 
-//================================================================================
-//  PARAMETERS
-	localparam [1:0] IDLE = 0;
-	localparam [1:0] CMD = 1;
-	localparam [1:0] TX = 2;
-	localparam [1:0] PAUSE = 3;
 
-	parameter MODE = 1'h0;
-	parameter [4:0] DEVID = 5'h1;
-	parameter [16:0] WORDSNUM = 17'd24;
-	parameter EOPBIT = 1'b1;
-	
 //================================================================================
-//  REG/WIRE
-	reg [1:0] currState;
-	reg [1:0] nextState;
-	
-	reg	[6:0]	txCnt;
-	reg	[6:0]	cmdCnt;
-	reg	[3:0]	pauseCnt;
-
-	wire	txStop	=	(cmdCnt	>=	WORDSNUM+1);
-	
-	reg [23:0] headerCmd = {MODE,DEVID,WORDSNUM,EOPBIT};
-	reg [23:0] spiData;
-	
-	reg	[23:0]	dspSpiData;
-	
-	reg sckFlag;
+//	REG/WIRE
 //================================================================================
-//  ASSIGNMENTS
-
-assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b0;
-assign	TxDone_o	=	(txStop & (currState== CMD));
-
-//================================================================================
-//  CODING
-
-always	@(posedge	Clk_i)	begin
-	if	(!Rst_i)	begin
-		if	(currState	==	CMD)	begin
-			if	(!txStop)	begin
-				cmdCnt	<=	cmdCnt+1;
-			end else begin
-				cmdCnt <= 0;
-			end
-		end
-	end	else	begin
-		cmdCnt	<=	0;
-	end
-end
-
-always	@(posedge	Clk_i)	begin
-	if	(!Rst_i)	begin
-		if	(currState	==	TX)	begin
-			txCnt	<=	txCnt+1;
-		end	else	begin
-			txCnt	<=	0;
-		end
-	end	else	begin
-		txCnt	<=	0;
-	end
-end
-
-always	@(posedge	Clk_i)	begin
-	if	(!Rst_i)	begin
-		if	(currState	==	PAUSE)	begin
-			pauseCnt	<=	pauseCnt+1;
-		end	else	begin
-			pauseCnt	<=	0;
-		end
-	end	else	begin
-		pauseCnt	<=	0;
-	end
-end
-	
-always	@(posedge	Clk_i)	begin
-	if	(!Rst_i)	begin
-		if	(currState	==	CMD)	begin
-			spiData	<=	spiData+cmdCnt;
-		end
-	end	else	begin
-		spiData	<=	24'hab;
-	end
-end
-
-always	@(posedge	Clk_i)	begin
-	if	(currState	==	CMD)	begin
-		if	(cmdCnt	==	0)	begin
-			dspSpiData		<=	headerCmd;
-		end	else	begin
-			dspSpiData		<=	spiData;
-		end	
-	end	else	if	(currState	==	TX)	begin
-		dspSpiData	<=	dspSpiData<<1;
-	end if	(currState	==	IDLE)	begin
-		dspSpiData	<=	0;
-	end
-end
-
-always	@(posedge Clk_i)	begin
-	if	(currState	==	TX)	begin
-		if	(txCnt	>=	7'd0)	begin
-			Mosi_o	<=	dspSpiData[23];
-		end	else	begin
-			Mosi_o	<=	1'b0;
-		end
-	end	else	begin
-		Mosi_o	<=	1'b0;
-	end
-end
-
-always	@(posedge	Clk_i)	begin
-	if	(currState	==	TX)	begin
-		Ss_o	<=	1'b0;
-		sckFlag	<=	1'b1;
-	end	else	begin
-		Ss_o	<=	1'b1;
-		sckFlag	<=	1'b0;
-	end
-end
-
-always	@(posedge	Clk_i)	begin
-	if	(Rst_i)	begin
-		currState	<=	IDLE;
-	end	else	begin
-		currState	<=	nextState;
-	end
-end
-
-always @(*) begin
-	nextState	=	IDLE;
-	case(currState)
-	IDLE	:	begin
-					if (Start_i)	begin
-						nextState = CMD;
-					end	else begin
-						nextState = IDLE;
-					end
-				end
-				
-	CMD	:		begin
-					if (!txStop)	begin
-						nextState = TX;
-					end	else begin
-						nextState = IDLE;
-					end
-				end
-
-	TX		:	begin
-					if (txCnt==6'd23) begin
-						nextState  = PAUSE;
-					end	else begin
-						nextState  = TX;
-					end
-				end
-        
-	PAUSE	:	begin
-					if (pauseCnt==4'd2) begin
-						nextState  = CMD;
-					end	else begin
-						nextState  = PAUSE;
-					end
-				end
-	endcase
-end
-
-
-
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
 
+    reg startFlag;
+    reg startR;
+    reg [31:0] trCnt;
+    reg valReg;
+    reg valToRxFifo1;
+    reg lineBusy;
+    reg [5:0] ssCnt;
+    reg Ss;
+    reg [31:0]spiDataR;
+    reg oldDataFlag;
+    
+    reg ssR;
+    reg SSR;
+    reg [31:0] mosiReg0;
+    reg [5:0] ssNum;
+    reg [2:0] delayCnt;
+    reg stopFlag;
+    
+    wire ssPol = SelSt_i ? Ss : ~Ss;
+    
+    
+    //================================================================================
+    //  ASSIGNMENTS
+    //================================================================================
+    
+    
+    assign Ss_o = ssPol; 
+    
+    //================================================================================
+    //	CODING
+    //================================================================================
+    
+    always @(*) begin 
+        if (Start_i) begin  
+            Val_o = valReg;
+        end
+        else begin 
+            Val_o = 1'b0;
+        end
+    end
+    
+    
+    always @(*) begin 
+        if (SelSt_i) begin 
+            if (!Ss_o) begin 
+                lineBusy = 1'b1;
+            end
+            else begin 
+                lineBusy = 1'b0;
+            end
+        end
+        else begin 
+            if (Ss_o) begin 
+                lineBusy = 1'b1;
+            end
+            else begin 
+                lineBusy = 1'b0;
+            end
+        end
+    end
+    
+    
+    
+    always @(posedge Clk_i) begin
+        if (valReg) begin  
+            spiDataR <= SpiData_i;
+        end
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            oldDataFlag = 1'b0;
+        end
+        else begin 
+            if (spiDataR == SpiData_i && (SpiData_i != 0) || EmptyFlag_i) begin 
+                oldDataFlag = 1'b1;
+            end
+            else begin 
+                oldDataFlag = 1'b0;
+            end
+        end
+    end
+    
+    
+    always @(posedge Clk_i) begin 
+        startR <= Start_i;
+    end
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            valToRxFifo1 = 1'b0;
+        end
+        else begin 
+            if (Start_i && !startR) begin 
+                valToRxFifo1 = 1'b1;
+            end
+            else begin 
+                valToRxFifo1 = 1'b0;
+            end
+        end
+    end
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            delayCnt <= 1'b0;
+        end
+        else begin 
+            if (stopFlag &&delayCnt < Stop_i) begin 
+                delayCnt <= delayCnt + 1'b1;
+            end
+            else begin 
+                delayCnt <= 1'b0;
+            end
+        end
+    end
+    
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            stopFlag <= 1'b0;
+        end
+        else begin
+            if (SelSt_i) begin 
+                if (ssPol && !ssR) begin 
+                    stopFlag <= 1'b1;
+                end
+                else if ( delayCnt == Stop_i) begin 
+                    stopFlag <= 1'b0;
+                end
+            end
+            else begin 
+                if (!ssPol && ssR) begin 
+                    stopFlag <= 1'b1;
+                end
+                else if (delayCnt == Stop_i) begin 
+                    stopFlag <= 1'b0;
+                end
+            end
+        end
+    end
+    
+    
+    
+    
+    always @(*) begin
+        if (SelSt_i) begin 
+            if (PulsePol_i) begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt < ssNum+Lag_i+Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+            else begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin  
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt <ssNum + Lag_i + Lag_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end 
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (!Ss && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (!Ss && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+        end
+        else begin 
+              if (PulsePol_i) begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt < ssNum+Lag_i+Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+            else begin 
+                if (ClockPhase_i) begin
+                    if (Lead_i == 0) begin  
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt <ssNum + Lag_i + Lag_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end 
+                else begin
+                    if (Lead_i == 0) begin 
+                        if (ssPol && (ssCnt <= ssNum+Lag_i+Lead_i && ssCnt > Lag_i) ) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                    else begin 
+                        if (ssPol && (ssCnt < ssNum + Lag_i + Lead_i && ssCnt > Lag_i)) begin 
+                            Sck_o = ~(~Clk_i);
+                        end
+                        else begin 
+                            Sck_o = 1'b0;
+                        end
+                    end
+                end
+            end
+        end
+            
+    end
+    
+    
+    always @(*) begin
+        if (Rst_i) begin 
+            Mosi0_o = 1'b0;
+        end
+        else begin
+            if (SelSt_i) begin 
+                if (!EndianSel_i) begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[7]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[15]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[23]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[31]):1'b0;
+                        end
+                    endcase
+                end
+                else begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (!Ss&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                    endcase
+                end
+            end
+            else begin 
+                if (!EndianSel_i) begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[7]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[15]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[23]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[31]):1'b0;
+                        end
+                    endcase
+                end
+                else begin 
+                    case (WidthSel_i)  
+                        0 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        1 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        2 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                        3 : begin
+                            Mosi0_o = (ssPol&& (ssCnt <= ssNum+Lag_i && ssCnt > Lag_i))? (mosiReg0[0]):1'b0;
+                        end
+                    endcase
+                end
+            end
+        end
+    end
+    
+    
+    
+    always @(posedge Clk_i) begin
+        ssR <= ssPol;
+        SSR <= Ss;
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            startFlag = 1'b0;
+        end
+        else begin 
+            if (Start_i && !stopFlag && !EmptyFlag_i) begin 
+                startFlag = 1'b1;
+            end
+            else begin 
+                startFlag = 1'b0;
+            end
+        end
+    end
+    
+    always @(*) begin
+        if (SelSt_i) begin 
+            if (Ss_o && !ssR) begin 
+                valReg = 1'b1;
+            end
+            else begin 
+                valReg = 1'b0;
+            end
+        end
+        else begin 
+            if (!Ss_o&& ssR) begin 
+                valReg = 1'b1;
+            end
+            else begin 
+                valReg = 1'b0;
+            end
+        end
+    end
+    
+    
+    always @(*) begin 
+        if (Rst_i) begin 
+            ssNum = 1'b0;
+        end
+        else begin 
+            case (WidthSel_i) 
+                0 : begin 
+                    ssNum = 8;
+                end
+                1 : begin 
+                    ssNum = 16;
+                end
+                2 : begin 
+                    ssNum = 24;
+                end
+                3 : begin 
+                    ssNum = 32;
+                end
+            endcase
+        end
+    end
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            ssCnt <= 1'b0;
+        end
+        else if (ssCnt <= (ssNum+Lag_i+Lead_i)  && startFlag  ) begin 
+            ssCnt <= ssCnt + 1'b1;
+        end
+        else begin
+            if (ssCnt == ssNum-1 || !startFlag) begin 
+                ssCnt <= 1'b0;
+            end
+        end
+    end
+    
+    
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            Ss <= 1'b1;
+        end
+        else begin 
+            if (ssCnt <= (ssNum+Lag_i+Lead_i)  && startFlag ) begin 
+                Ss <= 1'b0;
+            end
+            else begin 
+                Ss <= 1'b1;
+            end
+        end
+    end
+    
+    
+    always @(negedge Clk_i) begin 
+        if (Rst_i) begin 
+            mosiReg0 <= SpiData_i[31:0];
+        end
+        else begin
+            if (!EndianSel_i) begin 
+                if (!SSR && (ssCnt > Lag_i && ssCnt < ssNum + Lag_i + Lead_i)) begin
+                    mosiReg0 <= mosiReg0 << 1;
+                end
+                else begin 
+                    mosiReg0 <= SpiData_i[31:0];
+                end
+            end
+            else begin 
+                if (!SSR && (ssCnt > Lag_i && ssCnt < ssNum + Lag_i + Lead_i)) begin
+                    mosiReg0 <= mosiReg0 >> 1;
+                end
+                else begin 
+                    mosiReg0 <= SpiData_i[31:0];
+                end
+            end
+        end
+    end
+    
+    
+    
+    
+    
+    
+    
+    endmodule

src/src/Top/TopSbTmsg.v

@@ -184,6 +184,118 @@ PacketAnalyzer1Mosi	PacketAnalyzer1Mosi
 	.Busy_o					(busyMosi1)
 );
 
+LmxWrapper #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(24),
+	.DATA_WIDTH		(24)
+) LmxWrapper_inst(
+	.WrClk_i		(gclk100),
+	.RdClk_i		(clk60),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valLmxDataToFifo),
+	.Ss_o			(),
+	.Sck_o			(),
+	.Mosi_o			()
+);
+
+DDSWrapper #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(3),
+	.OUT_WIDTH		(64),
+	.DATA_WIDTH		(64)
+) DDSWrapper_inst(
+	.WrClk_i		(gclk100),
+	.RdClk_i		(clk50),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valDdsDataToFifo),
+	.Ss_o			(),
+	.Sck_o			(),
+	.Mosi_o			()
+);
+
+PotWrapper #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(16),
+	.DATA_WIDTH		(16)
+) PotWrapper_inst(
+	.WrClk_i		(gclk100),
+	.RdClk_i		(clk5),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valPotDataToFifo),
+	.Ss_o			(),
+	.Sck_o			(),
+	.Mosi_o			()
+);
+
+DacWrapper #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(16),
+	.DATA_WIDTH		(16)
+) DacWrapper_inst(
+	.WrClk_i		(gclk100),
+	.RdClk_i		(clk50),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valDacDataToFifo),
+	.Ss_o			(),
+	.Sck_o			(),
+	.Mosi_o			()
+);
+
+AttenuatorWrapper #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(16),
+	.DATA_WIDTH		(16)
+) AttenuatorWrapper_inst(
+	.WrClk_i		(gclk100),
+	.RdClk_i		(clk50),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valAttDataToFifo),
+	.Ss_o			(),
+	.Sck_o			(),
+	.Mosi_o			()
+);
+
+ShiftRegWrapper #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(8),
+	.DATA_WIDTH		(8)
+) ShRegWrapper_inst(
+	.WrClk_i		(gclk100),
+	.RdClk_i		(clk26dot25),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valShRegDataToFifo),
+	.Ss_o			(),
+	.Sck_o			(),
+	.Mosi_o			()
+);
+
+Max2870Wrapper #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(24),
+	.DATA_WIDTH		(24)
+) Max2870Wrapper_inst(
+	.WrClk_i		(gclk100),
+	.RdClk_i		(clk20),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valMaxDataToFifo),
+	.Ss_o			(),
+	.Sck_o			(),
+	.Mosi_o			()
+);
+
 GpioCtrl GpioCtrl
 (
 	.Clk_i					(gclk100),
@@ -196,4 +308,4 @@ GpioCtrl GpioCtrl
 );
 
 
-endmodule
+endmodule

src/src/Top/TopSbTmsgTb.sv

@@ -0,0 +1,335 @@
+`timescale 1ns/1ps
+
+module TopSbTmsgTb;
+   parameter CLK_PERIOD = 8.13; // Clock period in ns
+
+    // Inputs
+    logic Clk_i;
+    logic Clk100;
+    logic Clk20;
+    logic Clk80;
+    logic Clk50;
+    logic Clk24;
+    logic Clk10; 
+    logic Rst_i;
+    logic Start_i;
+    logic CPHA_i;
+    logic [31:0] SPIdata;
+	logic SpiDataVal_i;
+    logic SELST_i;
+    logic [1:0] WidthSel_i;
+    logic LAG_i;
+    logic LEAD_i;
+    logic EndianSel_i;
+    logic [5:0] Stop_i;
+    logic PulsePol_i;
+
+    // Outputs
+    wire Mosi0_o;
+    wire Mosi1_o;
+    wire Mosi1_io;
+    wire Mosi2_o;
+    wire Mosi3_o;
+    wire Sck_o;
+    wire Ss_o;
+    wire Val_o;
+
+    wire valR;
+    wire valQ;
+    wire SckR;
+    wire SckQ;
+    wire SsR;
+    wire SsQ;
+    wire mosi0R;
+    wire mosi0Q;
+
+    wire locked;
+    wire rstInit;
+
+    logic [16:0] trCnt;
+    logic [4:0] trCntSync;
+
+
+    logic modeSel; 
+    logic [23:0] randData;
+    logic [31:0] randData32;
+    logic [5:0] QSPITotalWordNum;
+    logic Stop;
+    logic [31:0] stopCnt;
+    logic rstForFPGA;
+
+//***********************************************
+//	            Lines From RF Top
+//***********************************************
+
+    logic [7:0] sckFromRFTop;
+    logic [7:0] mosiFromRFTop;
+    logic [7:0] ssFromRFTop;
+
+
+    logic [23:0] dataFromSPItb;
+    logic        valFromSPItb; 
+
+//***********************************************
+//	            CLASSES
+//***********************************************
+
+class Packet;
+    rand bit [23:0] data;
+    rand bit [31:0] data32;
+endclass
+
+Packet pkt;
+
+//***********************************************
+//	      HEADERS FOR DEVICES
+//***********************************************
+localparam [4:0]  DeviceIdLmx2594 = 5'h0;
+localparam [4:0]  DeviceIdDDS = 5'h1;
+localparam [4:0]  DeviceIdPot = 5'h2;
+localparam [4:0]  DeviceIdDac = 5'h3;
+localparam [4:0]  DeviceIdAtt = 5'h4;
+localparam [4:0]  DeviceIdShReg = 5'h5;
+localparam [4:0]  DeviceIdMax2870 = 5'h6;
+localparam [4:0]  DeviceIdGPIO = 5'h7;
+
+localparam [16:0] Lmx2594InitWordNum = 17'd113;
+localparam [16:0] DDSInitWordNum = 17'd37;
+localparam [16:0] MaxInitWordNum = 17'd6;
+
+localparam [23:0] InitLMX2594Header = {1'h0, DeviceIdLmx2594, Lmx2594InitWordNum, 1'h1};
+localparam [23:0] InitDDSHeader = {1'h0, DeviceIdDDS, DDSInitWordNum, 1'h1};
+localparam [23:0] InitMAX2870Header = {1'h0, DeviceIdMax2870, MaxInitWordNum, 1'h1};
+localparam [3:0]  LMXWordNum = 4'd14;
+localparam [1:0]  DDSWordNum = 2'd3;
+localparam        POTWordNum = 1'd1;
+localparam        DACWordNum = 1'd1;
+localparam        ATTWordNum = 1'd1;
+localparam [1:0]  ShRegWordNum = 1'd1;
+localparam [2:0]  MaxWordNum =   3'd2;
+localparam [1:0]  GPIOWordNum =  2'd1;
+
+localparam [23:0] AllDevQSPIHeader = {1'h1, LMXWordNum, DDSWordNum, POTWordNum, DACWordNum,ATTWordNum, ShRegWordNum,MaxWordNum, GPIOWordNum, 7'h1};
+
+//***********************************************
+//	           ASSIGNS
+//***********************************************
+assign Val_o = (modeSel) ? valQ : valR;
+assign Sck_o = (modeSel) ? SckQ : SckR;
+assign Ss_o = (modeSel) ? SsQ : SsR;
+assign Mosi0_o = (modeSel) ? mosi0Q : mosi0R;
+
+assign emptyFlagTx = (trCnt > 183) ? 1'b1 : 1'b0;
+assign QSPITotalWordNum = LMXWordNum + DDSWordNum + POTWordNum + DACWordNum + ATTWordNum + ShRegWordNum + MaxWordNum + GPIOWordNum; 
+
+//***********************************************
+//	           CLOCK GENERATION
+//***********************************************
+always #(CLK_PERIOD/2) Clk_i = ~Clk_i;
+always #(10/2) Clk100 = ~Clk100;
+always #(20/2) Clk50 = ~Clk50;
+always #(12.5/2) Clk80 = ~Clk80;
+always #(41.67/2) Clk24 = ~Clk24;
+always #(50/2) Clk20 = ~Clk20;
+always #(50)   Clk10 = ~Clk10; 
+
+//***********************************************
+//	           INITIALIZATION
+//***********************************************
+
+initial begin
+      // Initialize Inputs
+      Clk_i = 1;
+      Clk100= 1;
+      Clk20 = 1;
+      Clk50 = 1;
+      Clk80 = 1;
+      Clk24 = 1;
+      rstForFPGA = 0;
+      Clk10 = 1;
+      pkt = new();
+      Rst_i = 1;
+      Start_i = 0;
+      CPHA_i = 0;		SpiDataVal_i = 0;
+      SELST_i = 1;//0:High, 1:Low
+    //   WidthSel_i = 2; // 3-32bit, 2-24bit, 1-16bit, 0-8bit
+      LAG_i = 0;
+      LEAD_i = 0;
+      EndianSel_i = 0; // 0:MSB first, 1:lsb first
+      PulsePol_i = 0;
+      // Reset the system
+      #(CLK_PERIOD*10) Rst_i = 0;
+      #(300000-60) rstForFPGA = 1;
+      #(CLK_PERIOD*74) rstForFPGA = 0;
+      #(20) Start_i = 1; // Start SPI transaction
+    
+  end
+//***********************************************
+
+always_ff @(posedge Clk10) begin
+    if (Rst_i) begin 
+        trCnt <= 0;
+    end
+    else begin 
+        if (Val_o) begin 
+            trCnt <= trCnt + 1;
+        end
+    end
+end
+
+genvar i;
+always_comb begin 
+    if (Rst_i) begin 
+        WidthSel_i = 2'd0;
+    end
+    else begin 
+        if (trCnt > 152 && trCnt < 159) begin 
+            WidthSel_i = 2'd3;
+        end
+        else begin 
+            WidthSel_i = 2'd2;
+        end
+    end
+end
+
+always_comb begin 
+    if (Rst_i) begin 
+        modeSel = 0;
+    end
+    else begin 
+        if (trCnt == 159) begin 
+            modeSel = 1;
+        end
+    end
+end
+
+always_comb begin 
+    if (Rst_i) begin 
+        Stop_i = 6'd0;
+    end
+    else begin 
+        if (trCnt == 158) begin 
+            Stop_i = 6'h0;
+        end
+        else begin
+            Stop_i = 6'd0;
+        end
+    end
+end
+
+always_ff @(posedge Clk10) begin 
+    if (Rst_i) begin 
+        randData<=0;
+        randData32 <= 0;
+    end
+    else begin 
+        randData <= pkt.randomize(data);
+        randData32 <= pkt.randomize(data32);
+    end
+end
+
+always_comb begin 
+    if (Rst_i) begin 
+        SPIdata = 0;
+    end
+    else begin 
+        // if (!rstInit && locked) begin
+            if (trCnt == 0) begin 
+                SPIdata = InitLMX2594Header;
+            end
+            // else if (trCnt > 0 && trCnt < 114) begin 
+            //     SPIdata = pkt.data;
+            // end
+            else if (trCnt == 114) begin 
+                SPIdata = InitDDSHeader;
+            end
+            else if (trCnt == 152) begin 
+                SPIdata = InitMAX2870Header;
+            end
+            else if (trCnt > 152 && trCnt < 159) begin 
+                // if (trCnt % 2 == 0) begin 
+                //     SPIdata = 32'haaaaaaaa;
+                // end
+                // else begin 
+                //     SPIdata = 32'h55555555;
+                // end
+                SPIdata = 32'haaaaaaaa;
+                // SPIdata = pkt.data32;
+            end
+            else if (trCnt == 159) begin 
+                SPIdata = AllDevQSPIHeader;
+            end
+            else begin
+                // if (trCnt % 2 == 0) begin 
+                //     SPIdata = 24'haaaaaa;
+                // end
+                // else begin 
+                //     SPIdata = 24'h555555;
+                // end
+                SPIdata = 24'haaaaaa;
+                // SPIdata = pkt.data;
+            end
+        end
+    end
+// end
+
+//***********************************************
+//	           DUT INSTANTIATION
+//***********************************************
+    GSR GSR(.GSRI(1'b1));
+
+   ExtSpiMEmul ExtSpiMEmul_inst (
+        .Clk_i(Clk10), 
+        .Rst_i(Rst_i || modeSel), 
+        .Start_i(Start_i), 
+        .ClockPhase_i(CPHA_i),
+        .EmptyFlag_i(emptyFlagTx), 
+        .SpiData_i(SPIdata),
+        .SelSt_i(SELST_i),
+        .WidthSel_i(WidthSel_i),
+        .Lag_i(LAG_i),
+        .Lead_i(LEAD_i),
+        .EndianSel_i(EndianSel_i),
+        .Stop_i(Stop_i),
+        .PulsePol_i(PulsePol_i),
+        .Mosi0_o(mosi0R),
+        .Sck_o(SckR),
+        .Ss_o(SsR),
+        .Val_o(valR)
+    );
+
+    ExtQspiMEmul ExtQspiMEmul_inst (
+        .Clk_i(Clk10),
+        .Rst_i(Rst_i || !modeSel),
+        .Start_i(Start_i),
+        .ClockPhase_i(CPHA_i),
+        .EmptyFlag_i(emptyFlagTx),
+        .SpiData_i(SPIdata),
+        .SelSt_i(SELST_i),
+        .WidthSel_i(WidthSel_i),
+        .Lag_i(LAG_i),
+        .Lead_i(LEAD_i),
+        .EndianSel_i(EndianSel_i),
+        .Stop_i(Stop_i),
+        .PulsePol_i(PulsePol_i),
+        .Mosi0_o(mosi0Q),
+        .Mosi1_o(Mosi1_o),
+        .Mosi2_o(Mosi2_o),
+        .Mosi3_o(Mosi3_o),
+        .Sck_o(SckQ),
+        .Ss_o(SsQ),
+        .Val_o(valQ)
+    );
+
+    TopSbTmsg TopSbTmsg_inst (
+        .Clk_i(Clk24),
+        .Rst_i(rstForFPGA),
+        .Sck_i(Sck_o),
+        .Ss_i(Ss_o),
+        .Mosi0_i(Mosi0_o),
+        .Mosi1_io(Mosi1_o),
+        .Mosi2_i(Mosi2_o),
+        .Mosi3_i(Mosi3_o)
+    );
+
+    endmodule

src/src/Top/TopSbTmsgTb.v

@@ -1,275 +0,0 @@
-`timescale 1ns / 1ps
-
-//////////////////////////////////////////////////////////////////////////////////
-// Company: Tair
-// Engineer: Churbanov S.
-// 
-// Create Date:     
-// Design Name: 
-// Module Name:    InterfaceArbiter
-// Project Name: 
-// Target Devices: 
-// Tool versions: 
-// Description: 
-//
-// Dependencies: 
-//
-// Revision: 
-// Revision 0.01 - File Created
-// Additional Comments: 
-//
-//////////////////////////////////////////////////////////////////////////////////
-
-module TopSbTmsgTb();
-
-//================================================================================
-//  REG/WIRE
-	
-	parameter OUTWORDWIDTH = 24;
-	parameter SSPIWORDWIDTH = 24;
-	parameter QSPIWORDWIDTH = 6;
-	
-	localparam [1:0] IDLE = 0;
-	localparam [1:0] SINGLE = 1;
-	localparam [1:0] DELAY = 2;
-	localparam [1:0] QUAD = 3;
-	
-	reg spiMode = 1'b0; //0 - single 1- quad
-	
-	reg [31:0] tbCnt;
-	reg [31:0] delCnt;
-	reg stateCnt;
-	
-	reg Clk100;
-	reg Clk10;
-	
-	reg [1:0] currState;
-	reg [1:0] nextState;
-	
-	reg rst;
-	
-	wire txStart = (tbCnt == 100 | tbCnt == 3000);
-	wire txDoneS;
-	wire txDoneQ;
-	
-	
-	wire sckS;
-	wire sckQ;
-	wire ssS;
-	wire ssQ;
-	
-	wire ss;
-	wire sck;
-	
-	wire mosi0S;
-	wire mosi0Q;
-	wire mosi1Q;
-	wire mosi2Q;
-	wire mosi3Q;
-	
-	wire delDone = (delCnt == 500);
-//================================================================================
-//  ASSIGNMENTS
-	
-	assign sck = (currState==SINGLE) ? sckS:sckQ;
-	assign ss = (currState==SINGLE) ? ssS:ssQ;
-	assign mosi0 = (currState==SINGLE) ? mosi0S:mosi0Q;
-	assign mosi1 = (currState==SINGLE) ? 1'b1:mosi1Q;
-	assign mosi2 = (currState==SINGLE) ? 1'b1:mosi2Q;
-	assign mosi3 = (currState==SINGLE) ? 1'b1:mosi3Q;
-//================================================================================
-//clocks gen
-	always	#5 Clk100	=	~Clk100;	
-	always	#50 Clk10	=	~Clk10;	
-	
-	
-//================================================================================
-//  CODING
-
-initial begin
-	Clk100	=	1'b1;
-	Clk10	=	1'b1;
-	rst		=	1'b1;
-#100;
-	rst		=	1'b0;
-end	
-	
-always	@(negedge	Clk100)	begin
-	if	(!rst)		begin
-		tbCnt	<=	tbCnt+1;
-	end	else	begin
-		tbCnt	<=	0;
-	end
-end
-
-always	@(posedge	Clk100)	begin
-	if	(!rst)		begin
-		if (currState == DELAY) begin
-			delCnt	<=	delCnt+1;
-		end	else	begin
-			delCnt	<=	0;
-		end
-	end else	begin
-		delCnt	<=	0;
-	end
-end
-
-always	@(negedge	Clk10)	begin
-	if	(!rst)		begin
-		if (txDoneS|txDoneQ) begin
-			stateCnt	<=	stateCnt+1;
-		end	
-	end else begin
-		stateCnt <= 0;
-	end
-end
-
-always	@(posedge	Clk100)	begin
-	if	(!rst)		begin
-		case (stateCnt)
-			0:	begin
-					spiMode <= 1'b0;
-				end
-			1:	begin
-					spiMode <= 1'b1;
-				end
-			default:begin
-						spiMode <= 1'b0;
-					end
-		endcase
-	end else begin
-		spiMode <= 1'b0;
-	end
-end
-
-always	@(posedge	Clk100)	begin
-	if	(rst)	begin
-		currState	<=	IDLE;
-	end	else	begin
-		currState	<=	nextState;
-	end
-end
-
-
-always @(*) begin
-	nextState	=	IDLE;
-	case(currState)
-	IDLE	:	begin
-					if (txStart)	begin
-						case (spiMode)
-							1'b0:	begin
-											nextState = SINGLE;
-										end
-							1'b1:		begin
-											nextState = QUAD;
-										end
-						endcase
-					end	else begin
-						nextState = IDLE;
-					end
-				end
-				
-	SINGLE	:	begin
-					if (txDoneS)	begin
-						nextState = DELAY;
-					end	else begin
-						nextState = SINGLE;
-					end
-				end
-				
-	DELAY	:	begin
-					if (delDone)	begin
-						nextState = QUAD;
-					end	else begin
-						nextState = DELAY;
-					end
-				end
-				
-	QUAD		:	begin
-					if (txDoneQ) begin
-						nextState  = IDLE;
-					end	else begin
-						nextState  = QUAD;
-					end
-				end
-	endcase
-end
-
-ExtSpiMEmul SingleSpiSm
-(
-	.Rst_i		(rst),
-	.Clk_i		(Clk10),
-	
-	.Start_i	((currState==SINGLE)),
-	.TxDone_o	(txDoneS),
-	
-	.Sck_o		(sckS),
-	.Ss_o		(ssS),
-	.Mosi_o		(mosi0S)
-	
-);
-
-ExtQSpiMEmul QuadSpiSm
-(
-	.Rst_i		(rst),
-	.Clk_i		(Clk10),
-	
-	.Start_i	((currState==QUAD)),
-	.TxDone_o	(txDoneQ),
-	
-	.Sck_o		(sckQ),
-	.Ss_o		(ssQ),
-	.Mosi0_o	(mosi0Q),
-	.Mosi1_o	(mosi1Q),
-	.Mosi2_o	(mosi2Q),
-	.Mosi3_o	(mosi3Q)
-	
-);
-
-TopSbTmsg DUT
-(
-	.Clk_i	(Clk100),
-	.Rst_i	(rst),
-	
-	.Sck_i	(sck),
-	.Ss_i	(ss),
-	
-	.Mosi0_i	(mosi0),
-	.Mosi1_io	(mosi1),
-	.Mosi2_i	(mosi2),
-	.Mosi3_i	(mosi3),
-	
-	.Miso1_i		(),
-	.Miso2_i		(),
-	.MisoMax2870_i	(),
-	
-	.I2CSck_o	(),
-	.I2CSda_io	(),
-	
-	.Ss_o		(),
-	.Sck_o		(),
-	.Mosi_o		(),
-	
-	.Gpio_o		()
-);
-
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-