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+////////////////////////////////////////////////////////////////////////////////////////////
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+// Company: TAIR
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+// Engineer: Zaytsev Mikhail
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+//
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+// Create Date: 18/04/2024
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+// Design Name:
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+// Module Name: PacketAnalyzer4Mosi
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+// Project Name: SB_TMSG44V1_FPGA
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+// Target Devices: Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
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+// Tool versions:
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+// Description: The module analyzes the input data bus DataFromSpi_i[23:0] by the
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+// validity signal ValDataFromSpi_i. When a configuration packet is
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+// received, it is captured into the internal register. Further, each
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+// incoming data packet decrements the internal configuration register
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+// until the internal configuration register is zero, which means that
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+// the module is ready to receive the next configuration packet. Each
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+// decrement sets the data validity bit for the specific end device.
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+// The module also has an output signal Busy_o, which signals that
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+// the module is in the state of processing the data received in
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+// 4MOSI mode for writing to the FIFO.
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+//
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+// Dependencies:
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+// Revision:
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+// Revision 1.0 - File Created
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+// Additional Comments:
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+//
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+////////////////////////////////////////////////////////////////////////////////////////////
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+module PacketAnalyzer4Mosi (
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+ input Clk_i,
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+ input Rst_i,
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+
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+ input [23:0] DataFromSpi_i,
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+ input ValDataFromSpi_i,
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+
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+ input BusyMosi1_i,
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+
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+ output reg ValLmxDataToFifo_o,
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+ output reg ValDdsDataToFifo_o,
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+ output reg ValPotDataToFifo_o,
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+ output reg ValDacDataToFifo_o,
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+ output reg ValAttDataToFifo_o,
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+ output reg ValShRegDataToFifo_o,
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+ output reg ValMaxDataToFifo_o,
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+ output reg ValGpioDataToFifo_o,
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+
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+ output reg Busy_o
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+);
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+
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+//==========================================
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+// Registers
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+//==========================================
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+reg [22:0] DataSpiReg;
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+
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+//==========================================
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+// Wires
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+//==========================================
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+wire lmxOr;
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+wire ddsOr;
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+wire potOr;
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+wire dacOr;
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+wire attOr;
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+wire shRegOr;
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+wire maxOr;
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+wire gpioOr;
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+
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+wire [7:0] selector;
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+
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+//==========================================
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+// Parameters
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+//==========================================
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+localparam [22:0] DECREMENT_LMX = 23'h80000; //23'b000 1000 0000 0000 0000 0000
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+localparam [22:0] DECREMENT_DDS = 23'h20000; //23'b000 0010 0000 0000 0000 0000
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+localparam [22:0] DECREMENT_POT = 23'h10000; //23'b000 0001 0000 0000 0000 0000
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+localparam [22:0] DECREMENT_DAC = 23'h8000; //23'b000 0000 1000 0000 0000 0000
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+localparam [22:0] DECREMENT_ATT = 23'h4000; //23'b000 0000 0100 0000 0000 0000
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+localparam [22:0] DECREMENT_SH_REG = 23'h1000; //23'b000 0000 0001 0000 0000 0000
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+localparam [22:0] DECREMENT_MAX = 23'h200; //23'b000 0000 0000 0010 0000 0000
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+localparam [22:0] DECREMENT_GPIO = 23'h80; //23'b000 0000 0000 0000 1000 0000
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+
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+//==========================================
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+// Assignments
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+//==========================================
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+assign lmxOr = |DataSpiReg[22:19];
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+assign ddsOr = |DataSpiReg[18:17];
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+assign potOr = DataSpiReg[16];
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+assign dacOr = DataSpiReg[15];
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+assign attOr = DataSpiReg[14];
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+assign shRegOr = |DataSpiReg[13:12];
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+assign maxOr = |DataSpiReg[11:9];
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+assign gpioOr = |DataSpiReg[8:7];
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+
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+assign selector = {lmxOr, ddsOr, potOr, dacOr, attOr, shRegOr, maxOr, gpioOr};
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+
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+//==========================================================================//
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+// CODING //
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+//==========================================================================//
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+always @(posedge Clk_i) begin
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+ if (Rst_i) begin
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+ Busy_o <= 1'b0;
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+ end
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+ else if (DataSpiReg != 0) begin
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+ Busy_o <= 1'b1;
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+ end
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+ else begin
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+ Busy_o <= 1'b0;
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+ end
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+end
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+
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+always @(posedge Clk_i) begin
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+ if (Rst_i || BusyMosi1_i) begin
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+ DataSpiReg <= 23'b0;
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+ ValLmxDataToFifo_o <= 1'b0;
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+ ValDdsDataToFifo_o <= 1'b0;
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+ ValPotDataToFifo_o <= 1'b0;
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+ ValDacDataToFifo_o <= 1'b0;
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+ ValAttDataToFifo_o <= 1'b0;
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+ ValShRegDataToFifo_o <= 1'b0;
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+ ValMaxDataToFifo_o <= 1'b0;
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+ ValGpioDataToFifo_o <= 1'b0;
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+ end
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+ else if (ValDataFromSpi_i) begin
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+ if ((DataSpiReg == 0) && (DataFromSpi_i[23] == 1'b1)) begin
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+ DataSpiReg <= DataFromSpi_i[22:0];
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+ end
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+ else begin
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+ casez(selector)
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+ 8'b1???????: begin //LMX
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+ DataSpiReg <= DataSpiReg - DECREMENT_LMX;
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+ ValLmxDataToFifo_o <= 1'b1;
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+ end
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+ 8'b01??????: begin //DDS
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+ DataSpiReg <= DataSpiReg - DECREMENT_DDS;
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+ ValDdsDataToFifo_o <= 1'b1;
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+ end
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+ 8'b001?????: begin //POT
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+ DataSpiReg <= DataSpiReg - DECREMENT_POT;
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+ ValPotDataToFifo_o <= 1'b1;
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+ end
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+ 8'b0001????: begin //DAC
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+ DataSpiReg <= DataSpiReg - DECREMENT_DAC;
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+ ValDacDataToFifo_o <= 1'b1;
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+ end
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+ 8'b00001???: begin //ATT
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+ DataSpiReg <= DataSpiReg - DECREMENT_ATT;
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+ ValAttDataToFifo_o <= 1'b1;
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+ end
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+ 8'b000001??: begin //ShReg
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+ DataSpiReg <= DataSpiReg - DECREMENT_SH_REG;
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+ ValShRegDataToFifo_o <= 1'b1;
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+ end
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+ 8'b0000001?: begin //MAX2870
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+ DataSpiReg <= DataSpiReg - DECREMENT_MAX;
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+ ValMaxDataToFifo_o <= 1'b1;
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+ end
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+ 8'b00000001: begin //GPIO
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+ DataSpiReg <= DataSpiReg - DECREMENT_GPIO;
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+ ValGpioDataToFifo_o <= 1'b1;
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+ end
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+ default: begin
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+ ValLmxDataToFifo_o <= 1'b0;
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+ ValDdsDataToFifo_o <= 1'b0;
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+ ValPotDataToFifo_o <= 1'b0;
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+ ValDacDataToFifo_o <= 1'b0;
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+ ValAttDataToFifo_o <= 1'b0;
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+ ValShRegDataToFifo_o <= 1'b0;
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+ ValMaxDataToFifo_o <= 1'b0;
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+ ValGpioDataToFifo_o <= 1'b0;
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+ end
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+ endcase
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+//=========================DELETE AFTER HARDWARE TEST===========================
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+ /*if (lmxOr) begin //LMX
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+ DataSpiReg <= DataSpiReg - DECREMENT_LMX;
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+ ValLmxDataToFifo_o <= 1'b1;
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+ end
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+ else if (ddsOr) begin //DDS
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+ DataSpiReg <= DataSpiReg - DECREMENT_DDS;
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+ ValDdsDataToFifo_o <= 1'b1;
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+ end
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+ else if (potOr) begin //POT
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+ DataSpiReg <= DataSpiReg - DECREMENT_POT;
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+ ValPotDataToFifo_o <= 1'b1;
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+ end
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+ else if (dacOr) begin //DAC
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+ DataSpiReg <= DataSpiReg - DECREMENT_DAC;
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+ ValDacDataToFifo_o <= 1'b1;
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+ end
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+ else if (attOr) begin
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+ DataSpiReg <= DataSpiReg - DECREMENT_ATT;
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+ ValAttDataToFifo_o <= 1'b1;
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+ end
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+ else if (shRegOr) begin
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+ DataSpiReg <= DataSpiReg - DECREMENT_SH_REG;
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+ ValShRegDataToFifo_o <= 1'b1;
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+ end
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+ else if (maxOr) begin
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+ DataSpiReg <= DataSpiReg - DECREMENT_MAX;
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+ ValMaxDataToFifo_o <= 1'b1;
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+ end
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+ else if (gpioOr) begin
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+ DataSpiReg <= DataSpiReg - DECREMENT_GPIO;
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+ ValGpioDataToFifo_o <= 1'b1;
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+ end
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+ else begin
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+ ValLmxDataToFifo_o <= 1'b0;
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+ ValDdsDataToFifo_o <= 1'b0;
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+ ValPotDataToFifo_o <= 1'b0;
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+ ValDacDataToFifo_o <= 1'b0;
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+ ValAttDataToFifo_o <= 1'b0;
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+ ValShRegDataToFifo_o <= 1'b0;
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+ ValMaxDataToFifo_o <= 1'b0;
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+ ValGpioDataToFifo_o <= 1'b0;
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+ end*/
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+//=========================DELETE AFTER HARDWARE TEST===========================
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+ end
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+ end
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+ else begin
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+ ValLmxDataToFifo_o <= 1'b0;
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+ ValDdsDataToFifo_o <= 1'b0;
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+ ValPotDataToFifo_o <= 1'b0;
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+ ValDacDataToFifo_o <= 1'b0;
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+ ValAttDataToFifo_o <= 1'b0;
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+ ValShRegDataToFifo_o <= 1'b0;
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+ ValMaxDataToFifo_o <= 1'b0;
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+ ValGpioDataToFifo_o <= 1'b0;
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+ end
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+end
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+
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+endmodule
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Anatoliy Chigirinskiy