GpioCtrl переименован в Gpio1Ctrl. Добавлена возможность записи регистра Gpio1 в режиме 1Mosi.

src/src/GpioCtrl/GpioCtrl.v

@@ -4,7 +4,7 @@
 // 
 // Create Date:		24/04/2024 
 // Design Name: 
-// Module Name:		GpioCtrl 
+// Module Name:		Gpio1Ctrl 
 // Project Name:	SB_TMSG44V1_FPGA
 // Target Devices:	Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
 // Tool versions:
@@ -16,12 +16,15 @@
 // Additional Comments: 
 //
 ////////////////////////////////////////////////////////////////////////////////////////////
-module GpioCtrl (
+module Gpio1Ctrl (
 	input Clk_i,
 	input Rst_i,
 	
 	input ValGpioDataToFifo_i,
 	input [23:0] Data_i,
+	input ValDataFromSpi_i,
+
+	input FlagDirectGpio1_i,
 
 	output reg [21:0] GpioReg_o
 );
@@ -30,7 +33,7 @@ always @(posedge Clk_i) begin
 	if(Rst_i) begin
 		GpioReg_o <= 0;
 	end 
-	else if (ValGpioDataToFifo_i) begin
+	else if (ValGpioDataToFifo_i || (FlagDirectGpio1_i && ValDataFromSpi_i)) begin
 		GpioReg_o <= Data_i[21:0];
 	end
 end

src/src/Gpio1Ctrl/Gpio1CtrlTb.v

@@ -0,0 +1,169 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		Zaytsev Mikhail
+// 
+// Create Date:		26/04/2024 
+// Design Name: 
+// Module Name:		Gpio1CtrlTb 
+// Project Name:	SB_TMSG44V1_FPGA
+// Target Devices:	Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:		The module simulates three 4Mosi GPIO register writes 
+//					and three 1Mosi GPIO register writes.
+//
+// Dependencies:	
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+`timescale 1ns / 1ns
+
+module Gpio1CtrlTb();
+
+reg Clk;
+reg Rst;
+reg [4:0] cnt;
+reg [4:0] state;
+
+reg [23:0] DataGpio;
+reg ValData;
+
+reg FlagDirectGpio1;
+reg ValDataFromSpi;
+
+always #5 Clk = ~Clk;
+
+initial begin
+	Clk	=	1'b1;
+	Rst = 	1'b1;
+	#100
+	Rst = 	1'b0;
+end
+
+always @(posedge Clk) begin
+	if(Rst) begin
+		DataGpio <= 0;
+		cnt <= 0;
+		state <= 0;
+		ValData <= 0;
+		FlagDirectGpio1 <= 0;
+		ValDataFromSpi <= 0;
+	end 
+	else begin
+		case (state)
+			0: begin
+				DataGpio <= 23'h3FFFFF;
+
+				if (cnt == 6) begin
+					cnt <= 0;
+					ValData <= 1;
+					state <= state + 1;
+				end
+				else begin
+					ValData = 0;
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			1: begin
+				DataGpio <= 23'h311111;
+
+				if (cnt == 6) begin
+					cnt <= 0;
+					ValData <= 1;
+					state <= state + 1;
+				end
+				else begin
+					ValData = 0;
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			2: begin
+				DataGpio <= 23'h3AAAAA;
+
+				if (cnt == 6) begin
+					cnt <= 0;
+					ValData <= 1;
+					state <= state + 1;
+				end
+				else begin
+					ValData = 0;
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			3: begin
+				ValData = 0;
+				state = state + 1;
+			end
+			4: begin
+				DataGpio <= 23'h3FFFFA;
+
+				if (cnt == 6) begin
+					cnt <= 0;
+					ValDataFromSpi <= 1;
+					state <= state + 1;
+				end
+				else begin
+					FlagDirectGpio1 <= 1;
+					ValDataFromSpi = 0;
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			5: begin
+				DataGpio <= 23'h31111A;
+
+				if (cnt == 6) begin
+					cnt <= 0;
+					ValDataFromSpi <= 1;
+					state <= state + 1;
+				end
+				else begin
+					ValDataFromSpi = 0;
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			6: begin
+				DataGpio <= 23'h3AAAAF;
+
+				if (cnt == 6) begin
+					cnt <= 0;
+					ValDataFromSpi <= 1;
+					state <= state + 1;
+				end
+				else begin
+					ValDataFromSpi = 0;
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			7: begin
+				ValDataFromSpi = 0;
+				state = state + 1;
+			end
+
+			8: begin
+				FlagDirectGpio1 <= 0;
+			end
+		endcase
+	end
+end
+
+Gpio1Ctrl DUT(
+	.Clk_i					(Clk),
+	.Rst_i					(Rst),
+
+	.ValGpioDataToFifo_i	(ValData),
+	.Data_i					(DataGpio),
+	.ValDataFromSpi_i		(ValDataFromSpi),
+
+	.FlagDirectGpio1_i		(FlagDirectGpio1),
+
+	.GpioReg_o				()
+);
+
+endmodule

src/src/Gpio1Ctrl/Gpio1CtrlWave.do

@@ -0,0 +1,27 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /Gpio1CtrlTb/DUT/Clk_i
+add wave -noupdate /Gpio1CtrlTb/DUT/Rst_i
+add wave -noupdate /Gpio1CtrlTb/DUT/ValGpioDataToFifo_i
+add wave -noupdate /Gpio1CtrlTb/DUT/Data_i
+add wave -noupdate /Gpio1CtrlTb/DUT/ValDataFromSpi_i
+add wave -noupdate /Gpio1CtrlTb/DUT/FlagDirectGpio1_i
+add wave -noupdate /Gpio1CtrlTb/DUT/GpioReg_o
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {18 ns} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ns} {1008 ns}

src/src/GpioCtrl/GpioCtrlTb.v

@@ -1,90 +0,0 @@
-`timescale 1ns / 1ns
-
-module GpioCtrlTb();
-
-reg Clk;
-reg Rst;
-reg [4:0] cnt;
-reg [4:0] state;
-
-reg [23:0] DataGpio;
-reg ValData;
-
-always #5 Clk = ~Clk;
-
-initial begin
-	Clk	=	1'b1;
-	Rst = 	1'b1;
-	#100
-	Rst = 	1'b0;
-end
-
-always @(posedge Clk) begin
-	if(Rst) begin
-		DataGpio <= 0;
-		cnt <= 0;
-		state <= 0;
-		ValData <= 0;
-	end 
-	else begin
-		case (state)
-			0: begin
-				DataGpio <= 23'h3FFFFF;
-
-				if (cnt == 6) begin
-					cnt <= 0;
-					ValData <= 1;
-					state <= state + 1;
-				end
-				else begin
-					ValData = 0;
-					cnt <= cnt + 1;
-					state <= state;
-				end
-			end
-			1: begin
-				DataGpio <= 23'h311111;
-
-				if (cnt == 6) begin
-					cnt <= 0;
-					ValData <= 1;
-					state <= state + 1;
-				end
-				else begin
-					ValData = 0;
-					cnt <= cnt + 1;
-					state <= state;
-				end
-			end
-			2: begin
-				DataGpio <= 23'h3AAAAA;
-
-				if (cnt == 6) begin
-					cnt <= 0;
-					ValData <= 1;
-					state <= state + 1;
-				end
-				else begin
-					ValData = 0;
-					cnt <= cnt + 1;
-					state <= state;
-				end
-			end
-			3: begin
-				ValData = 0;
-			end
-		endcase
-	end
-end
-
-GpioCtrl DUT(
-	.Clk_i					(Clk),
-	.Rst_i					(Rst),
-
-	.ValGpioDataToFifo_i	(ValData),
-	.Data_i					(DataGpio),
-
-	.GpioReg_o				()
-);
-
-endmodule