Изменены названия модулей, параметров. Из модуля SpiM убран флаг startFlag. В тестбенче реализована логика сравнения отправленных и принятых данных.

src/src/SPIm/.~lock.SPIm.docx#

@@ -0,0 +1 @@
+,DESKTOP-1TRD5RL/AnatoliyChigirinskiy,DESKTOP-1TRD5RL,19.04.2024 15:22,file:///C:/Users/AnatoliyChigirinskiy/AppData/Roaming/LibreOffice/4;

src/src/SPIm/SPIs_tb.v

@@ -1,4 +1,4 @@
-module SPIs_tb (
+module ExtSpiSlaveEmul (
     input Clk_i,
     input Rst_i,
 
@@ -6,9 +6,7 @@ module SPIs_tb (
     input Ss_i,
     input Mosi0_i,
 
-    output reg [17:0] Data_o,
-    output reg [5:0] Addr_o,
-    output [23:0] DataToRxFifo_o,
+    output reg [23:0] Data_o,
     output reg Val_o
 );
 
@@ -22,13 +20,9 @@ module SPIs_tb (
 //===============================================================================
 //  ASSIGNMENTS
 
-
-    assign DataToRxFifo_o = {Addr_o, Data_o};
-
 //================================================================================
 //	CODING
 //================================================================================
-
     always	@(posedge	Clk_i)	begin
     	ssReg	<=	Ss_i;
     	ssRegR	<=	ssReg;
@@ -36,22 +30,11 @@ module SPIs_tb (
 
     always @(posedge Clk_i) begin 
         if (Rst_i) begin 
-            Data_o <= 18'h0;
-        end
-        else begin
-            if (ssReg && !ssRegR) begin 
-                Data_o <= shiftReg[17:0];
-            end
-        end
-    end
-
-    always @(posedge Clk_i) begin 
-        if (Rst_i) begin 
-            Addr_o <= 8'h0;
+            Data_o <= 24'h0;
         end
         else begin 
             if (ssReg && !ssRegR) begin 
-                Addr_o <= shiftReg[23:18];
+                Data_o <= shiftReg;
             end
         end
     end

src/src/SPIm/SPIm.v

@@ -1,14 +1,14 @@
 ////////////////////////////////////////////////////////////////////////////////////////////
-// Company:      TAIR
-// Engineer:    Chigrinskiy A. 
+// Company:         TAIR
+// Engineer:        Chigrinskiy A. 
 // 
-// Create Date:    18/04/2024 
+// Create Date:     18/04/2024 
 // Design Name: 
-// Module Name:    SPIm
-// Project Name:  SB_TMSG44V1_FPGA
+// Module Name:     SPIm
+// Project Name:    SB_TMSG44V1_FPGA
 // Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
 // Tool versions:
-// Description:  This module implements SPI master interface
+// Description:     This module implements SPI master interface
 //
 // Dependencies:  
 // Revision: 
@@ -16,14 +16,13 @@
 // Additional Comments: 
 //
 ////////////////////////////////////////////////////////////////////////////////////////////
-
-module SPIm #(
-    parameter ssNum = 24
+module SpiM #(
+    parameter DATA_WIDTH = 24
 )(
     input Clk_i,
     input Rst_i,
     input Val_i,
-    input [ssNum-1:0] SpiData_i,
+    input [DATA_WIDTH-1:0] SpiData_i,
 
     output Ss_o,
     output Mosi_o,
@@ -32,22 +31,36 @@ module SPIm #(
 );
 
 //================================================================================
-//	REG/WIRE
+//FUNCTIONS
 //================================================================================
-reg [6:0] ssCnt;
-reg [ssNum-1:0] mosiReg;
-reg             ssReg;
+function integer log2;
+input [31:0] value;
+	begin
+		log2 = 0;
+		while (value > 1) begin
+			value   = value >> 1;
+			log2    = log2 + 1;
+		end
+		if	((2**log2)<DATA_WIDTH)	begin
+			log2	=	log2+1;
+		end	
+	end
+endfunction
 
-reg startFlag;
-reg ssR;
+//================================================================================
+//	REG/WIRE
+//================================================================================
+reg [log2(DATA_WIDTH)-1:0] ssCnt;
+reg [DATA_WIDTH-1:0] mosiReg;
+reg	ssReg;
 
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
 assign Ss_o = ssReg;
-assign Mosi_o = (!Ss_o) ? mosiReg[ssNum-1] : 1'b0;
-assign Sck_o = (!Ss_o) ? Clk_i : 1'b0;
-assign Busy_o = !Ss_o;
+assign Mosi_o = (!ssReg) ? mosiReg[DATA_WIDTH-1] : 1'b0;
+assign Sck_o = (!ssReg) ? Clk_i : 1'b0;
+assign Busy_o = !ssReg;
 
 //================================================================================
 //	CODING
@@ -56,26 +69,29 @@ always @(negedge Clk_i) begin
     if (Rst_i) begin 
         ssCnt <= 7'h0;
     end
-    else begin 
-        if (ssCnt < ssNum && startFlag) begin
-            ssCnt <= ssCnt + 1;
+    else begin
+        if (ssCnt == 0) begin 
+            if (Val_i) begin 
+                ssCnt <= ssCnt + 1;
+            end
         end
         else begin 
-            ssCnt <= 7'h0;
+            if (ssCnt < DATA_WIDTH) begin 
+                ssCnt <= ssCnt + 1;
+            end
+            else begin 
+                ssCnt <= 7'h0;
+            end
         end
     end
 end
 
-always @(posedge Clk_i) begin 
-    ssR <= ssReg;
-end
-
 always @(negedge Clk_i) begin 
     if (Rst_i) begin 
         mosiReg <= 0;
     end
     else begin 
-        if (!Ss_o) begin 
+        if (!ssReg) begin 
             mosiReg <= mosiReg << 1;
         end
         else begin
@@ -86,26 +102,12 @@ always @(negedge Clk_i) begin
     end
 end
 
-always @(*) begin 
-    if (Rst_i) begin 
-        startFlag = 1'b0;
-    end
-    else begin 
-        if (Val_i) begin 
-            startFlag = 1'b1;
-        end
-        else if (ssReg && !ssR) begin 
-            startFlag = 1'b0;
-        end
-    end
-end
-
 always @(negedge Clk_i) begin 
     if (Rst_i) begin 
         ssReg <= 1'b1;
     end
     else begin 
-        if (ssCnt < ssNum && startFlag) begin 
+        if (ssCnt < DATA_WIDTH) begin 
             ssReg <= 1'b0;
         end
         else begin 

src/src/SPIm/SPIm_tb.sv

@@ -1,5 +1,5 @@
 `timescale 1ns / 1ps
-module SPIm_tb;
+module SpiM_tb;
 logic Clk_i;
 logic Rst_i;
 logic [23:0] spiData;
@@ -14,12 +14,16 @@ localparam N = 16;
 //***********************************************
 logic [23:0] randData;
 logic [23:0] spiQueue [N-1:0];
+logic [23:0] spisQueue [N-1:0];
 logic busyFromSpi;
 logic valToSpi;
 logic [4:0] numOfWords;
+logic [4:0] numOfWordsSPIs;
+logic valFromSPIs;
 logic sck;
 logic ss;
 logic mosi;
+logic [23:0] spiDataFromDUT;
 
 //***********************************************
 //	            CLASSES
@@ -31,6 +35,7 @@ endclass
 
 Packet pkt;
 
+
 //***********************************************
 //	           CLOCK GENERATION
 //***********************************************
@@ -49,8 +54,18 @@ initial begin
     foreach(spiQueue[i]) begin
         spiQueue[i] = $urandom();
     end
+    wait(numOfWordsSPIs == 5'h10);
+    if (spiQueue == spisQueue) begin
+        $display("Test Passed");
+    end
+    else begin
+        $display("Test Failed");
+    end
 end
 
+//***********************************************
+//	           CODING
+//***********************************************
 always_ff @(posedge Clk_i) begin 
     if (Rst_i) begin 
         randData<=0;
@@ -96,10 +111,37 @@ always_ff @(*) begin
     end
 end
 
+always_ff @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        numOfWordsSPIs<=5'h0;
+    end
+    else begin
+        if (valFromSPIs) begin 
+            numOfWordsSPIs <= numOfWordsSPIs + 1;
+        end
+    end
+end
+
+
+
+always_ff @(posedge Clk_i) begin
+    if (Rst_i) begin 
+        foreach(spisQueue[i]) begin
+            spisQueue[i] <= 0;
+        end
+    end
+    else begin 
+        if (valFromSPIs) begin 
+            spisQueue[(N-1)-numOfWordsSPIs] <= spiDataFromDUT;
+        end
+    end
+end
+
+
 //***********************************************
 //	           DUT INSTANTIATION
 //***********************************************
-SPIm DUT (
+SpiM DUT (
     .Clk_i(Clk_i),
     .Rst_i(Rst_i),
     .SpiData_i(spiData),
@@ -110,14 +152,14 @@ SPIm DUT (
     .Busy_o(busyFromSpi)
 );
 
-SPIs_tb SPIs_inst (
+ExtSpiSlaveEmul ExtSpiSlaveEmul_inst (
     .Clk_i(Clk_i),
     .Rst_i(Rst_i),
     .Sck_i(sck),
     .Ss_i(ss),
     .Mosi0_i(mosi),
-    .DataToRxFifo_o(spiDataFromDUT),
-    .Val_o(valFromDUT)
+    .Data_o(spiDataFromDUT),
+    .Val_o(valFromSPIs)
 );
 
 endmodule