Merge branch 'Mikhail/feature_ClkGen' of zaytsev.mikhail/SB_TMSG44V1_FPGA into dev

src/src/ClkGen/ClkGen.v

@@ -0,0 +1,111 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		Zaytsev Mikhail
+// 
+// Create Date:		23/04/2024 
+// Design Name: 
+// Module Name:		ClkGen 
+// Project Name:	SB_TMSG44V1_FPGA
+// Target Devices:	Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:		
+//
+//		|-----------------------------------------------------------------------→CLK_24_MHz
+//		|
+//		|					|---------------------------------------------------→CLK_SYS_100_MHz
+//		|					|
+//		|					|------------→CLKDIV(/5)---(20MHz)---→CLKDIV(/4)----→CLK_5_MHz
+//		|					|							|
+//		|					|							|-----------------------→CLK_20_MHz
+//		|					|
+//	CLK_24_MHz_i---→rPLL(100MHz)------------------------------------------------→CLK_50_MHz
+//			|
+//			|------→rPLL(210MHz)------→CLKDIV(/8)-------------------------------→CLK_26.25_MHz
+//								|
+//								|-----→CLKDIV(/3.5)-----------------------------→CLK_60_MHz					
+// Dependencies:	
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module ClkGen (
+	input Clk24Mhz_i,
+
+	output Clk24Mhz_o,
+	output Clk100Mhz_o,
+	output Clk5Mhz_o,
+	output Clk20Mhz_o,
+	output Clk50Mhz_o,
+	output Clk26dot25Mhz_o,
+	output Clk60Mhz_o
+);
+
+//==========================================
+// Wires
+//==========================================
+wire clk100Mhz;
+wire clk210Mhz;
+wire clk20Mhz;
+wire clkBufg24Mhz;
+
+wire lockFirstPll;
+wire lockSecondPll;
+
+//==========================================
+// Assignments
+//==========================================
+assign Clk20Mhz_o = clk20Mhz;
+assign Clk24Mhz_o = clkBufg24Mhz;
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+GowinPllFirst GowinPllFirst100M50M (
+	.clkout		(clk100Mhz),
+	.lock		(lockFirstPll),
+	.clkoutd	(Clk50Mhz_o),
+	.clkin		(Clk24Mhz_i)
+);
+
+GowinClkDiv5 GowinClkDiv100MhzTo20Mhz (
+	.clkout		(clk20Mhz),
+	.hclkin		(clk100Mhz),
+	.resetn		(lockFirstPll)
+);
+
+GowinClkDiv4 GowinClkDiv20MhzTo5Mhz (
+	.clkout		(Clk5Mhz_o),
+	.hclkin		(clk20Mhz),
+	.resetn		(lockFirstPll)
+);
+
+BUFG BUFG_100Mhz (
+	.O			(Clk100Mhz_o),
+	.I			(clk100Mhz)
+);
+
+BUFG BUFG_24Mhz (
+	.O			(clkBufg24Mhz),
+	.I			(Clk24Mhz_i)
+);
+
+GowinPllSecond GowinPllSecond210M (
+	.clkout		(clk210Mhz),
+	.lock		(lockSecondPll),
+	.clkin		(Clk24Mhz_i)
+);
+
+GowinClkDiv8 GowinClkDiv210MhzTo26dot25 (
+	.clkout		(Clk26dot25Mhz_o),
+	.hclkin		(clk210Mhz),
+	.resetn		(lockSecondPll)
+);
+
+GowinClkDiv3dot5 GowinClkDiv210MhzTo60Mhz (
+	.clkout		(Clk60Mhz_o),
+	.hclkin		(clk210Mhz),
+	.resetn		(lockSecondPll)
+);
+
+endmodule

src/src/ClkGen/ClkGenTb.v

@@ -0,0 +1,27 @@
+`timescale 1ns / 1ns
+
+module ClkGenTb();
+
+GSR GSR(.GSRI(1'b1));
+
+reg Clk24;
+
+always #21 Clk24 = ~Clk24;
+
+initial begin
+	Clk24	=	1'b1;
+end	
+
+ClkGen DUT(
+	.Clk24Mhz_i			(Clk24),
+
+	.Clk24Mhz_o 		(),
+	.Clk100Mhz_o 		(),
+	.Clk5Mhz_o 			(),
+	.Clk20Mhz_o 		(),
+	.Clk50Mhz_o 		(),
+	.Clk26dot25Mhz_o 	(),
+	.Clk60Mhz_o 		()
+);
+
+endmodule

src/src/ClkGen/ClkGenWave.do

@@ -0,0 +1,32 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /ClkGenTb/DUT/Rst_i
+add wave -noupdate /ClkGenTb/DUT/Clk24Mhz_i
+add wave -noupdate /ClkGenTb/DUT/ClkBufg24Mhz_o
+add wave -noupdate /ClkGenTb/DUT/Clk100Mhz_o
+add wave -noupdate /ClkGenTb/DUT/Clk5Mhz_o
+add wave -noupdate /ClkGenTb/DUT/Clk20Mhz_o
+add wave -noupdate /ClkGenTb/DUT/Clk50Mhz_o
+add wave -noupdate /ClkGenTb/DUT/Clk26dot25Mhz_o
+add wave -noupdate /ClkGenTb/DUT/Clk60Mhz_o
+add wave -noupdate /ClkGenTb/DUT/clk100Mhz
+add wave -noupdate /ClkGenTb/DUT/clk210Mhz
+add wave -noupdate /ClkGenTb/DUT/clk20Mhz
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {963496245 ps} 0} {{Cursor 3} {263733718 ps} 0}
+quietly wave cursor active 2
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 53
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {192080876 ps} {318594555 ps}

src/src/ClkGen/GowinClkDiv3dot5/GowinClkDiv3dot5.ipc

@@ -0,0 +1,12 @@
+[General]
+ipc_version=4
+file=GowinClkDiv3dot5
+module=GowinClkDiv3dot5
+target_device=gw1n9c-046
+type=clock_clkdiv
+version=1.0
+
+[Config]
+Calibration=false
+Division_Factor=3.5
+Language=0

src/src/ClkGen/GowinClkDiv3dot5/GowinClkDiv3dot5.mod

@@ -0,0 +1,14 @@
+-series GW1N
+-device GW1N-9
+-device_version C
+-package PBGA256
+-part_number GW1N-LV9PG256C6/I5
+
+
+-mod_name GowinClkDiv3dot5
+-file_name GowinClkDiv3dot5
+-path C:/Gowin/Projects_GOWIN/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinClkDiv3dot5/
+-type CLKDIV
+-file_type vlg
+-division_factor 3.5
+-calib false

src/src/ClkGen/GowinClkDiv3dot5/GowinClkDiv3dot5.v

@@ -0,0 +1,30 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Tue Apr 23 12:08:22 2024
+
+module GowinClkDiv3dot5 (clkout, hclkin, resetn);
+
+output clkout;
+input hclkin;
+input resetn;
+
+wire gw_gnd;
+
+assign gw_gnd = 1'b0;
+
+CLKDIV clkdiv_inst (
+    .CLKOUT(clkout),
+    .HCLKIN(hclkin),
+    .RESETN(resetn),
+    .CALIB(gw_gnd)
+);
+
+defparam clkdiv_inst.DIV_MODE = "3.5";
+defparam clkdiv_inst.GSREN = "false";
+
+endmodule //GowinClkDiv3dot5

src/src/ClkGen/GowinClkDiv3dot5/GowinClkDiv3dot5_tmp.v

@@ -0,0 +1,19 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Tue Apr 23 12:08:22 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    GowinClkDiv3dot5 your_instance_name(
+        .clkout(clkout_o), //output clkout
+        .hclkin(hclkin_i), //input hclkin
+        .resetn(resetn_i) //input resetn
+    );
+
+//--------Copy end-------------------

src/src/ClkGen/GowinClkDiv4/GowinClkDiv4.ipc

@@ -0,0 +1,12 @@
+[General]
+ipc_version=4
+file=GowinClkDiv4
+module=GowinClkDiv4
+target_device=gw1n9c-046
+type=clock_clkdiv
+version=1.0
+
+[Config]
+Calibration=false
+Division_Factor=4
+Language=0

src/src/ClkGen/GowinClkDiv4/GowinClkDiv4.mod

@@ -0,0 +1,14 @@
+-series GW1N
+-device GW1N-9
+-device_version C
+-package PBGA256
+-part_number GW1N-LV9PG256C6/I5
+
+
+-mod_name GowinClkDiv4
+-file_name GowinClkDiv4
+-path C:/Gowin/Projects_GOWIN/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinClkDiv4/
+-type CLKDIV
+-file_type vlg
+-division_factor 4
+-calib false

src/src/ClkGen/GowinClkDiv4/GowinClkDiv4.v

@@ -0,0 +1,30 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Tue Apr 23 12:05:58 2024
+
+module GowinClkDiv4 (clkout, hclkin, resetn);
+
+output clkout;
+input hclkin;
+input resetn;
+
+wire gw_gnd;
+
+assign gw_gnd = 1'b0;
+
+CLKDIV clkdiv_inst (
+    .CLKOUT(clkout),
+    .HCLKIN(hclkin),
+    .RESETN(resetn),
+    .CALIB(gw_gnd)
+);
+
+defparam clkdiv_inst.DIV_MODE = "4";
+defparam clkdiv_inst.GSREN = "false";
+
+endmodule //GowinClkDiv4

src/src/ClkGen/GowinClkDiv4/GowinClkDiv4_tmp.v

@@ -0,0 +1,19 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Tue Apr 23 12:05:58 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    GowinClkDiv4 your_instance_name(
+        .clkout(clkout_o), //output clkout
+        .hclkin(hclkin_i), //input hclkin
+        .resetn(resetn_i) //input resetn
+    );
+
+//--------Copy end-------------------

src/src/ClkGen/GowinClkDiv5/GowinClkDiv5.ipc

@@ -0,0 +1,12 @@
+[General]
+ipc_version=4
+file=GowinClkDiv5
+module=GowinClkDiv5
+target_device=gw1n9c-046
+type=clock_clkdiv
+version=1.0
+
+[Config]
+Calibration=false
+Division_Factor=5
+Language=0

src/src/ClkGen/GowinClkDiv5/GowinClkDiv5.mod

@@ -0,0 +1,14 @@
+-series GW1N
+-device GW1N-9
+-device_version C
+-package PBGA256
+-part_number GW1N-LV9PG256C6/I5
+
+
+-mod_name GowinClkDiv5
+-file_name GowinClkDiv5
+-path C:/Gowin/Projects_GOWIN/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinClkDiv5/
+-type CLKDIV
+-file_type vlg
+-division_factor 5
+-calib false

src/src/ClkGen/GowinClkDiv5/GowinClkDiv5.v

@@ -0,0 +1,30 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Tue Apr 23 12:05:24 2024
+
+module GowinClkDiv5 (clkout, hclkin, resetn);
+
+output clkout;
+input hclkin;
+input resetn;
+
+wire gw_gnd;
+
+assign gw_gnd = 1'b0;
+
+CLKDIV clkdiv_inst (
+    .CLKOUT(clkout),
+    .HCLKIN(hclkin),
+    .RESETN(resetn),
+    .CALIB(gw_gnd)
+);
+
+defparam clkdiv_inst.DIV_MODE = "5";
+defparam clkdiv_inst.GSREN = "false";
+
+endmodule //GowinClkDiv5

src/src/ClkGen/GowinClkDiv5/GowinClkDiv5_tmp.v

@@ -0,0 +1,19 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Tue Apr 23 12:05:24 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    GowinClkDiv5 your_instance_name(
+        .clkout(clkout_o), //output clkout
+        .hclkin(hclkin_i), //input hclkin
+        .resetn(resetn_i) //input resetn
+    );
+
+//--------Copy end-------------------

src/src/ClkGen/GowinClkDiv8/GowinClkDiv8.ipc

@@ -0,0 +1,12 @@
+[General]
+ipc_version=4
+file=GowinClkDiv8
+module=GowinClkDiv8
+target_device=gw1n9c-046
+type=clock_clkdiv
+version=1.0
+
+[Config]
+Calibration=false
+Division_Factor=8
+Language=0

src/src/ClkGen/GowinClkDiv8/GowinClkDiv8.mod

@@ -0,0 +1,14 @@
+-series GW1N
+-device GW1N-9
+-device_version C
+-package PBGA256
+-part_number GW1N-LV9PG256C6/I5
+
+
+-mod_name GowinClkDiv8
+-file_name GowinClkDiv8
+-path C:/Gowin/Projects_GOWIN/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinClkDiv8/
+-type CLKDIV
+-file_type vlg
+-division_factor 8
+-calib false

src/src/ClkGen/GowinClkDiv8/GowinClkDiv8.v

@@ -0,0 +1,30 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Tue Apr 23 12:06:26 2024
+
+module GowinClkDiv8 (clkout, hclkin, resetn);
+
+output clkout;
+input hclkin;
+input resetn;
+
+wire gw_gnd;
+
+assign gw_gnd = 1'b0;
+
+CLKDIV clkdiv_inst (
+    .CLKOUT(clkout),
+    .HCLKIN(hclkin),
+    .RESETN(resetn),
+    .CALIB(gw_gnd)
+);
+
+defparam clkdiv_inst.DIV_MODE = "8";
+defparam clkdiv_inst.GSREN = "false";
+
+endmodule //GowinClkDiv8

src/src/ClkGen/GowinClkDiv8/GowinClkDiv8_tmp.v

@@ -0,0 +1,19 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Tue Apr 23 12:06:26 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    GowinClkDiv8 your_instance_name(
+        .clkout(clkout_o), //output clkout
+        .hclkin(hclkin_i), //input hclkin
+        .resetn(resetn_i) //input resetn
+    );
+
+//--------Copy end-------------------

src/src/ClkGen/GowinPllFirst/GowinPllFirst.ipc

@@ -0,0 +1,28 @@
+[General]
+ipc_version=4
+file=GowinPllFirst
+module=GowinPllFirst
+target_device=gw1n9c-046
+type=clock_rpll
+version=1.0
+
+[Config]
+CKLOUTD3=false
+CLKFB_SOURCE=0
+CLKIN_FREQ=24
+CLKOUTD=true
+CLKOUTD_BYPASS=false
+CLKOUTD_FREQ=50
+CLKOUTD_SOURCE_CLKOUT=true
+CLKOUTD_TOLERANCE=0
+CLKOUTP=false
+CLKOUT_BYPASS=false
+CLKOUT_DIVIDE_DYN=true
+CLKOUT_FREQ=100
+CLKOUT_TOLERANCE=0
+DYNAMIC=false
+LANG=0
+LOCK_EN=true
+MODE_GENERAL=true
+PLL_PWD=false
+RESET_PLL=false

src/src/ClkGen/GowinPllFirst/GowinPllFirst.mod

@@ -0,0 +1,34 @@
+-series GW1N
+-device GW1N-9
+-device_version C
+-package PBGA256
+-part_number GW1N-LV9PG256C6/I5
+
+
+-mod_name GowinPllFirst
+-file_name GowinPllFirst
+-path C:/Gowin/Projects_GOWIN/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinPllFirst/
+-type PLL
+-rPll true
+-file_type vlg
+-dev_type GW1N-9C
+-dyn_idiv_sel false
+-idiv_sel 6
+-dyn_fbdiv_sel false
+-fbdiv_sel 25
+-dyn_odiv_sel false
+-odiv_sel 4
+-dyn_sdiv_sel 2
+-dyn_da_en false
+-rst_sig false
+-rst_sig_p false
+-fclkin 24
+-clkfb_sel 0
+-en_lock true
+-clkout_bypass false
+-en_clkoutp false
+-clkoutp_bypass false
+-en_clkoutd true
+-clkoutd_bypass false
+-clkoutd_src CLKOUT
+-en_clkoutd3 false

src/src/ClkGen/GowinPllFirst/GowinPllFirst.v

@@ -0,0 +1,64 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Tue Apr 23 17:38:48 2024
+
+module GowinPllFirst (clkout, lock, clkoutd, clkin);
+
+output clkout;
+output lock;
+output clkoutd;
+input clkin;
+
+wire clkoutp_o;
+wire clkoutd3_o;
+wire gw_gnd;
+
+assign gw_gnd = 1'b0;
+
+rPLL rpll_inst (
+    .CLKOUT(clkout),
+    .LOCK(lock),
+    .CLKOUTP(clkoutp_o),
+    .CLKOUTD(clkoutd),
+    .CLKOUTD3(clkoutd3_o),
+    .RESET(gw_gnd),
+    .RESET_P(gw_gnd),
+    .CLKIN(clkin),
+    .CLKFB(gw_gnd),
+    .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd})
+);
+
+defparam rpll_inst.FCLKIN = "24";
+defparam rpll_inst.DYN_IDIV_SEL = "false";
+defparam rpll_inst.IDIV_SEL = 5;
+defparam rpll_inst.DYN_FBDIV_SEL = "false";
+defparam rpll_inst.FBDIV_SEL = 24;
+defparam rpll_inst.DYN_ODIV_SEL = "false";
+defparam rpll_inst.ODIV_SEL = 4;
+defparam rpll_inst.PSDA_SEL = "0000";
+defparam rpll_inst.DYN_DA_EN = "false";
+defparam rpll_inst.DUTYDA_SEL = "1000";
+defparam rpll_inst.CLKOUT_FT_DIR = 1'b1;
+defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1;
+defparam rpll_inst.CLKOUT_DLY_STEP = 0;
+defparam rpll_inst.CLKOUTP_DLY_STEP = 0;
+defparam rpll_inst.CLKFB_SEL = "internal";
+defparam rpll_inst.CLKOUT_BYPASS = "false";
+defparam rpll_inst.CLKOUTP_BYPASS = "false";
+defparam rpll_inst.CLKOUTD_BYPASS = "false";
+defparam rpll_inst.DYN_SDIV_SEL = 2;
+defparam rpll_inst.CLKOUTD_SRC = "CLKOUT";
+defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT";
+defparam rpll_inst.DEVICE = "GW1N-9C";
+
+endmodule //GowinPllFirst

src/src/ClkGen/GowinPllFirst/GowinPllFirst_tmp.v

@@ -0,0 +1,20 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Tue Apr 23 17:38:48 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    GowinPllFirst your_instance_name(
+        .clkout(clkout_o), //output clkout
+        .lock(lock_o), //output lock
+        .clkoutd(clkoutd_o), //output clkoutd
+        .clkin(clkin_i) //input clkin
+    );
+
+//--------Copy end-------------------

src/src/ClkGen/GowinPllSecond/GowinPllSecond.ipc

@@ -0,0 +1,24 @@
+[General]
+ipc_version=4
+file=GowinPllSecond
+module=GowinPllSecond
+target_device=gw1n9c-046
+type=clock_rpll
+version=1.0
+
+[Config]
+CKLOUTD3=false
+CLKFB_SOURCE=0
+CLKIN_FREQ=24
+CLKOUTD=false
+CLKOUTP=false
+CLKOUT_BYPASS=false
+CLKOUT_DIVIDE_DYN=true
+CLKOUT_FREQ=210
+CLKOUT_TOLERANCE=0
+DYNAMIC=false
+LANG=0
+LOCK_EN=true
+MODE_GENERAL=true
+PLL_PWD=false
+RESET_PLL=false

src/src/ClkGen/GowinPllSecond/GowinPllSecond.mod

@@ -0,0 +1,32 @@
+-series GW1N
+-device GW1N-9
+-device_version C
+-package PBGA256
+-part_number GW1N-LV9PG256C6/I5
+
+
+-mod_name GowinPllSecond
+-file_name GowinPllSecond
+-path C:/Gowin/Projects_GOWIN/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinPllSecond/
+-type PLL
+-rPll true
+-file_type vlg
+-dev_type GW1N-9C
+-dyn_idiv_sel false
+-idiv_sel 4
+-dyn_fbdiv_sel false
+-fbdiv_sel 35
+-dyn_odiv_sel false
+-odiv_sel 2
+-dyn_da_en false
+-rst_sig false
+-rst_sig_p false
+-fclkin 24
+-clkfb_sel 0
+-en_lock true
+-clkout_bypass false
+-en_clkoutp false
+-clkoutp_bypass false
+-en_clkoutd false
+-clkoutd_bypass false
+-en_clkoutd3 false

src/src/ClkGen/GowinPllSecond/GowinPllSecond.v

@@ -0,0 +1,64 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Tue Apr 23 17:39:37 2024
+
+module GowinPllSecond (clkout, lock, clkin);
+
+output clkout;
+output lock;
+input clkin;
+
+wire clkoutp_o;
+wire clkoutd_o;
+wire clkoutd3_o;
+wire gw_gnd;
+
+assign gw_gnd = 1'b0;
+
+rPLL rpll_inst (
+    .CLKOUT(clkout),
+    .LOCK(lock),
+    .CLKOUTP(clkoutp_o),
+    .CLKOUTD(clkoutd_o),
+    .CLKOUTD3(clkoutd3_o),
+    .RESET(gw_gnd),
+    .RESET_P(gw_gnd),
+    .CLKIN(clkin),
+    .CLKFB(gw_gnd),
+    .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd})
+);
+
+defparam rpll_inst.FCLKIN = "24";
+defparam rpll_inst.DYN_IDIV_SEL = "false";
+defparam rpll_inst.IDIV_SEL = 3;
+defparam rpll_inst.DYN_FBDIV_SEL = "false";
+defparam rpll_inst.FBDIV_SEL = 34;
+defparam rpll_inst.DYN_ODIV_SEL = "false";
+defparam rpll_inst.ODIV_SEL = 2;
+defparam rpll_inst.PSDA_SEL = "0000";
+defparam rpll_inst.DYN_DA_EN = "false";
+defparam rpll_inst.DUTYDA_SEL = "1000";
+defparam rpll_inst.CLKOUT_FT_DIR = 1'b1;
+defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1;
+defparam rpll_inst.CLKOUT_DLY_STEP = 0;
+defparam rpll_inst.CLKOUTP_DLY_STEP = 0;
+defparam rpll_inst.CLKFB_SEL = "internal";
+defparam rpll_inst.CLKOUT_BYPASS = "false";
+defparam rpll_inst.CLKOUTP_BYPASS = "false";
+defparam rpll_inst.CLKOUTD_BYPASS = "false";
+defparam rpll_inst.DYN_SDIV_SEL = 2;
+defparam rpll_inst.CLKOUTD_SRC = "CLKOUT";
+defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT";
+defparam rpll_inst.DEVICE = "GW1N-9C";
+
+endmodule //GowinPllSecond

src/src/ClkGen/GowinPllSecond/GowinPllSecond_tmp.v

@@ -0,0 +1,19 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.01 (64-bit)
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-9
+//Device Version: C
+//Created Time: Tue Apr 23 17:39:37 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    GowinPllSecond your_instance_name(
+        .clkout(clkout_o), //output clkout
+        .lock(lock_o), //output lock
+        .clkin(clkin_i) //input clkin
+    );
+
+//--------Copy end-------------------