Добавлены сигналы lock на выходе Pll. Сигналы lock используются как сброс для делителей. Иправлено название пина Clk24Mhz_o. Исправлена документация.

src/src/ClkGen/ClkGen.v

@@ -30,10 +30,9 @@
 //
 ////////////////////////////////////////////////////////////////////////////////////////////
 module ClkGen (
-	input Rst_i,
 	input Clk24Mhz_i,
 
-	output ClkBufg24Mhz_o,
+	output Clk24Mhz_o,
 	output Clk100Mhz_o,
 	output Clk5Mhz_o,
 	output Clk20Mhz_o,
@@ -50,17 +49,21 @@ wire clk210Mhz;
 wire clk20Mhz;
 wire clkBufg24Mhz;
 
+wire lockFirstPll;
+wire lockSecondPll;
+
 //==========================================
 // Assignments
 //==========================================
 assign Clk20Mhz_o = clk20Mhz;
-assign ClkBufg24Mhz_o = clkBufg24Mhz;
+assign Clk24Mhz_o = clkBufg24Mhz;
 
 //==========================================================================//
 //									CODING									//
 //==========================================================================//
 GowinPllFirst GowinPllFirst100M50M (
 	.clkout		(clk100Mhz),
+	.lock		(lockFirstPll),
 	.clkoutd	(Clk50Mhz_o),
 	.clkin		(Clk24Mhz_i)
 );
@@ -68,13 +71,13 @@ GowinPllFirst GowinPllFirst100M50M (
 GowinClkDiv5 GowinClkDiv100MhzTo20Mhz (
 	.clkout		(clk20Mhz),
 	.hclkin		(clk100Mhz),
-	.resetn		(~Rst_i)
+	.resetn		(lockFirstPll)
 );
 
 GowinClkDiv4 GowinClkDiv20MhzTo5Mhz (
 	.clkout		(Clk5Mhz_o),
 	.hclkin		(clk20Mhz),
-	.resetn		(~Rst_i)
+	.resetn		(lockFirstPll)
 );
 
 BUFG BUFG_100Mhz (
@@ -89,19 +92,20 @@ BUFG BUFG_24Mhz (
 
 GowinPllSecond GowinPllSecond210M (
 	.clkout		(clk210Mhz),
+	.lock		(lockSecondPll),
 	.clkin		(Clk24Mhz_i)
 );
 
 GowinClkDiv8 GowinClkDiv210MhzTo26dot25 (
 	.clkout		(Clk26dot25Mhz_o),
 	.hclkin		(clk210Mhz),
-	.resetn		(~Rst_i)
+	.resetn		(lockSecondPll)
 );
 
-GowinClkDiv3dot5 your_instance_name(
+GowinClkDiv3dot5 GowinClkDiv210MhzTo60Mhz (
 	.clkout		(Clk60Mhz_o),
 	.hclkin		(clk210Mhz),
-	.resetn		(~Rst_i)
+	.resetn		(lockSecondPll)
 );
 
 endmodule

src/src/ClkGen/ClkGenTb.v

@@ -5,22 +5,17 @@ module ClkGenTb();
 GSR GSR(.GSRI(1'b1));
 
 reg Clk24;
-reg rst;
 
 always #21 Clk24 = ~Clk24;
 
 initial begin
 	Clk24	=	1'b1;
-	rst		=	1'b1;
-#220000;
-	rst		=	1'b0;
 end	
 
 ClkGen DUT(
-	.Rst_i				(rst),
 	.Clk24Mhz_i			(Clk24),
 
-	.ClkBufg24Mhz_o 	(),
+	.Clk24Mhz_o 		(),
 	.Clk100Mhz_o 		(),
 	.Clk5Mhz_o 			(),
 	.Clk20Mhz_o 		(),

src/src/ClkGen/GowinPllFirst/GowinPllFirst.ipc

@@ -22,7 +22,7 @@ CLKOUT_FREQ=100
 CLKOUT_TOLERANCE=0
 DYNAMIC=false
 LANG=0
-LOCK_EN=false
+LOCK_EN=true
 MODE_GENERAL=true
 PLL_PWD=false
 RESET_PLL=false

src/src/ClkGen/GowinPllFirst/GowinPllFirst.mod

@@ -24,7 +24,7 @@
 -rst_sig_p false
 -fclkin 24
 -clkfb_sel 0
--en_lock false
+-en_lock true
 -clkout_bypass false
 -en_clkoutp false
 -clkoutp_bypass false

src/src/ClkGen/GowinPllFirst/GowinPllFirst.v

@@ -5,15 +5,15 @@
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
 //Device Version: C
-//Created Time: Tue Apr 23 11:52:55 2024
+//Created Time: Tue Apr 23 17:38:48 2024
 
-module GowinPllFirst (clkout, clkoutd, clkin);
+module GowinPllFirst (clkout, lock, clkoutd, clkin);
 
 output clkout;
+output lock;
 output clkoutd;
 input clkin;
 
-wire lock_o;
 wire clkoutp_o;
 wire clkoutd3_o;
 wire gw_gnd;
@@ -22,7 +22,7 @@ assign gw_gnd = 1'b0;
 
 rPLL rpll_inst (
     .CLKOUT(clkout),
-    .LOCK(lock_o),
+    .LOCK(lock),
     .CLKOUTP(clkoutp_o),
     .CLKOUTD(clkoutd),
     .CLKOUTD3(clkoutd3_o),

src/src/ClkGen/GowinPllFirst/GowinPllFirst_tmp.v

@@ -5,13 +5,14 @@
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
 //Device Version: C
-//Created Time: Tue Apr 23 11:52:55 2024
+//Created Time: Tue Apr 23 17:38:48 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
     GowinPllFirst your_instance_name(
         .clkout(clkout_o), //output clkout
+        .lock(lock_o), //output lock
         .clkoutd(clkoutd_o), //output clkoutd
         .clkin(clkin_i) //input clkin
     );

src/src/ClkGen/GowinPllSecond/GowinPllSecond.ipc

@@ -18,7 +18,7 @@ CLKOUT_FREQ=210
 CLKOUT_TOLERANCE=0
 DYNAMIC=false
 LANG=0
-LOCK_EN=false
+LOCK_EN=true
 MODE_GENERAL=true
 PLL_PWD=false
 RESET_PLL=false

src/src/ClkGen/GowinPllSecond/GowinPllSecond.mod

@@ -23,7 +23,7 @@
 -rst_sig_p false
 -fclkin 24
 -clkfb_sel 0
--en_lock false
+-en_lock true
 -clkout_bypass false
 -en_clkoutp false
 -clkoutp_bypass false

src/src/ClkGen/GowinPllSecond/GowinPllSecond.v

@@ -5,14 +5,14 @@
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
 //Device Version: C
-//Created Time: Tue Apr 23 11:59:12 2024
+//Created Time: Tue Apr 23 17:39:37 2024
 
-module GowinPllSecond (clkout, clkin);
+module GowinPllSecond (clkout, lock, clkin);
 
 output clkout;
+output lock;
 input clkin;
 
-wire lock_o;
 wire clkoutp_o;
 wire clkoutd_o;
 wire clkoutd3_o;
@@ -22,7 +22,7 @@ assign gw_gnd = 1'b0;
 
 rPLL rpll_inst (
     .CLKOUT(clkout),
-    .LOCK(lock_o),
+    .LOCK(lock),
     .CLKOUTP(clkoutp_o),
     .CLKOUTD(clkoutd_o),
     .CLKOUTD3(clkoutd3_o),

src/src/ClkGen/GowinPllSecond/GowinPllSecond_tmp.v

@@ -5,13 +5,14 @@
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
 //Device Version: C
-//Created Time: Tue Apr 23 11:59:12 2024
+//Created Time: Tue Apr 23 17:39:37 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
     GowinPllSecond your_instance_name(
         .clkout(clkout_o), //output clkout
+        .lock(lock_o), //output lock
         .clkin(clkin_i) //input clkin
     );