Обновил регистровую карту и назначение пинов для SB_TMSG44v2

src/constr/SbTmsg.cst

@@ -4,8 +4,14 @@
 //Tool Version: V1.9.9.03 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
-//Created Time: Fri 12 27 16:05:36 2024
+//Created Time: Wed 02 26 16:29:59 2025
 
+IO_LOC "FpgaLed_o" L16;
+IO_PORT "FpgaLed_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "HrCtrlFpga_o" J16;
+IO_PORT "HrCtrlFpga_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "LrCtrlFpga_o" J15;
+IO_PORT "LrCtrlFpga_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_LOC "DataMax2870MixRf2_o" C1;
 IO_PORT "DataMax2870MixRf2_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_LOC "ClkMax2870MixRf2_o" C2;
@@ -54,7 +60,7 @@ IO_LOC "DdsSaw1Fpga_o" E1;
 IO_PORT "DdsSaw1Fpga_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_LOC "GpioAdRfV2_o" C16;
 IO_PORT "GpioAdRfV2_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GpioAdRfV1_o" D15;
+IO_LOC "GpioAdRfV1_o" D16;
 IO_PORT "GpioAdRfV1_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_LOC "RefOffsetCtrlFpga_o" P1;
 IO_PORT "RefOffsetCtrlFpga_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
@@ -72,34 +78,30 @@ IO_LOC "PllVtuneCtrl_o" L2;
 IO_PORT "PllVtuneCtrl_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_LOC "AmAlc1Fix_o" A2;
 IO_PORT "AmAlc1Fix_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "SwCap1_o" A11;
+IO_LOC "SwCap1_o" A12;
 IO_PORT "SwCap1_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "SwCap2_o" A14;
+IO_LOC "SwCap2_o" A10;
 IO_PORT "SwCap2_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "SwCap3_o" A12;
-IO_PORT "SwCap3_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "AmAlcSw_o" A10;
+IO_LOC "AmAlcSw_o" A9;
 IO_PORT "AmAlcSw_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "SwCap4_o" A13;
-IO_PORT "SwCap4_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_LOC "DdsSyncFpga_o" R6;
 IO_PORT "DdsSyncFpga_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_LOC "DdsResetFpga_o" T5;
 IO_PORT "DdsResetFpga_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_LOC "DdsSyncCtrlFpga_o" T6;
 IO_PORT "DdsSyncCtrlFpga_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "CtrlAmSw3_o" J16;
+IO_LOC "CtrlAmSw3_o" K16;
 IO_PORT "CtrlAmSw3_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "RfSw2_o" H16;
+IO_LOC "RfSw2_o" G16;
 IO_PORT "RfSw2_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "RfSw1_o" G16;
+IO_LOC "RfSw1_o" H16;
 IO_PORT "RfSw1_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_PORT "AnyFlag_o" IO_TYPE=LVCMOS33;
-IO_LOC "RfLd_o" R8;
+IO_LOC "RfLd_o" R9;
 IO_PORT "RfLd_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "I2cScl_o" K16;
+IO_LOC "I2cScl_o" T8;
 IO_PORT "I2cScl_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "I2cSda_io" L16;
+IO_LOC "I2cSda_io" T7;
 IO_PORT "I2cSda_io" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_LOC "Mosi1_io" T12;
 IO_PORT "Mosi1_io" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
@@ -115,11 +117,11 @@ IO_LOC "Mosi2_i" T14;
 IO_PORT "Mosi2_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
 IO_LOC "Mosi0_i" R12;
 IO_PORT "Mosi0_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
-IO_LOC "Ss_i" T9;
+IO_LOC "Ss_i" R8;
 IO_PORT "Ss_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
 IO_LOC "Sck_i" T13;
 IO_PORT "Sck_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
-IO_LOC "Rst_i" R9;
+IO_LOC "Rst_i" T9;
 IO_PORT "Rst_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
 IO_LOC "Clk_i" H11;
 IO_PORT "Clk_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;

src/src/Top/TopSbTmsg.v

@@ -56,9 +56,9 @@ module TopSbTmsg
 	output DdsSyncCtrlFpga_o,
 	output DdsResetFpga_o,
 	output DdsSyncFpga_o,
-	output SwCap4_o,
+	output LrCtrlFpga_o,
 	output AmAlcSw_o,
-	output SwCap3_o,
+	output FpgaAlcDetSet_o,
 	output SwCap2_o,
 	output SwCap1_o,
 	output AmAlc1Fix_o,
@@ -73,6 +73,7 @@ module TopSbTmsg
 	output GpioAdRfV2_o,
 	output DdsSaw1Fpga_o,
 	output FpgaAmCtrl_o,
+	output HrCtrlFpga_o,
 
 	//Output SPI devices
 	output reg CsLmx94_o,
@@ -101,15 +102,21 @@ module TopSbTmsg
 
 	output reg CsMax2870MixRf2_o,
 	output reg ClkMax2870MixRf2_o,
-	output reg DataMax2870MixRf2_o
+	output reg DataMax2870MixRf2_o,
+
+	/* Led */
+	output     FpgaLed_o
+
 
 );
 
 //================================================================================
 //  LOCALPARAM
 
-localparam [11:0] BOARD_VER 	= 12'h1;
-localparam [11:0] FIRMWARE_VER	= 12'h1;	
+localparam [11:0] BOARD_VER 	= 12'h2;
+localparam [11:0] FIRMWARE_VER	= 12'h1;
+
+localparam LED_TICK_RATE = 48000000;//0.5Hz 24MHz
 
 //================================================================================
 //  REG/WIRE
@@ -199,9 +206,15 @@ localparam [11:0] FIRMWARE_VER	= 12'h1;
 
 	wire [23:0] servInfo;
 
+	/* LedCnt*/
+	reg [31:0] ledCnt;
+	/* LedReg */
+	reg ledReg;
+
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
+assign HrCtrlFpga_o			= gpio1CtrlData[23];
 assign FpgaAmCtrl_o			= gpio1CtrlData[22];
 assign DdsSaw1Fpga_o 		= gpio1CtrlData[21];
 assign GpioAdRfV2_o 		= gpio1CtrlData[20];
@@ -215,13 +228,12 @@ assign PllSyncCtrl_o 		= gpio1CtrlData[13];
 assign AmAlc1Fix_o 			= gpio1CtrlData[11];
 assign SwCap1_o 			= gpio1CtrlData[10];
 assign SwCap2_o 			= gpio1CtrlData[9];
-assign SwCap3_o 			= gpio1CtrlData[8];
+assign FpgaAlcDetSet_o 		= gpio1CtrlData[8];
 assign AmAlcSw_o 			= gpio1CtrlData[7];
-assign SwCap4_o 			= gpio1CtrlData[6];
+assign LrCtrlFpga_o 		= gpio1CtrlData[6];
 assign DdsResetFpga_o 		= gpio1CtrlData[4];
 assign DdsSyncCtrlFpga_o 	= gpio1CtrlData[3];
 assign CtrlAmSw3_o 			= gpio1CtrlData[2];
-// assign CtrlAmSw3_o 			= testTrig;		//Debug-only
 assign RfSw2_o 				= gpio1CtrlData[1];
 assign RfSw1_o 				= gpio1CtrlData[0];
 
@@ -233,8 +245,27 @@ assign AnyFlag_o = anyFlag;//Debug-only
 
 assign servInfo	= {BOARD_VER, FIRMWARE_VER};
 
+assign FpgaLed_o = ledReg;
+
 //================================================================================
 //  CODING
+/* Blink Led */
+always @(posedge Clk_i) begin
+    if (initRst) begin
+        ledCnt <= 0;
+        ledReg <= 1'b1;
+    end
+    else begin
+        if (ledCnt == LED_TICK_RATE) begin
+            ledReg <= ~ledReg;
+            ledCnt <= 0;
+        end
+        else begin
+            ledCnt <= ledCnt + 1;
+        end
+    end
+end
+
 always @(*) begin 
 	if (Rst_i) begin 
 		misoReg = 1'b0;