Merge branch 'dev' into Anatoliy/feature_FifoCtrl

src/src/Gpio2Read/ExtSpiMEmulGpio2Read.v

@@ -0,0 +1,205 @@
+`timescale 1ns / 1ps
+
+module ExtSpiMEmulGpio2Read 
+(
+	input Rst_i,
+	input Clk_i,
+	
+	input Start_i,
+	output TxDone_o,
+	
+	output Sck_o,
+	output reg Ss_o,
+	output reg Mosi_o
+	
+);
+
+//================================================================================
+//  PARAMETERS
+	localparam [1:0] IDLE = 0;
+	localparam [1:0] CMD = 1;
+	localparam [1:0] TX = 2;
+	localparam [1:0] PAUSE = 3;
+
+	parameter MODE = 1'h0;
+	parameter [4:0] DEVID = 5'h9;
+	parameter [16:0] WORDSNUM = 17'h1;
+	parameter EOPBIT = 1'b1;
+	
+//================================================================================
+//  REG/WIRE
+	reg [1:0] currState;
+	reg [1:0] nextState;
+	
+	reg	[6:0]	txCnt;
+	reg	[6:0]	cmdCnt;
+	reg	[3:0]	pauseCnt;
+
+	wire	txStop	=	(cmdCnt	>=	WORDSNUM+1);
+	
+	reg [23:0] headerCmd = {MODE,DEVID,WORDSNUM,EOPBIT};
+	reg [23:0] spiData;
+	
+	reg	[23:0]	dspSpiData;
+	
+	reg sckFlag;
+//================================================================================
+//  ASSIGNMENTS
+
+assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b1;
+assign	TxDone_o	=	(txStop & (currState== CMD));
+
+//================================================================================
+//  CODING
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	CMD)	begin
+			if	(!txStop)	begin
+				cmdCnt	<=	cmdCnt+1;
+			end else begin
+				cmdCnt <= 0;
+			end
+		end
+	end	else	begin
+		cmdCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	TX)	begin
+			txCnt	<=	txCnt+1;
+		end	else	begin
+			txCnt	<=	0;
+		end
+	end	else	begin
+		txCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	PAUSE)	begin
+			pauseCnt	<=	pauseCnt+1;
+		end	else	begin
+			pauseCnt	<=	0;
+		end
+	end	else	begin
+		pauseCnt	<=	0;
+	end
+end
+	
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	CMD)	begin
+			spiData	<=	spiData+cmdCnt;
+		end
+	end	else	begin
+		spiData	<=	24'hab;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(currState	==	CMD)	begin
+		if	(cmdCnt	==	0)	begin
+			dspSpiData		<=	headerCmd;
+		end	else	begin
+			dspSpiData		<=	spiData;
+		end	
+	end	else	if	(currState	==	TX)	begin
+		dspSpiData	<=	dspSpiData<<1;
+	end if	(currState	==	IDLE)	begin
+		dspSpiData	<=	0;
+	end
+end
+
+always	@(posedge Clk_i)	begin
+	if	(currState	==	TX)	begin
+		if	(txCnt	>=	7'd0)	begin
+			Mosi_o	<=	dspSpiData[23];
+		end	else	begin
+			Mosi_o	<=	1'b1;
+		end
+	end	else	begin
+		Mosi_o	<=	1'b1;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(currState	==	TX)	begin
+		Ss_o	<=	1'b0;
+		sckFlag	<=	1'b1;
+	end	else	begin
+		Ss_o	<=	1'b1;
+		sckFlag	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(Rst_i)	begin
+		currState	<=	IDLE;
+	end	else	begin
+		currState	<=	nextState;
+	end
+end
+
+always @(*) begin
+	nextState	=	IDLE;
+	case(currState)
+	IDLE	:	begin
+					if (Start_i)	begin
+						nextState = CMD;
+					end	else begin
+						nextState = IDLE;
+					end
+				end
+				
+	CMD	:		begin
+					if (!txStop)	begin
+						nextState = TX;
+					end	else begin
+						nextState = IDLE;
+					end
+				end
+
+	TX		:	begin
+					if (txCnt==6'd23) begin
+						nextState  = PAUSE;
+					end	else begin
+						nextState  = TX;
+					end
+				end
+        
+	PAUSE	:	begin
+					if (pauseCnt==4'd2) begin
+						nextState  = CMD;
+					end	else begin
+						nextState  = PAUSE;
+					end
+				end
+	endcase
+end
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/Gpio2Read/Gpio2Read.v

@@ -0,0 +1,72 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		Zaytsev Mikhail
+// 
+// Create Date:		26/04/2024 
+// Design Name: 
+// Module Name:		Gpio2Read 
+// Project Name:	SB_TMSG44V1_FPGA
+// Target Devices:	Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:		The module stores the current state of the LdLmx_i and LdMax_i lines 
+//					and sends this data over the MisoGpio2_o line when 
+//					requested by FlagDirectGpio2.
+//
+// Dependencies:	
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module Gpio2Read (
+	input Clk_i,
+	input Rst_i,
+
+	input ClkSpi_i,
+
+	input LdLmx_i,
+	input LdMax_i,
+
+	input FlagDirectGpio2_i,
+
+	output MisoGpio2_o
+);
+
+//==========================================
+// Registers
+//==========================================
+reg [1:0] gpio2Reg;
+
+//==========================================
+// Wires
+//==========================================
+
+//==========================================
+// Parameters
+//==========================================
+
+//==========================================
+// Assignments
+//==========================================
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		gpio2Reg <= 0;
+	end
+	else begin
+		gpio2Reg <= {LdMax_i, LdLmx_i};
+	end
+end
+
+SpiReadback SpiReadback_TempReg (
+	.ClkSpi_i		(ClkSpi_i),
+	.Rst_i			(Rst_i),
+	.RegData_i		( {22'b0, gpio2Reg} ),
+	.FlagDirect_i	(FlagDirectGpio2_i),
+	.Miso_o			(MisoGpio2_o)
+);
+
+endmodule

src/src/Gpio2Read/Gpio2ReadTb.v

@@ -0,0 +1,271 @@
+`timescale 1ns / 1ps
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company: Tair
+// Engineer: Zaytsev M.
+// 
+// Create Date:     
+// Design Name: 
+// Module Name:    Gpio2ReadTb
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module Gpio2ReadTb();
+
+//================================================================================
+//  REG/WIRE
+	
+	parameter OutWordWith = 24;
+	parameter SingleSpiWordWith = 24;
+	parameter QuadSpiWordWith = 6;
+	
+	localparam [1:0] IDLE = 0;
+	localparam [1:0] SINGLE = 1;
+	localparam [1:0] DELAY = 2;
+	localparam [1:0] QUAD = 3;
+	
+	reg SPIMODE = 1'b0; //0 - single 1- quad
+	
+	reg [31:0] tbCnt;
+	reg [31:0] delCnt;
+	reg stateCnt;
+	
+	reg Clk100;
+	reg Clk10;
+
+	reg Clk24;
+	
+	reg [1:0] currState;
+	reg [1:0] nextState;
+	
+	reg rst;
+	
+	wire txStart = (tbCnt == 100 | tbCnt == 3000);
+	wire txDoneS;
+	wire txDoneQ;
+	
+	
+	wire sckS;
+	wire sckQ;
+	wire ssS;
+	wire ssQ;
+	
+	wire ss;
+	wire sck;
+	
+	wire mosi0S;
+	wire mosi0Q;
+	wire mosi1Q;
+	wire mosi2Q;
+	wire mosi3Q;
+	
+	wire delDone = (delCnt == 500);
+//================================================================================
+//  ASSIGNMENTS
+	
+	assign sck = (currState==SINGLE) ? sckS:sckQ;
+	assign ss = (currState==SINGLE) ? ssS:ssQ;
+	assign mosi0 = (currState==SINGLE) ? mosi0S:mosi0Q;
+	assign mosi1 = (currState==SINGLE) ? 1'b1:mosi1Q;
+	assign mosi2 = (currState==SINGLE) ? 1'b1:mosi2Q;
+	assign mosi3 = (currState==SINGLE) ? 1'b1:mosi3Q;
+//================================================================================
+//clocks gen
+	always	#5 Clk100	=	~Clk100;	
+	always	#50 Clk10	=	~Clk10;	
+
+	always	#21 Clk24	=	~Clk24;
+	
+//================================================================================
+//  CODING
+
+initial begin
+	Clk100	=	1'b1;
+	Clk10	=	1'b1;
+	Clk24	= 	1'b1;
+	rst		=	1'b1;
+#100;
+	rst		=	1'b0;
+end	
+	
+always	@(negedge	Clk100)	begin
+	if	(!rst)		begin
+		tbCnt	<=	tbCnt+1;
+	end	else	begin
+		tbCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk100)	begin
+	if	(!rst)		begin
+		if (currState == DELAY) begin
+			delCnt	<=	delCnt+1;
+		end	else	begin
+			delCnt	<=	0;
+		end
+	end else	begin
+		delCnt	<=	0;
+	end
+end
+
+always	@(negedge	Clk10)	begin
+	if	(!rst)		begin
+		if (txDoneS|txDoneQ) begin
+			stateCnt	<=	stateCnt+1;
+		end	
+	end else begin
+		stateCnt <= 0;
+	end
+end
+
+always	@(posedge	Clk100)	begin
+	if	(!rst)		begin
+		case (stateCnt)
+			0:	begin
+					SPIMODE <= 1'b0;
+				end
+			1:	begin
+					SPIMODE <= 1'b1;
+				end
+			default:begin
+						SPIMODE <= 1'b0;
+					end
+		endcase
+	end else begin
+		SPIMODE <= 1'b0;
+	end
+end
+
+always	@(posedge	Clk100)	begin
+	if	(rst)	begin
+		currState	<=	IDLE;
+	end	else	begin
+		currState	<=	nextState;
+	end
+end
+
+
+always @(*) begin
+	nextState	=	IDLE;
+	case(currState)
+	IDLE	:	begin
+					if (txStart)	begin
+						case (SPIMODE)
+							1'b0:	begin
+											nextState = SINGLE;
+										end
+							1'b1:		begin
+											nextState = QUAD;
+										end
+						endcase
+					end	else begin
+						nextState = IDLE;
+					end
+				end
+				
+	SINGLE	:	begin
+					if (txDoneS)	begin
+						nextState = DELAY;
+					end	else begin
+						nextState = SINGLE;
+					end
+				end
+				
+	DELAY	:	begin
+					if (delDone)	begin
+						nextState = SINGLE;
+					end	else begin
+						nextState = DELAY;
+					end
+				end
+				
+	QUAD		:	begin
+					if (txDoneQ) begin
+						nextState  = IDLE;
+					end	else begin
+						nextState  = QUAD;
+					end
+				end
+	endcase
+end
+
+ExtSpiMEmulGpio2Read SingleSpiSm
+(
+	.Rst_i		(rst),
+	.Clk_i		(Clk10),
+	
+	.Start_i	((currState==SINGLE)),
+	.TxDone_o	(txDoneS),
+	
+	.Sck_o		(sckS),
+	.Ss_o		(ssS),
+	.Mosi_o		(mosi0S)
+	
+);
+
+wire dataValIntArb;
+wire [23:0] dataFromIntArb;
+wire flagDirectGpio2;
+
+InterfaceArbiter InterfaceArbiter
+(
+	.Rst_i		(rst),
+	.Clk_i		(Clk100),
+	
+	.Sck_i		(sck),
+	.Ss_i		(ss),
+	
+	.Mosi0_i	(mosi0),
+	.Mosi1_i	(mosi1),
+	.Mosi2_i	(mosi2),
+	.Mosi3_i	(mosi3),
+	
+	
+	.DataVal_o	(dataValIntArb),
+	.Data_o		(dataFromIntArb)
+);
+
+PacketAnalyzer1Mosi PacketAnalyzer1Mosi_inst (
+	.Clk_i					(Clk100),	
+	.Rst_i					(rst),	
+	
+	.DataFromSpi_i 			(dataFromIntArb),
+	.ValDataFromSpi_i 		(dataValIntArb),
+	
+	.BusyMosi4_i			(0),
+
+	.FlagDirectLmx_o		(),
+	.FlagDirectDds_o		(),
+	.FlagDirectPot_o		(),
+	.FlagDirectDac_o		(),
+	.FlagDirectAtt_o		(),
+	.FlagDirectShReg_o		(),
+	.FlagDirectMax_o		(),
+	.FlagDirectGpio1_o		(),
+	.FlagDirectTemp_o		(),
+	.FlagDirectGpio2_o		(flagDirectGpio2),
+
+	.Busy_o					()
+);
+
+Gpio2Read DUT(
+	.Clk_i					(Clk100),
+	.Rst_i					(rst),
+	.ClkSpi_i				(sckS),
+	.LdLmx_i				(0),
+	.LdMax_i				(1),
+	.FlagDirectGpio2_i		(flagDirectGpio2),
+	.MisoGpio2_o			()
+);
+
+endmodule

src/src/Gpio2Read/Gpio2ReadWave.do

@@ -0,0 +1,28 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /Gpio2ReadTb/DUT/Clk_i
+add wave -noupdate /Gpio2ReadTb/DUT/Rst_i
+add wave -noupdate /Gpio2ReadTb/DUT/ClkSpi_i
+add wave -noupdate /Gpio2ReadTb/DUT/LdLmx_i
+add wave -noupdate /Gpio2ReadTb/DUT/LdMax_i
+add wave -noupdate /Gpio2ReadTb/DUT/FlagDirectGpio2
+add wave -noupdate /Gpio2ReadTb/DUT/MisoGpio2_o
+add wave -noupdate /Gpio2ReadTb/DUT/gpio2Reg
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {7581547 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {15057656 ps}

src/src/TempRead/TempReadTb.v

@@ -258,8 +258,9 @@ PacketAnalyzer1Mosi PacketAnalyzer1Mosi_inst (
 	.FlagDirectAtt_o		(),
 	.FlagDirectShReg_o		(),
 	.FlagDirectMax_o		(),
-	.FlagDirectGpio_o		(),
+	.FlagDirectGpio1_o		(),
 	.FlagDirectTemp_o		(flagDirectTemp),
+	.FlagDirectGpio2_o		(),
 
 	.Busy_o					()
 );