Тесты

src/constr/SbTmsg.sdc

@@ -2,13 +2,19 @@
 //All rights reserved.
 //File Title: Timing Constraints file
 //Tool Version: V1.9.11.02 (64-bit) 
-//Created Time: 2025-06-09 11:49:38
-create_clock -name clk5 -period 200 -waveform {0 100} [get_nets {clk5}]
-create_clock -name clk60 -period 16.667 -waveform {0 8.334} [get_nets {clk60}]
+//Created Time: 2025-06-11 14:43:55
 create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
 create_clock -name Sck_i -period 16.667 -waveform {0 8.334} [get_ports {Sck_i}]
 create_generated_clock -name clk50 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 12 -multiply_by 25 [get_nets {clk50}]
+create_generated_clock -name clk210 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 4 -multiply_by 35 [get_nets {ClkGen/clk210Mhz}]
+create_generated_clock -name clk5 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 120 -multiply_by 25 [get_nets {clk5}]
+# create_generated_clock -name clk60 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 14 -multiply_by 35 [get_nets {clk60}]
+create_generated_clock -name clk26dot25 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 32 -multiply_by 35 [get_nets {clk26dot25}]
+create_generated_clock -name clk20 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 30 -multiply_by 25 [get_nets {clk20}]
+create_generated_clock -name clk100 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 6 -multiply_by 25 [get_nets {ClkGen/clk100Mhz}]
+set_clock_groups -asynchronous -group [get_clocks {Sck_i}] -group [get_clocks {Clk_i}]
 set_false_path -from [get_regs {InitRst/signal_o_s1}] 
-report_timing -hold -from_clock [get_clocks {clk60}] -to_clock [get_clocks {Sck_i}] -max_paths 100 -max_common_paths 1
-report_timing -hold -from_clock [get_clocks {Sck_i}] -to_clock [get_clocks {clk60}] -max_paths 100 -max_common_paths 1
-report_timing -setup -from [get_regs {DDSWrapper/ssReg_s0}] -to [get_regs {DDSWrapper/DdsSyncFpga_o_s0}]
+# report_timing -setup -from_clock [get_clocks {clk50}] -to_clock [get_clocks {clk60}] -max_paths 250 -max_common_paths 1
+# report_timing -setup -from_clock [get_clocks {clk60}] -to_clock [get_clocks {clk50}] -max_paths 250 -max_common_paths 1
+report_timing -setup -from_clock [get_clocks {clk50}] -to_clock [get_clocks {clk50}] -max_paths 100 -max_common_paths 1
+# report_timing -setup -from_clock [get_clocks {clk60}] -to_clock [get_clocks {clk60}] -max_paths 100 -max_common_paths 1

src/src/ClkGen/ClkGen.v

@@ -38,6 +38,8 @@ module ClkGen (
 	output Clk20Mhz_o,
 	output Clk50Mhz_o,
 	output Clk26dot25Mhz_o,
+	output LockFirstPll_o,
+	output Clk210Mhz_o,
 	output Clk60Mhz_o
 );
 
@@ -57,6 +59,8 @@ wire lockSecondPll;
 //==========================================
 assign Clk20Mhz_o = clk20Mhz;
 assign Clk24Mhz_o = clkBufg24Mhz;
+assign Clk210Mhz_o = clk210Mhz;
+assign LockFirstPll_o = lockFirstPll;
 
 //==========================================================================//
 //									CODING									//

src/src/ClkGen/GowinPllFirst/GowinPllFirst.ipc

@@ -12,17 +12,19 @@ CLKFB_SOURCE=0
 CLKIN_FREQ=24
 CLKOUTD=true
 CLKOUTD_BYPASS=false
-CLKOUTD_FREQ=50
 CLKOUTD_SOURCE_CLKOUT=true
-CLKOUTD_TOLERANCE=0
 CLKOUTP=false
 CLKOUT_BYPASS=false
-CLKOUT_DIVIDE_DYN=true
-CLKOUT_FREQ=100
-CLKOUT_TOLERANCE=0
+CLKOUT_DIVIDE_DYN=false
 DYNAMIC=false
 LANG=0
 LOCK_EN=true
-MODE_GENERAL=true
+MODE_GENERAL=false
 PLL_PWD=false
 RESET_PLL=false
+CLKFB_DIVIDE_DYNAMIC=false
+CLKFB_DIVIDE_STATIC_SEL=5
+CLKIN_DIVIDE_DYN=false
+CLKIN_DIVIDE_STATIC_SEL=1
+CLKOUTD_DIVIDE=4
+CLKOUT_DIVIDER=1

src/src/ClkGen/GowinPllFirst/GowinPllFirst.mod

@@ -7,18 +7,18 @@
 
 -mod_name GowinPllFirst
 -file_name GowinPllFirst
--path C:/Gowin/Projects_GOWIN/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinPllFirst/
+-path C:/Gowin/Projects/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinPllFirst/
 -type PLL
 -rPll true
 -file_type vlg
 -dev_type GW1N-9C
 -dyn_idiv_sel false
--idiv_sel 6
+-idiv_sel 1
 -dyn_fbdiv_sel false
--fbdiv_sel 25
+-fbdiv_sel 5
 -dyn_odiv_sel false
 -odiv_sel 4
--dyn_sdiv_sel 2
+-dyn_sdiv_sel 4
 -dyn_da_en false
 -rst_sig false
 -rst_sig_p false

src/src/ClkGen/GowinPllFirst/GowinPllFirst.v

@@ -1,11 +1,11 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: IP file
-//Tool Version: V1.9.9.01 (64-bit)
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
 //Device Version: C
-//Created Time: Tue Apr 23 17:38:48 2024
+//Created Time: Wed Jun 11 17:00:49 2025
 
 module GowinPllFirst (clkout, lock, clkoutd, clkin);
 
@@ -40,9 +40,9 @@ rPLL rpll_inst (
 
 defparam rpll_inst.FCLKIN = "24";
 defparam rpll_inst.DYN_IDIV_SEL = "false";
-defparam rpll_inst.IDIV_SEL = 5;
+defparam rpll_inst.IDIV_SEL = 0;
 defparam rpll_inst.DYN_FBDIV_SEL = "false";
-defparam rpll_inst.FBDIV_SEL = 24;
+defparam rpll_inst.FBDIV_SEL = 4;
 defparam rpll_inst.DYN_ODIV_SEL = "false";
 defparam rpll_inst.ODIV_SEL = 4;
 defparam rpll_inst.PSDA_SEL = "0000";
@@ -56,7 +56,7 @@ defparam rpll_inst.CLKFB_SEL = "internal";
 defparam rpll_inst.CLKOUT_BYPASS = "false";
 defparam rpll_inst.CLKOUTP_BYPASS = "false";
 defparam rpll_inst.CLKOUTD_BYPASS = "false";
-defparam rpll_inst.DYN_SDIV_SEL = 2;
+defparam rpll_inst.DYN_SDIV_SEL = 4;
 defparam rpll_inst.CLKOUTD_SRC = "CLKOUT";
 defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT";
 defparam rpll_inst.DEVICE = "GW1N-9C";

src/src/ClkGen/GowinPllFirst/GowinPllFirst_tmp.v

@@ -1,20 +1,20 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.01 (64-bit)
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
 //Device Version: C
-//Created Time: Tue Apr 23 17:38:48 2024
+//Created Time: Wed Jun 11 17:00:49 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
     GowinPllFirst your_instance_name(
-        .clkout(clkout_o), //output clkout
-        .lock(lock_o), //output lock
-        .clkoutd(clkoutd_o), //output clkoutd
-        .clkin(clkin_i) //input clkin
+        .clkout(clkout), //output clkout
+        .lock(lock), //output lock
+        .clkoutd(clkoutd), //output clkoutd
+        .clkin(clkin) //input clkin
     );
 
 //--------Copy end-------------------

src/src/ClkGen/GowinPllSecond/GowinPllSecond.ipc

@@ -13,12 +13,15 @@ CLKIN_FREQ=24
 CLKOUTD=false
 CLKOUTP=false
 CLKOUT_BYPASS=false
-CLKOUT_DIVIDE_DYN=true
-CLKOUT_FREQ=210
-CLKOUT_TOLERANCE=0
+CLKOUT_DIVIDE_DYN=false
 DYNAMIC=false
 LANG=0
 LOCK_EN=true
-MODE_GENERAL=true
+MODE_GENERAL=false
 PLL_PWD=false
 RESET_PLL=false
+CLKFB_DIVIDE_DYNAMIC=false
+CLKFB_DIVIDE_STATIC_SEL=9
+CLKIN_DIVIDE_DYN=false
+CLKIN_DIVIDE_STATIC_SEL=1
+CLKOUT_DIVIDER=1

src/src/ClkGen/GowinPllSecond/GowinPllSecond.mod

@@ -7,17 +7,17 @@
 
 -mod_name GowinPllSecond
 -file_name GowinPllSecond
--path C:/Gowin/Projects_GOWIN/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinPllSecond/
+-path C:/Gowin/Projects/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinPllSecond/
 -type PLL
 -rPll true
 -file_type vlg
 -dev_type GW1N-9C
 -dyn_idiv_sel false
--idiv_sel 4
+-idiv_sel 1
 -dyn_fbdiv_sel false
--fbdiv_sel 35
+-fbdiv_sel 9
 -dyn_odiv_sel false
--odiv_sel 2
+-odiv_sel 4
 -dyn_da_en false
 -rst_sig false
 -rst_sig_p false

src/src/ClkGen/GowinPllSecond/GowinPllSecond.v

@@ -1,11 +1,11 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: IP file
-//Tool Version: V1.9.9.01 (64-bit)
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
 //Device Version: C
-//Created Time: Tue Apr 23 17:39:37 2024
+//Created Time: Wed Jun 11 17:16:11 2025
 
 module GowinPllSecond (clkout, lock, clkin);
 
@@ -40,11 +40,11 @@ rPLL rpll_inst (
 
 defparam rpll_inst.FCLKIN = "24";
 defparam rpll_inst.DYN_IDIV_SEL = "false";
-defparam rpll_inst.IDIV_SEL = 3;
+defparam rpll_inst.IDIV_SEL = 0;
 defparam rpll_inst.DYN_FBDIV_SEL = "false";
-defparam rpll_inst.FBDIV_SEL = 34;
+defparam rpll_inst.FBDIV_SEL = 8;
 defparam rpll_inst.DYN_ODIV_SEL = "false";
-defparam rpll_inst.ODIV_SEL = 2;
+defparam rpll_inst.ODIV_SEL = 4;
 defparam rpll_inst.PSDA_SEL = "0000";
 defparam rpll_inst.DYN_DA_EN = "false";
 defparam rpll_inst.DUTYDA_SEL = "1000";

src/src/ClkGen/GowinPllSecond/GowinPllSecond_tmp.v

@@ -1,19 +1,19 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.01 (64-bit)
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
 //Device Version: C
-//Created Time: Tue Apr 23 17:39:37 2024
+//Created Time: Wed Jun 11 17:16:11 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
     GowinPllSecond your_instance_name(
-        .clkout(clkout_o), //output clkout
-        .lock(lock_o), //output lock
-        .clkin(clkin_i) //input clkin
+        .clkout(clkout), //output clkout
+        .lock(lock), //output lock
+        .clkin(clkin) //input clkin
     );
 
 //--------Copy end-------------------

src/src/InterfaceArbiter/InterfaceArbiter.v

@@ -19,8 +19,7 @@
 // Additional Comments: 
 //
 //////////////////////////////////////////////////////////////////////////////////
-
-module InterfaceArbiter 
+module InterfaceArbiter
 #(	
 	parameter OUTWORDWIDTH = 24,
 	parameter SSPIWORDWIDTH = 24,
@@ -38,17 +37,16 @@ module InterfaceArbiter
 	input Mosi2_i,
 	input Mosi3_i,
 	
-	
-	output DataVal_o,
 	output reg TestTrig_o,
+	output reg DataVal_o,
 	output [OUTWORDWIDTH-1:0] Data_o
 );
 
 //================================================================================
 //  REG/WIRE
 
-	localparam [1:0] IDLE = 2'b01;
-	localparam [1:0] DATARX = 2'b10;
+	localparam [1:0] IDLE = 0;
+	localparam [1:0] DATARX = 1;
 	
 	reg [OUTWORDWIDTH-1:0] dataRegSSpi;
 	reg [OUTWORDWIDTH-1:0] dataRegQSpi;
@@ -59,28 +57,14 @@ module InterfaceArbiter
 	reg [QSPIWORDWIDTH-1:0] captReg1;
 	reg [QSPIWORDWIDTH-1:0] captReg2;
 	reg [QSPIWORDWIDTH-1:0] captReg3;
-
-	reg [OUTWORDWIDTH-1:0] captRegSspiR;
-	reg [OUTWORDWIDTH-1:0] captRegSspiRR;
-
-	reg [QSPIWORDWIDTH-1:0] captReg0R;
-	reg [QSPIWORDWIDTH-1:0] captReg0RR;
-	reg [QSPIWORDWIDTH-1:0] captReg1R;
-	reg [QSPIWORDWIDTH-1:0] captReg1RR;
-	reg [QSPIWORDWIDTH-1:0] captReg2R;
-	reg [QSPIWORDWIDTH-1:0] captReg2RR;
-	reg [QSPIWORDWIDTH-1:0] captReg3R;
-	reg [QSPIWORDWIDTH-1:0] captReg3RR;
-
-	reg ssReg;
-	reg ssRegR;
-	reg ssRegRR;
 	
-	reg spiMode;
 	
-	wire ssPos;
-	reg ssPosR;
+	reg spiMode;
+	reg spiModeSyncA;
+	reg spiModeSyncB;
 	
+	wire dataVal;
+	wire dataValNeg;
 	reg dataValReg;
 	
 	reg [OUTWORDWIDTH/4-1:0] ssCnt;
@@ -93,88 +77,26 @@ module InterfaceArbiter
 	reg [1:0] currState;
 	
 	reg rxDone;
-
-	wire plsToggleSyncSignal;
-	reg plsToggle;
-	reg plsToggleSyncA;
-	reg plsToggleSyncB;
-	reg plsToggleSyncC;
-	reg plsToggleSyncSignalR;
-
-	/* SpiMode Sync Signals */
-	reg spiModeSyncA;
-	reg spiModeSyncB;
-
 //================================================================================
 //  ASSIGNMENTS
-	assign ssPos = ssRegR & !ssRegRR;
 
 	
-	assign DataVal_o = plsToggleSyncSignalR;
+	// assign DataVal_o = dataValReg;
 	assign Data_o = (spiModeSyncB)? dataRegQSpi:dataRegSSpi;
-
-	assign plsToggleSyncSignal = plsToggleSyncC^plsToggleSyncB;
-
-	//assign ssCntRstThresh = (spiMode) ? QSPIWORDWIDTH-1:SSPIWORDWIDTH-1;
 	
 //================================================================================
 //  CODING
 
 	always @(posedge Clk_i) begin 
-    	if (Rst_i) begin 
-    	    plsToggleSyncA <= 1'b0;
-    	    plsToggleSyncB <= 1'b0;
-    	end
-    	else begin 
-    	    plsToggleSyncA <= plsToggle;
-    	    plsToggleSyncB <= plsToggleSyncA;
-    	end
-	end
-
-	always @(posedge Clk_i) begin 
-		if (Rst_i) begin 
-			spiModeSyncA <= 1'b0;
-			spiModeSyncB <= 1'b0;
-		end
-		else begin 
-			spiModeSyncA <= spiMode;
-			spiModeSyncB <= spiModeSyncA;
-		end
-	end
-
-	always @(posedge Clk_i) begin 
-	    if (Rst_i) begin 
-	        plsToggleSyncC <= 1'b0;
-	    end
-	    else begin
-	        plsToggleSyncC <= plsToggleSyncB;
-	    end
-	end
-	
-	always @(posedge Ss_i or posedge Rst_i) begin 
 		if (Rst_i) begin 
-			plsToggle <= 1'b0;
+			DataVal_o <= 1'b0;
 		end
 		else begin 
-			if (Ss_i) begin 
-				plsToggle <= ~plsToggle;
-			end
-			else begin 
-				plsToggle <= plsToggle;
-			end
+			DataVal_o <= dataValReg;
 		end
 	end
 
-	always @(posedge Clk_i) begin 
-		if (Rst_i) begin 
-			plsToggleSyncSignalR <= 1'b0;
-		end
-		else begin 
-			plsToggleSyncSignalR <= plsToggleSyncSignal;
-		end
-	end
-
-	always @(posedge Sck_i or posedge Rst_i) begin 
+	always @(posedge Sck_i) begin 
 		if (Rst_i) begin 
 			captRegSspi <= 0;
 
@@ -195,40 +117,6 @@ module InterfaceArbiter
 		end
 	end
 
-	always @(posedge Clk_i) begin 
-		if (Rst_i) begin 
-			captRegSspiR <= 0;
-			captRegSspiRR <= 0;
-		end
-		else begin 
-			captRegSspiR <= captRegSspi;
-			captRegSspiRR <= captRegSspiR;
-		end
-	end
-
-	always @(posedge Clk_i) begin 
-		if (Rst_i) begin 
-			captReg0R <= 0;
-			captReg0RR <= 0;
-			captReg1R <= 0;
-			captReg1RR <= 0;
-			captReg2R <= 0;
-			captReg2RR <= 0;
-			captReg3R <= 0;
-			captReg3RR <= 0;
-		end
-		else begin 
-			captReg0R <= captReg0;
-			captReg0RR <= captReg0R;
-			captReg1R <= captReg1;
-			captReg1RR <= captReg1R;
-			captReg2R <= captReg2;
-			captReg2RR <= captReg2R;
-			captReg3R <= captReg3;
-			captReg3RR <= captReg3R;
-		end
-	end
-
 	always @(*) begin
 		if (currState == IDLE && (Data_o[11]& Data_o[8])) begin
 			TestTrig_o = 1'b1;
@@ -238,17 +126,13 @@ module InterfaceArbiter
 		end
 	end
 
-	always @(posedge Sck_i or posedge Rst_i) begin 
-		if (Rst_i) begin 
+	always @(posedge Sck_i or posedge Ss_i) begin 
+		if (Ss_i) begin 
 			ssCnt <= 0;
 		end
 		else begin 
-			if (currState == IDLE) begin
-				if (!Ss_i) begin 
-					ssCnt <= ssCnt+1; 
-				end
-			end else begin
-				ssCnt <= 0;
+			if (!Ss_i) begin 
+				ssCnt <= ssCnt+1; 
 			end
 		end
 	end
@@ -256,7 +140,7 @@ module InterfaceArbiter
 	always @(posedge Clk_i) begin
 		if (!Rst_i) begin
 			if (currState == DATARX) begin
-				if (plsToggleSyncSignal) begin
+				if (dataVal) begin
 					if (wordsCnt == wordsNum-1) begin
 						wordsCnt <= 0;
 						rxDone <= 1'b1;
@@ -275,67 +159,57 @@ module InterfaceArbiter
 		end
 	end
 	
-	always @(posedge Sck_i or posedge Rst_i) begin 
+	always @(posedge Sck_i) begin 
 		if (Rst_i) begin 
 			spiMode <= 1'b0;
 		end
 		else begin
 			if (currState == IDLE) begin 
 				if (ssCnt == 1) begin 
-					if (captRegSspi[0]) begin 
-						spiMode <= 1'b1; 
-					end 
-					else begin 
-						spiMode <= 1'b0; 
-					end
+					spiMode <= captRegSspi[0]; 
 				end
 			end
 		end
 	end
-	
+
+	always @(posedge Clk_i) begin 
+		if (Rst_i) begin 
+			spiModeSyncA <= 1'b0;
+			spiModeSyncB <= 1'b0;
+		end
+		else begin 
+			spiModeSyncA <= spiMode;
+			spiModeSyncB <= spiModeSyncA;
+		end
+	end
+
+	always @(posedge Clk_i) begin
+		if (!Rst_i) begin
+			dataValReg <= dataVal;
+			if (dataVal) begin
+				dataRegSSpi <= captRegSspi;
+				dataRegQSpi <= {captReg0,captReg1,captReg2,captReg3};
+			end 
+		end else begin
+			dataRegSSpi <= 0;
+			dataRegQSpi <= 0;
+			dataValReg <= 0;
+		end
+	end
+
 	always @(posedge Clk_i) begin
 		if (!Rst_i) begin
 			if (currState == IDLE) begin
-				if (!spiMode) begin
+				if (!spiModeSyncB) begin
 					wordsNum <= dataRegSSpi[17:1];
 				end else begin
-					wordsNum <= dataRegQSpi[21:19]+dataRegQSpi[17:16]+dataRegQSpi[15:12]+dataRegQSpi[11:9]+dataRegQSpi[7:6]+dataRegQSpi[4:3]+dataRegQSpi[2]+dataRegQSpi[1];
+					wordsNum <= dataRegQSpi[21:19]+dataRegQSpi[17:16]+dataRegQSpi[15:12]+dataRegQSpi[10:9]+dataRegQSpi[7:6]+dataRegQSpi[4:3]+dataRegQSpi[2]+dataRegQSpi[1];
 				end 
 			end
 		end else begin
 			wordsNum <= 0;
 		end
 	end 
-	
-	always @(posedge Clk_i) begin
-		if (!Rst_i) begin
-			ssReg <= Ss_i;
-			ssRegR <= ssReg;
-			ssRegRR <= ssRegR;
-			ssPosR <= ssPos;
-		end else begin
-			ssReg <= 1;
-			ssRegR <= 1;
-			ssRegRR <= 1;
-			ssPosR <= 0;
-		end
-	end 
-	
-	always @(posedge Clk_i) begin
-		if (!Rst_i) begin
-			if (plsToggleSyncSignal) begin
-				dataRegSSpi <= captRegSspiRR;
-				dataRegQSpi <= {captReg0R,captReg1R,captReg2R,captReg3R};
-				dataValReg <= 1'b1;
-			end else begin
-				dataValReg <= 1'b0;
-			end
-		end else begin
-			dataRegSSpi <= 0;
-			dataRegQSpi <= 0;
-			dataValReg <= 0;
-		end
-	end
 
 	always @(posedge Clk_i) begin
 		if (Rst_i) begin
@@ -349,7 +223,7 @@ module InterfaceArbiter
 		nextState = IDLE;
 		case(currState)
 		IDLE		:begin
-						if (plsToggleSyncSignalR)	begin
+						if (dataValReg)	begin
 							nextState = DATARX;
 						end	else begin
 							nextState = IDLE;
@@ -366,23 +240,25 @@ module InterfaceArbiter
 		endcase
 	end
 
-endmodule
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+	edgeDetectingSynchronizer#
+	( 
+		.Length(2),
+		.EdgeType("rising")
+	) edgeDetectingSynchronizer (		
+		.Rst_i(1'b0),	
+		.Clk_i(Clk_i),
+		.D_i(Ss_i),
+		.D_o(dataVal)
+	);
+
+	// edgeDetectingSynchronizer#
+	// ( 
+	// 	.Length(2),
+	// 	.EdgeType("falling")
+	// ) edgeDetectingSynchronizer2 (		
+	// 	.Rst_i(1'b0),	
+	// 	.Clk_i(Clk_i),
+	// 	.D_i(dataVal),
+	// 	.D_o(dataValNeg)
+	// );
+endmodule

src/src/Synchronizer/synchronizer.v

@@ -0,0 +1,175 @@
+//---------------------------------------------------
+//------------- BASIC SYNCHRONIZER ------------------
+//---------------------------------------------------
+module basicSynchronizer #
+(	parameter Length = 2)
+(	
+	input Rst_i,	
+	input Clk_i,
+	input D_i,
+	output D_o
+);
+
+	reg [Length-1 : 0] dReg;
+
+	always @ (posedge Rst_i or posedge Clk_i)
+		if (Rst_i)
+			dReg <= 0;
+		else
+			dReg <= {dReg[Length-2 : 0], D_i};
+	
+	assign D_o = dReg[Length - 1];
+	
+endmodule
+
+//---------------------------------------------------
+//--------- EDGE-DETECTING SYNCHRONIZER -------------
+//---------------------------------------------------
+
+module edgeDetectingSynchronizer #
+( 
+	parameter Length = 2,
+	parameter EdgeType = "rising"
+)
+(		
+	input Rst_i,	
+	input Clk_i,
+	input D_i,
+	output D_o
+);
+
+	wire basicSyncOut;
+	reg outReg;
+
+	basicSynchronizer # (.Length(Length)) 
+	basicSynch (
+		.Rst_i(Rst_i),
+		.Clk_i(Clk_i),
+		.D_i(D_i),
+		.D_o(basicSyncOut)
+	);
+		
+	always @ (posedge Rst_i or posedge Clk_i)
+		if (Rst_i)
+			outReg <= 0;
+		else
+			outReg <= basicSyncOut;
+			
+	generate 
+		if (EdgeType == "rising")
+			assign D_o = (basicSyncOut & (~outReg));
+		else
+			assign D_o = ((~basicSyncOut) & (outReg));
+	endgenerate
+	
+endmodule
+
+
+//--------------------------------------------------------------------------
+//------------- FAST-TO-SLOW FREQUENCY DOMAIN SYNCHRONIZER -----------------
+//--------------------------------------------------------------------------
+module fastToSlowSynch
+(		
+	input Rst_i,	
+	input Clk_i,
+	input D_i,
+	output D_o
+);
+
+	reg din_r, dout_r, rsti;
+	
+	wire rsts = (Rst_i || rsti);
+	
+	always @ (posedge rsts or posedge D_i)
+		if (rsts)
+			din_r <= 0;
+		else
+			din_r <= 1;
+			
+	always @ (posedge Rst_i or posedge Clk_i)
+		if (Rst_i)
+			begin
+				dout_r <= 0;
+				rsti <= 0;
+			end
+		else 
+			if (din_r)
+				begin
+					dout_r <= 1;
+					rsti <= 1;
+				end
+			else if (dout_r)
+				begin
+					dout_r <= 0;
+					rsti <= 0;
+				end
+
+	assign D_o = dout_r;	
+	
+endmodule
+
+//--------------------------------------------------------------------------
+//------------- FAST-TO-SLOW FREQUENCY DOMAIN SYNCHRONIZER -----------------
+//--------------------------------------------------------------------------
+module fastToSlowSynchPosPulseStretch #
+(
+	parameter StretchInClock = 2,
+	parameter SyncLength = 2
+)
+(		
+	input Rst_i,
+	input D_i,
+	output D_o,
+	input ClkIn_i,
+	input ClkOut_i
+);
+
+	reg dStretched;
+	generate 
+		if (StretchInClock > 2)
+			begin
+				reg [StretchInClock-2:0] dShReg;
+				always @ (posedge ClkIn_i or posedge Rst_i)
+					if (Rst_i)
+						begin
+							dShReg <= 0;
+							dStretched <= 0;
+						end
+					else
+						begin
+							dShReg <= {dShReg[StretchInClock-3:0], D_i};
+							dStretched <= (D_i || (dShReg != 0)) ? 1 : 0;
+						end
+			end
+		else if (StretchInClock == 2)
+			begin
+				reg dReg;
+				always @ (posedge ClkIn_i or posedge Rst_i)
+					if (Rst_i)
+						begin
+							dReg <= 0;
+							dStretched <= 0;
+						end
+					else
+						begin
+							dReg <= D_i;
+							dStretched <= dReg | D_i;
+						end
+			end
+	endgenerate
+	
+	edgeDetectingSynchronizer #
+	( 
+		.Length(SyncLength),
+		.EdgeType("rising")
+	)
+	edgeSyncInst
+	(		
+		.Rst_i(Rst_i),
+		.Clk_i(ClkOut_i),
+		.D_i(dStretched),
+		.D_o(D_o)
+	);	
+	
+endmodule
+

src/src/Top/TopSbTmsg.v

@@ -202,6 +202,9 @@ localparam LED_TICK_RATE = 48000000;//0.5Hz 24MHz
 	//InitRst
 	wire initRst;
 
+	/* Lock First PLL */
+	wire lockFirstPll;
+
 	reg misoReg;
 
 	wire [23:0] servInfo;
@@ -245,7 +248,7 @@ assign AnyFlag_o = anyFlag;//Debug-only
 
 assign servInfo	= {BOARD_VER, FIRMWARE_VER};
 
-assign FpgaLed_o = ledReg;
+assign FpgaLed_o = clk60;
 // assign FpgaLed_o = 1'b1; //Golden-Image
 
 //================================================================================
@@ -381,6 +384,7 @@ ClkGen ClkGen
 	.Clk5Mhz_o			(clk5),
 	.Clk20Mhz_o			(clk20),
 	.Clk50Mhz_o			(clk50),
+	.LockFirstPll_o		(lockFirstPll),
 	.Clk26dot25Mhz_o	(clk26dot25),
 	.Clk60Mhz_o			(clk60)
 );

src/src/Top/TopSbTmsgTb.sv

@@ -131,7 +131,7 @@ localparam        POTWordNum = 2'd2;
 localparam        DACWordNum = 1'd1;
 localparam        ATTWordNum = 1'd1;
 localparam [1:0]  ShRegWordNum = 2'd1;
-localparam [2:0]  MaxWordNum =   3'd4;
+localparam [2:0]  MaxWordNum =   3'd2;
 localparam [1:0]  GPIOWordNum =  2'd1;
 
 localparam [23:0] Max2870Header         = {1'h1, 1'h0, 3'h0, 1'h0, 2'h0, 4'h0, 1'h0, MaxWordNum, 1'h0, 2'h0, 1'h0, 2'h0, 1'h0, 1'h0, 1'h1};
@@ -179,7 +179,7 @@ assign Mosi0_o = (modeSel) ? mosi0Q : mosi0R;
 assign Mosi1_io = (anyFlag) ? 1'bz : Mosi1_o;
 assign MisoLdLmx_i = 1'b1;
 
-assign emptyFlagTx = (trCnt > 74) ? 1'b1 : 1'b0;
+assign emptyFlagTx = (trCnt > 71) ? 1'b1 : 1'b0;
 assign QSPITotalWordNum = LMXWordNum + DDSWordNum + POTWordNum + DACWordNum + ATTWordNum + ShRegWordNum + MaxWordNum + GPIOWordNum; 
 
 assign currClk = (modeSel) ? Clk60 : Clk10;
@@ -326,7 +326,7 @@ always_comb begin
     else begin 
         // if (!rstInit && locked) begin
             if (trCnt == 0) begin 
-                SPIdata = AllDevQSPIHeader;
+                SPIdata = InitGpio1Header;
             end
             else if (trCnt == 2) begin 
                 SPIdata = InitGpio1Header;

src/src/WrapFifoChain/DDSWrapper.v

@@ -57,11 +57,24 @@ wire ddsFifoEmpty;
 
 reg ssR;
 reg ssReg;
-reg ddsDirectFlagR;
+// reg ddsDirectFlagR;
+reg ddsDirectFlagSyncA;
+reg ddsDirectFlagSyncB;
+reg ddsDirectFlagSyncC;
 reg [2:0] ddsWordNumReg;
-reg [2:0] ddsWordNumRegSync;
+reg [2:0] ddsWordNumRegRdDomain;
+reg [2:0] ddsWordNumRegSyncA;
+reg [2:0] ddsWordNumRegSyncB;
+
 reg [2:0] ddsSyncCnt;
 
+/* WordNumVal Synchronization */
+wire ddsWordNumValSyncRdDomain;
+reg plsToggleWordNumVal;
+reg plsToggleWordNumValSyncA;
+reg plsToggleWordNumValSyncB;
+
+
 reg plsToggle;
 reg plsToggleSyncA;
 reg plsToggleSyncB;
@@ -88,9 +101,34 @@ assign byteParityBits[6] = ^dataFromDdsFifo[55:48];
 assign byteParityBits[7] = ^dataFromDdsFifo[63:56];
 assign byteParityBits[8] = ^dataFromDdsFifo[71:64];
 assign byteParityBits[9] = ^dataFromDdsFifo[79:72];
+
+/* ddsWordNumVal Synchronization */
+assign ddsWordNumValSyncRdDomain = plsToggleWordNumValSyncB^plsToggleWordNumValSyncA;
 //==========================================================================//
 //									CODING									//
 //==========================================================================//
+always @(posedge WrClk_i) begin 
+	if (Rst_i) begin 
+		plsToggleWordNumVal <= 1'b0;
+	end
+	else if (DdsWordNumVal_i) begin 
+		plsToggleWordNumVal <= ~plsToggleWordNumVal;
+	end
+	else begin 
+		plsToggleWordNumVal <= plsToggleWordNumVal;
+	end
+end
+always @(posedge RdClk_i) begin 
+	if (Rst_i) begin 
+		plsToggleWordNumValSyncA <= 1'b0;
+		plsToggleWordNumValSyncB <= 1'b0;
+	end
+	else begin 
+		plsToggleWordNumValSyncA <= plsToggleWordNumVal;
+		plsToggleWordNumValSyncB <= plsToggleWordNumValSyncA;
+	end
+end
+
 /* Check parity bits */
 always @(posedge RdClk_i) begin 
 	if (Rst_i) begin 
@@ -114,12 +152,26 @@ end
 
 always @(posedge RdClk_i) begin 
 	if (Rst_i) begin 
-		ddsDirectFlagR <= 1'b0;
+		ddsDirectFlagSyncA <= 1'b0;
+		ddsDirectFlagSyncB <= 1'b0;
+		ddsDirectFlagSyncC <= 1'b0;
 	end
 	else begin 
-		ddsDirectFlagR <= DdsDirectFlag_i;
+		ddsDirectFlagSyncA <= DdsDirectFlag_i;
+		ddsDirectFlagSyncB <= ddsDirectFlagSyncA;
+		ddsDirectFlagSyncC <= ddsDirectFlagSyncB;
 	end
 end
+	edgeDetectingSynchronizer#
+	( 
+		.Length(2),
+		.EdgeType("rising")
+	) edgeDetectingSynchronizer (		
+		.Rst_i(1'b0),	
+		.Clk_i(Clk_i),
+		.D_i(),
+		.D_o(dataVal)
+	);
 
 always @(posedge RdClk_i) begin 
 	ssReg <= Ss_o;
@@ -173,12 +225,30 @@ always @(posedge WrClk_i) begin
 	end
 end
 
+// always @(posedge RdClk_i) begin 
+// 	if (Rst_i) begin 
+// 		ddsWordNumRegRdDomain <= 3'h0;
+// 	end
+// 	else begin 
+// 		if (ddsWordNumValSyncRdDomain) begin 
+// 			ddsWordNumRegRdDomain <= DdsWordNum_i>>2;
+// 		end
+// 		else begin 
+// 			if ((ssReg && !Ss_o) && (ddsWordNumRegRdDomain > 0)) begin 
+// 				ddsWordNumRegRdDomain <= ddsWordNumRegRdDomain-1;
+// 			end
+// 		end
+// 	end
+// end
+
 always @(posedge RdClk_i) begin 
 	if (Rst_i) begin 
-		ddsWordNumRegSync <= 3'h0;
+		ddsWordNumRegSyncA <= 3'h0;
+		ddsWordNumRegSyncB <= 3'h0;
 	end
 	else begin 
-		ddsWordNumRegSync <= ddsWordNumReg;
+		ddsWordNumRegSyncA <= ddsWordNumReg;
+		ddsWordNumRegSyncB <= ddsWordNumRegSyncA;
 	end
 end
 
@@ -187,14 +257,14 @@ always @(posedge RdClk_i) begin
 		DdsSyncFpga_o <= 1'b0;
 	end
 	else begin
-		if (ddsDirectFlagR && !DdsDirectFlag_i) begin 
+		if (ddsDirectFlagSyncC && !ddsDirectFlagSyncB) begin 
 				DdsSyncFpga_o <= 1'b1;
 		end 
-		else if ((!Ss_o && ssReg) && (ddsWordNumRegSync != 0)) begin 
+		else if ((!Ss_o && ssReg) && (ddsWordNumRegSyncB != 0)) begin 
 			DdsSyncFpga_o <= 1'b0;
 		end
 		else begin 
-			if (ddsWordNumRegSync == 3'h1 && (Ss_o && !ssReg)) begin 
+			if (ddsWordNumRegSyncB == 3'h1 && (Ss_o && !ssReg)) begin 
 				DdsSyncFpga_o <= 1'b1;
 			end
 			else begin 

src/src/WrapFifoChain/LmxWrapper.v

@@ -59,7 +59,10 @@ reg plsToggleSyncB;
 
 reg ssR;
 reg ssReg;
-reg ssRegDds;
+// reg ssRegDds;
+reg ssDdsSyncA;
+reg ssDdsSyncB;
+reg ssDdsSyncC;
 reg [3:0] lmxWordNumReg; 
 reg [3:0] lmxWordNumRegR;
 //==========================================================================//
@@ -112,10 +115,14 @@ end
 
 always @(posedge RdClk_i) begin 
 	if (Rst_i) begin 
-		ssRegDds <= 1'b0;
+		ssDdsSyncA <= 1'b0;
+		ssDdsSyncB <= 1'b0;
+		ssDdsSyncC <= 1'b0;
 	end
 	else begin 
-		ssRegDds <= DdsCs_i;
+		ssDdsSyncA <= DdsCs_i;
+		ssDdsSyncB <= ssDdsSyncA;
+		ssDdsSyncC <= ssDdsSyncB;
 	end
 end
 
@@ -144,7 +151,7 @@ always @(posedge RdClk_i) begin
 			if ((lmxWordNumReg == 0) && (DdsWordNumReg_i == 0)) begin
 				PllVtuneCtrl_o <= 1'b1;
 			end
-			else if ((!DdsCs_i && ssRegDds) && (DdsWordNumReg_i != 0)) begin 
+			else if ((!ssDdsSyncC && ssDdsSyncB ) && (DdsWordNumReg_i != 0)) begin 
 				PllVtuneCtrl_o <= 1'b0;
 			end
 			else if ((!Ss_o && ssReg) && (lmxWordNumReg != 0) ) begin