Обновлён скрипт. Изменения в InterfaceArbiter.

script/recreate.tcl

@@ -1,17 +1,44 @@
 set DSN_ROOT [file normalize [file join [file dirname [info script]] "."]]
 create_project -name SB_TMSG44V1_FPGA -dir $::DSN_ROOT/SB_TMSG44V1_FPGA_PROJ -pn GW1N-LV9PG256C6/I5 -device_version C -force 
 
-
-#add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/Top/RFTop.v"
-#add_file -type cst "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/constr/RF_FPGA.cst"
-#add_file -type sdc "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/constr/RF_FPGA.sdc"
-
+add_file -type cst "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/constr/SbTmsg.cst"
+add_file -type sdc "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/constr/SbTmsg.sdc"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/Top/TopSbTmsg.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinClkDiv3dot5/GowinClkDiv3dot5.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinClkDiv4/GowinClkDiv4.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinClkDiv5/GowinClkDiv5.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinClkDiv8/GowinClkDiv8.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinPLLFirst/GowinPLLFirst.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinPLLSecond/GowinPLLSecond.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/ClkGen/ClkGen.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/FifoCtrl/FifoCtrl.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/Gpio1Ctrl/Gpio1Ctrl.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/Gpio2Read/Gpio2Read.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/InterfaceArbiter/InterfaceArbiter.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/PacketAnalyzer1Mosi/PacketAnalyzer1Mosi.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/PacketAnalyzer4Mosi/PacketAnalyzer4Mosi.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/SpiM/SpiM.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/SpiReadback/SpiReadback.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/TempRead/TempI2cMaster.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/TempRead/TempRead.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/Fifo16x3/Fifo16x3.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoDDS/FifoDDS.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoLMX/FifoLMX.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoMax2870/FifoMax2870.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoShiftReg/FifoShiftReg.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/AttenuatorWrapper.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/DDSWrapper.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/LmxWrapper.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/Max2870Wrapper.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/ShifRegWrapper.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/DacWrapper.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/PotWrapper.v"
 
 
 
 set_option -synthesis_tool gowinsynthesis
 set_option -output_base_name SB_TMSG44V1_FPGA
-set_option -top_module TopSbtmsg
+set_option -top_module TopSbTmsg
 set_option -gen_verilog_sim_netlist 1
 
 set_option -print_all_synthesis_warning 0
@@ -99,4 +126,4 @@ set_option -error_detection_correction false
 set_option -stop_seu_handler false
 set_option -error_injection false
 set_option -ext_cclk false
-set_option -ext_cclk_div 
+set_option -ext_cclk_div

src/constr/RF_FPGA.cst

@@ -1,133 +0,0 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
-//All rights reserved. 
-//File Title: Physical Constraints file
-//Tool Version: V1.9.9.01 (64-bit)
-//Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-9
-//Created Time: Fri 04 12 11:25:42 2024
-
-IO_LOC "GPIO_o[21]" E1;
-IO_PORT "GPIO_o[21]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[20]" C16;
-IO_PORT "GPIO_o[20]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[19]" D15;
-IO_PORT "GPIO_o[19]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[18]" P1;
-IO_PORT "GPIO_o[18]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[17]" D1;
-IO_PORT "GPIO_o[17]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[16]" R1;
-IO_PORT "GPIO_o[16]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[15]" L1;
-IO_PORT "GPIO_o[15]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[14]" K2;
-IO_PORT "GPIO_o[14]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[13]" K1;
-IO_PORT "GPIO_o[13]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[12]" L2;
-IO_PORT "GPIO_o[12]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[11]" A2;
-IO_PORT "GPIO_o[11]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[10]" A11;
-IO_PORT "GPIO_o[10]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[9]" A14;
-IO_PORT "GPIO_o[9]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[8]" A12;
-IO_PORT "GPIO_o[8]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[7]" A10;
-IO_PORT "GPIO_o[7]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[6]" A13;
-IO_PORT "GPIO_o[6]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[5]" R6;
-IO_PORT "GPIO_o[5]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[4]" T5;
-IO_PORT "GPIO_o[4]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[3]" T6;
-IO_PORT "GPIO_o[3]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[2]" J16;
-IO_PORT "GPIO_o[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[1]" H16;
-IO_PORT "GPIO_o[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "GPIO_o[0]" G16;
-IO_PORT "GPIO_o[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_PORT "RstInit_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_PORT "Locked_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_PORT "Mosi0_o[7]" IO_TYPE=LVCMOS33;
-IO_LOC "Mosi0_o[6]" C1;
-IO_PORT "Mosi0_o[6]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Mosi0_o[5]" F16;
-IO_PORT "Mosi0_o[5]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Mosi0_o[4]" C7;
-IO_PORT "Mosi0_o[4]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Mosi0_o[3]" B3;
-IO_PORT "Mosi0_o[3]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Mosi0_o[2]" B5;
-IO_PORT "Mosi0_o[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Mosi0_o[1]" R3;
-IO_PORT "Mosi0_o[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Mosi0_o[0]" G1;
-IO_PORT "Mosi0_o[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_PORT "Sck_o[7]" IO_TYPE=LVCMOS33;
-IO_LOC "Sck_o[6]" C2;
-IO_PORT "Sck_o[6]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Sck_o[5]" E16;
-IO_PORT "Sck_o[5]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Sck_o[4]" B7;
-IO_PORT "Sck_o[4]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Sck_o[3]" A3;
-IO_PORT "Sck_o[3]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Sck_o[2]" A5;
-IO_PORT "Sck_o[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Sck_o[1]" T2;
-IO_PORT "Sck_o[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Sck_o[0]" G2;
-IO_PORT "Sck_o[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_PORT "Ss_o[7]" IO_TYPE=LVCMOS33;
-IO_LOC "Ss_o[6]" D2;
-IO_PORT "Ss_o[6]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Ss_o[5]" F15;
-IO_PORT "Ss_o[5]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Ss_o[4]" C8;
-IO_PORT "Ss_o[4]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Ss_o[3]" B4;
-IO_PORT "Ss_o[3]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Ss_o[2]" A4;
-IO_PORT "Ss_o[2]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Ss_o[1]" R4;
-IO_PORT "Ss_o[1]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Ss_o[0]" F1;
-IO_PORT "Ss_o[0]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_PORT "Clk50_o" IO_TYPE=LVCMOS33;
-IO_PORT "Clk100_o" IO_TYPE=LVCMOS33;
-IO_PORT "Clk600_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_PORT "Clk5_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_PORT "Clk20_o" IO_TYPE=LVCMOS33;
-IO_PORT "Clk30_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_PORT "Clk40_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_PORT "Clk75_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "I2CSck_o" K16;
-IO_PORT "I2CSck_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "I2CSda_io" L16;
-IO_PORT "I2CSda_io" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "Mosi1_io" T12;
-IO_PORT "Mosi1_io" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
-IO_LOC "MisoMax2870_i" B1;
-IO_PORT "MisoMax2870_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
-IO_LOC "Miso2_i" T3;
-IO_PORT "Miso2_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
-IO_LOC "Miso1_i" F2;
-IO_PORT "Miso1_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
-IO_LOC "Ss_i" T9;
-IO_PORT "Ss_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
-IO_LOC "Sck_i" T13;
-IO_PORT "Sck_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
-IO_LOC "Mosi3_i" T15;
-IO_PORT "Mosi3_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
-IO_LOC "Mosi2_i" T14;
-IO_PORT "Mosi2_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
-IO_LOC "Mosi0_i" R12;
-IO_PORT "Mosi0_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
-IO_LOC "Rst_i" R9;
-IO_PORT "Rst_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
-IO_LOC "Clk_i" H11;
-IO_PORT "Clk_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;

src/constr/RF_FPGA.sdc

@@ -1,21 +0,0 @@
-//Copyright (C)2014-2024 GOWIN Semiconductor Corporation.
-//All rights reserved.
-//File Title: Timing Constraints file
-//Tool Version: V1.9.9.01 (64-bit) 
-//Created Time: 2024-03-18 14:44:39
-create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
-create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
-create_generated_clock -name clk30 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 30 [get_ports {Clk30_o}]
-create_generated_clock -name clk40 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 40 [get_ports {Clk40_o}]
-create_generated_clock -name clk50 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 50 [get_ports {Clk50_o}]
-create_generated_clock -name clk5 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 5 [get_ports {Clk5_o}]
-create_generated_clock -name clk360 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 360 [get_ports {Clk600_o}]
-create_generated_clock -name clk100 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 100 [get_ports {Clk100_o}]
-create_generated_clock -name clk20 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 20 [get_ports {Clk20_o}]
-create_generated_clock -name clk75 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 72 [get_ports {Clk75_o}]
-set_clock_groups -asynchronous -group [get_clocks {Clk_i Sck_i}]
-report_timing -setup -from_clock [get_clocks {clk100}] -max_paths 100 -max_common_paths 1
-report_timing -setup -from_clock [get_clocks {clk360}] -max_paths 100 -max_common_paths 1
-report_timing -setup -from_clock [get_clocks {clk75}] -max_paths 100 -max_common_paths 1
-report_timing -setup -from_clock [get_clocks {clk50}] -max_paths 100 -max_common_paths 1
-report_timing -setup -from [get_ports {Rst_i}]

src/constr/SbTmsg.cst

@@ -0,0 +1 @@
+#

src/constr/SbTmsg.sdc

@@ -0,0 +1 @@
+#

src/src/InterfaceArbiter/InterfaceArbiter.v

@@ -90,7 +90,7 @@ module InterfaceArbiter
 	
 //================================================================================
 //  CODING
-	always @(posedge Sck_i or posedge Rst_i) begin
+	always @(posedge Sck_i or negedge Rst_i) begin
 		if (!Rst_i) begin
 			if (!Ss_i) begin
 				captRegSspi <= {captRegSspi[OUTWORDWIDTH-2:0], Mosi0_i};
@@ -110,7 +110,7 @@ module InterfaceArbiter
 		end
 	end
 	
-	always @(posedge Sck_i or posedge Rst_i) begin
+	always @(posedge Sck_i or negedge Rst_i) begin
 		if (!Rst_i) begin
 			if (!Ss_i) begin
 				if (ssCnt == ssCntRstThresh) begin
@@ -124,7 +124,7 @@ module InterfaceArbiter
 		end
 	end
 	
-	always @(posedge Clk_i or posedge Rst_i) begin
+	always @(posedge Clk_i) begin
 		if (!Rst_i) begin
 			if (currState == DATARX) begin
 				if (ssPos) begin
@@ -146,7 +146,7 @@ module InterfaceArbiter
 		end
 	end
 	
-	always @(posedge Sck_i or posedge Rst_i) begin
+	always @(posedge Sck_i or negedge Rst_i) begin
 		if (!Rst_i) begin
 			if (currState == IDLE) begin
 				if (ssCnt == 1) begin
@@ -162,7 +162,7 @@ module InterfaceArbiter
 		end
 	end 
 	
-	always @(posedge Clk_i or posedge Rst_i) begin
+	always @(posedge Clk_i) begin
 		if (!Rst_i) begin
 			if (currState == IDLE) begin
 				if (!spiMode) begin
@@ -176,7 +176,7 @@ module InterfaceArbiter
 		end
 	end 
 	
-	always @(posedge Clk_i or posedge Rst_i) begin
+	always @(posedge Clk_i) begin
 		if (!Rst_i) begin
 			ssReg <= Ss_i;
 			ssRegR <= ssReg;
@@ -190,7 +190,7 @@ module InterfaceArbiter
 		end
 	end 
 	
-	always @(posedge Clk_i or posedge Rst_i) begin
+	always @(posedge Clk_i) begin
 		if (!Rst_i) begin
 			if (ssPos) begin
 				dataRegSSpi <= captRegSspi;
@@ -206,7 +206,7 @@ module InterfaceArbiter
 		end
 	end
 
-	always @(posedge Clk_i or posedge Rst_i) begin
+	always @(posedge Clk_i) begin
 		if (Rst_i) begin
 			currState <= IDLE;
 		end else begin