Merge branch 'Mikhail/feature_MuxSpi' of zaytsev.mikhail/SB_TMSG44V1_FPGA into dev

src/src/Top/TopSbTmsg.v

@@ -75,7 +75,37 @@ module TopSbTmsg
 	output RefOffsetCtrlFpga_o,
 	output GpioAdRfV1_o,
 	output GpioAdRfV2_o,
-	output DdsSaw1Fpga_o
+	output DdsSaw1Fpga_o,
+
+	//Output SPI devices
+	output reg CsLmx94_o,
+	output reg ClkLmx94_o,
+	output reg DataLmx94_o,
+
+	output reg CsAd9912Fpga_o,
+	output reg ClkAd9912Fpga_o,
+	output reg MosiAd9912Fpga_o,
+
+	output reg CsPot_o,
+	output reg ClkPot_o,
+	output reg MosiPot_o,
+
+	output reg AmDac2Cs_o,
+	output reg AmDac2Clk_o,
+	output reg AmDac2_mosi_o,
+
+	output reg FpgaCsAtt_o,
+	output reg FpgaClkAtt_o,
+	output reg FpgaMosiAtt_o,
+
+	output reg CsRegRf2_o,
+	output reg ClkRegRf2_o,
+	output reg DataRegRf2_o,
+
+	output reg CsMax2870MixRf2_o,
+	output reg ClkMax2870MixRf2_o,
+	output reg DataMax2870MixRf2_o
+
 );
 
 //================================================================================
@@ -124,10 +154,39 @@ module TopSbTmsg
 	wire misoGpio2;
 	wire anyFlag;
 
-	reg misoReg;	
+	//Output SpiM wires 
+	wire lmxCsSpiM;
+	wire lmxClkSpiM;
+	wire lmxMosiSpiM;
+
+	wire ddsCsSpiM;
+	wire ddsClkSpiM;
+	wire ddsMosiSpiM;
+
+	wire potCsSpiM;
+	wire potClkSpiM;
+	wire potMosiSpiM;
+
+	wire dacCsSpiM;
+	wire dacClkSpiM;
+	wire dacMosiSpiM;
+
+	wire attCsSpiM;
+	wire attClkSpiM;
+	wire attMosiSpiM;
+
+	wire shRegCsSpiM;
+	wire shRegClkSpiM;
+	wire shRegMosiSpiM;
+
+	wire maxCsSpiM;
+	wire maxClkSpiM;
+	wire maxMosiSpiM;
+
+	reg misoReg;
 
- //================================================================================
-    //  ASSIGNMENTS
+//================================================================================
+//  ASSIGNMENTS
 //================================================================================
 assign DdsSaw1Fpga_o 		= gpio1CtrlData[21];
 assign GpioAdRfV2_o 		= gpio1CtrlData[20];
@@ -186,6 +245,82 @@ always @(*) begin
 	end
 end
 
+//====================================
+// MUX SpiM devices
+//====================================
+always @(*) begin
+	if (flagDirectLmx) begin	//LMX
+		CsLmx94_o 	= Ss_i;
+		ClkLmx94_o 	= Sck_i;
+		DataLmx94_o = Mosi0_i;
+	end
+	else begin
+		CsLmx94_o 	= lmxCsSpiM;
+		ClkLmx94_o 	= lmxClkSpiM;
+		DataLmx94_o = lmxMosiSpiM;
+	end
+	if (flagDirectDds) begin	//DDS
+		CsAd9912Fpga_o 		= Ss_i;
+		ClkAd9912Fpga_o 	= Sck_i;
+		MosiAd9912Fpga_o 	= Mosi0_i;
+	end
+	else begin
+		CsAd9912Fpga_o 		= ddsCsSpiM;
+		ClkAd9912Fpga_o 	= ddsClkSpiM;
+		MosiAd9912Fpga_o 	= ddsMosiSpiM;
+	end
+	if (flagDirectPot) begin	//POT
+		CsPot_o		= Ss_i;
+		ClkPot_o	= Sck_i;
+		MosiPot_o	= Mosi0_i;
+	end
+	else begin
+		CsPot_o		= potCsSpiM;
+		ClkPot_o	= potClkSpiM;
+		MosiPot_o	= potMosiSpiM;
+	end
+	if (flagDirectDac) begin	//DAC
+		AmDac2Cs_o 		= Ss_i;
+		AmDac2Clk_o 	= Sck_i;
+		AmDac2_mosi_o 	= Mosi0_i;
+	end
+	else begin
+		AmDac2Cs_o 		= dacCsSpiM;
+		AmDac2Clk_o 	= dacClkSpiM;
+		AmDac2_mosi_o 	= dacMosiSpiM;
+	end
+	if (flagDirectAtt) begin	//ATT
+		FpgaCsAtt_o		= Ss_i;
+		FpgaClkAtt_o	= Sck_i;
+		FpgaMosiAtt_o	= Mosi0_i;
+	end
+	else begin
+		FpgaCsAtt_o		= attCsSpiM;
+		FpgaClkAtt_o	= attClkSpiM;
+		FpgaMosiAtt_o	= attMosiSpiM;
+	end
+	if (flagDirectShReg) begin	//ShReg
+		CsRegRf2_o 		= Ss_i;
+		ClkRegRf2_o 	= Sck_i;
+		DataRegRf2_o 	= Mosi0_i;
+	end
+	else begin
+		CsRegRf2_o 		= shRegCsSpiM;
+		ClkRegRf2_o 	= shRegClkSpiM;
+		DataRegRf2_o 	= shRegMosiSpiM;
+	end
+	if (flagDirectMax) begin	//MAX
+		CsMax2870MixRf2_o	= Ss_i;
+		ClkMax2870MixRf2_o	= Sck_i;
+		DataMax2870MixRf2_o	= Mosi0_i;
+	end
+	else begin
+		CsMax2870MixRf2_o	= maxCsSpiM;
+		ClkMax2870MixRf2_o	= maxClkSpiM;
+		DataMax2870MixRf2_o	= maxMosiSpiM;
+	end
+end
+
 ClkGen ClkGen
 (
 	.Clk24Mhz_i			(Clk_i),
@@ -217,7 +352,6 @@ SpiSlaveArbiter
 	.Mosi2_i	(Mosi2_i),
 	.Mosi3_i	(Mosi3_i),
 	
-	
 	.DataVal_o	(spiDataVal),
 	.Data_o		(spiData)
 );
@@ -279,9 +413,9 @@ LmxWrapper #(
 	.Rst_i			(Rst_i),
 	.Data_i			(spiData),
 	.Val_i			(valLmxDataToFifo),
-	.Ss_o			(),
-	.Sck_o			(),
-	.Mosi_o			()
+	.Ss_o			(lmxCsSpiM),
+	.Sck_o			(lmxClkSpiM),
+	.Mosi_o			(lmxMosiSpiM)
 );
 
 DDSWrapper #(
@@ -295,9 +429,9 @@ DDSWrapper #(
 	.Rst_i			(Rst_i),
 	.Data_i			(spiData),
 	.Val_i			(valDdsDataToFifo),
-	.Ss_o			(),
-	.Sck_o			(),
-	.Mosi_o			()
+	.Ss_o			(ddsCsSpiM),
+	.Sck_o			(ddsClkSpiM),
+	.Mosi_o			(ddsMosiSpiM)
 );
 
 PotWrapper #(
@@ -311,9 +445,9 @@ PotWrapper #(
 	.Rst_i			(Rst_i),
 	.Data_i			(spiData),
 	.Val_i			(valPotDataToFifo),
-	.Ss_o			(),
-	.Sck_o			(),
-	.Mosi_o			()
+	.Ss_o			(potCsSpiM),
+	.Sck_o			(potClkSpiM),
+	.Mosi_o			(potMosiSpiM)
 );
 
 DacWrapper #(
@@ -327,9 +461,9 @@ DacWrapper #(
 	.Rst_i			(Rst_i),
 	.Data_i			(spiData),
 	.Val_i			(valDacDataToFifo),
-	.Ss_o			(),
-	.Sck_o			(),
-	.Mosi_o			()
+	.Ss_o			(dacCsSpiM),
+	.Sck_o			(dacClkSpiM),
+	.Mosi_o			(dacMosiSpiM)
 );
 
 AttenuatorWrapper #(
@@ -343,9 +477,9 @@ AttenuatorWrapper #(
 	.Rst_i			(Rst_i),
 	.Data_i			(spiData),
 	.Val_i			(valAttDataToFifo),
-	.Ss_o			(),
-	.Sck_o			(),
-	.Mosi_o			()
+	.Ss_o			(attCsSpiM),
+	.Sck_o			(attClkSpiM),
+	.Mosi_o			(attMosiSpiM)
 );
 
 ShiftRegWrapper #(
@@ -359,9 +493,9 @@ ShiftRegWrapper #(
 	.Rst_i			(Rst_i),
 	.Data_i			(spiData),
 	.Val_i			(valShRegDataToFifo),
-	.Ss_o			(),
-	.Sck_o			(),
-	.Mosi_o			()
+	.Ss_o			(shRegCsSpiM),
+	.Sck_o			(shRegClkSpiM),
+	.Mosi_o			(shRegMosiSpiM)
 );
 
 Max2870Wrapper #(
@@ -375,9 +509,9 @@ Max2870Wrapper #(
 	.Rst_i			(Rst_i),
 	.Data_i			(spiData),
 	.Val_i			(valMaxDataToFifo),
-	.Ss_o			(),
-	.Sck_o			(),
-	.Mosi_o			()
+	.Ss_o			(maxCsSpiM),
+	.Sck_o			(maxClkSpiM),
+	.Mosi_o			(maxMosiSpiM)
 );
 
 TempRead TempRead (