Исправлен модуль SpiReadback. Добавлена документация на SpiReadback. Изменены цвета на структурной схеме.

src/src/Gpio2Read/Gpio2Read.v

@@ -61,7 +61,7 @@ always @(posedge Clk_i) begin
 	end
 end
 
-SpiReadback SpiReadback_TempReg (
+SpiReadback SpiReadbackGpio2Read (
 	.ClkSpi_i		(ClkSpi_i),
 	.Rst_i			(Rst_i),
 	.RegData_i		( {22'b0, gpio2Reg} ),

src/src/SpiReadback/SpiReadback.v

@@ -1,3 +1,22 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		Zaytsev Mikhail
+// 
+// Create Date:		26/04/2024 
+// Design Name: 
+// Module Name:		SpiReadback 
+// Project Name:	SB_TMSG44V1_FPGA
+// Target Devices:	Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:		The module advances data sequentially to the MisoGpio2_o line 
+//					when the FlagDirect_i signal is present.
+//
+// Dependencies:	
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
 module SpiReadback (
 
 	input ClkSpi_i,
@@ -14,7 +33,6 @@ module SpiReadback (
 // Registers
 //==========================================
 reg [23:0] shReg;
-reg	flagSpiSync;
 
 //==========================================
 // Wires
@@ -28,14 +46,6 @@ assign Miso_o = shReg[23];
 //////////////////////////////////////////////////////////////////////////////////
 // 									Coding										//
 //////////////////////////////////////////////////////////////////////////////////
-always	@(negedge	ClkSpi_i)	begin
-	if	(!Rst_i)	begin
-		flagSpiSync		<=	FlagDirect_i;
-	end	else	begin
-		flagSpiSync		<=	0;
-	end
-end
-
 always @(negedge ClkSpi_i) begin
 	if (Rst_i) begin
 		shReg <= 0;
@@ -43,7 +53,7 @@ always @(negedge ClkSpi_i) begin
 	else if (FlagDirect_i == 0) begin
 		shReg <= RegData_i;
 	end
-	else if (flagSpiSync == 1) begin
+	else if (FlagDirect_i == 1) begin
 		shReg <= shReg << 1;
 	end
 end

src/src/TempRead/TempRead.v

@@ -99,7 +99,7 @@ always @(posedge Clk24Mhz_i) begin
 	end
 end
 
-SpiReadback SpiReadback_TempReg (
+SpiReadback SpiReadbackTempRead (
 	.ClkSpi_i		(ClkSpi_i),
 	.Rst_i			(Rst_i),
 	.RegData_i		( {8'h00, tempDataReadback} ),