Исправлена ошибка в SpiM. Добавлен модуль FifoCtrl.

src/src/FifoCtrl/FifoCtrl.v

@@ -0,0 +1,124 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     FifoCtrl
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:     This module is a controller for the FIFOs. It controls the read and write pointers of the FIFOs.
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module FifoCtrl #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 1,
+    parameter OUT_WIDTH = 24
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [23:0] Data_i,
+    input Val_i,
+    input BusySpiM_i,
+    input FifoFull_i,
+    input FifoEmpty_i,
+
+    output [OUT_WIDTH-1:0] Data_o,
+    output reg ReadEn_o,
+    output reg  WriteEn_o
+
+);
+//================================================================================
+//	LOCAL PARAMETERS
+//================================================================================
+localparam DATA_WIDTH = WR_NUM*IN_WIDTH;
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+reg [DATA_WIDTH-1:0] dataReg;
+reg [1:0]  wrCnt;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign Data_o = dataReg[OUT_WIDTH-1:0];
+
+//================================================================================
+//	CODING
+//================================================================================
+always @(posedge WrClk_i) begin 
+    if (Rst_i) begin 
+        wrCnt <= 0;
+    end
+    else begin 
+        if (Val_i) begin 
+            wrCnt <= wrCnt + 1;
+        end
+        else if (wrCnt == WR_NUM) begin 
+            wrCnt <= 0;
+        end
+    end
+end
+
+always @(posedge WrClk_i) begin 
+    if (Rst_i) begin 
+        dataReg <= 0;
+    end
+    else begin 
+        case (wrCnt)
+        0 : begin 
+            if (Val_i) begin 
+                dataReg[IN_WIDTH-1:0] <= Data_i;
+            end
+        end
+        1 : begin 
+            if (Val_i) begin 
+                dataReg[(2*IN_WIDTH)-1:IN_WIDTH] <= Data_i;
+            end
+        end
+        2 : begin 
+            if (Val_i) begin 
+                dataReg[(3*IN_WIDTH)-1:(2*IN_WIDTH)] <= Data_i;
+            end
+        end
+        endcase
+    end
+end
+
+always @(posedge WrClk_i) begin
+    if (Rst_i) begin 
+        WriteEn_o <= 1'b0;
+    end
+    else begin  
+        if (Val_i && wrCnt == WR_NUM-1) begin
+            WriteEn_o <= 1'b1;
+        end
+        else begin 
+            WriteEn_o <= 1'b0;
+        end
+    end
+end
+
+always @(posedge RdClk_i) begin
+    if (Rst_i) begin 
+        ReadEn_o <= 1'b0;
+    end
+    else begin  
+        if (!FifoEmpty_i && !BusySpiM_i) begin 
+            ReadEn_o <= 1'b1;
+        end
+        else begin 
+            ReadEn_o <= 1'b0;
+        end
+    end
+end
+
+endmodule

src/src/FifoCtrl/FifoCtrl_tb.sv

@@ -0,0 +1,202 @@
+`timescale 1ns/1ps
+module FifoCtrl_tb;
+logic WrClk_i;
+logic RdClkDDS_i;
+logic RdClkLMX_i;
+logic Rst_i;
+logic [23:0] data;
+logic BusySpiLMX;
+logic BusySpiDDS;
+logic valFromSPI64;
+logic valFromSPI24;
+
+logic wrEnDDS;
+logic wrEnLMX;
+
+logic rdEnDDS;
+logic rdEnLMX;
+
+logic fullFlagLMX;
+logic emptyFlagLMX;
+
+logic fullFlagDDS;
+logic emptyFlagDDS;
+
+logic [23:0] dataToFifo24;
+logic [63:0] dataToFifo64;
+logic [23:0] dataFromFifo24;
+logic [63:0] dataFromFifo64;
+
+
+
+logic [6:0] OUT_WIDTH;
+logic [1:0] WR_NUM;
+
+
+//***********************************************
+//	           LOCALPARAMS
+//***********************************************
+localparam FIFTY_MHZ = 20;
+localparam SIXTY_MHZ = 16;
+
+//***********************************************
+//	           CLOCK GENERATION
+//***********************************************
+always begin
+    #5 WrClk_i = ~WrClk_i;
+    #(FIFTY_MHZ/2) RdClkDDS_i = ~RdClkDDS_i;
+    #(SIXTY_MHZ/2) RdClkLMX_i = ~RdClkLMX_i;
+end
+
+//***********************************************
+//	           DUT INSTANTIATION
+//***********************************************
+
+FifoCtrl#(
+    .IN_WIDTH(24),
+    .WR_NUM(3),
+    .OUT_WIDTH(64)
+) FifoCtrlDDS_inst (
+    .WrClk_i(WrClk_i),
+    .RdClk_i(RdClkDDS_i),
+    .Rst_i(Rst_i),
+    .Data_i(data),
+    .Val_i(valFromSPI64),
+    .FifoFull_i(fullFlagDDS),
+    .FifoEmpty_i(emptyFlagDDS),
+    .BusySpiM_i(BusySpiDDS),
+    .Data_o(dataToFifo64),
+    .ReadEn_o(rdEnDDS),
+    .WriteEn_o(wrEnDDS)
+);
+
+FifoCtrl #(
+    .IN_WIDTH(24),
+    .WR_NUM(1),
+    .OUT_WIDTH(24)
+) FifoCtrlLMX_inst (
+    .WrClk_i(WrClk_i),
+    .RdClk_i(RdClkLMX_i),
+    .Rst_i(Rst_i),
+    .Data_i(data),
+    .Val_i(valFromSPI24),
+    .FifoFull_i(fullFlagLMX),
+    .FifoEmpty_i(emptyFlagLMX),
+    .BusySpiM_i(BusySpiLMX),
+    .Data_o(dataToFifo24),
+    .ReadEn_o(rdEnLMX),
+    .WriteEn_o(wrEnLMX)
+);
+
+FifoLMX FifoLMX_inst (
+    .Data(dataToFifo24),
+    .WrClk(WrClk_i),
+    .RdClk(RdClkLMX_i),
+    .WrEn(wrEnLMX),
+    .RdEn(rdEnLMX),
+    .Q(dataFromFifo24),
+    .Empty(emptyFlagLMX),
+    .Full(fullFlagLMX)
+);
+
+FifoDDS FifoDDS_inst (
+    .Data(dataToFifo64),
+    .WrClk(WrClk_i),
+    .RdClk(RdClkDDS_i),
+    .WrEn(wrEnDDS),
+    .RdEn(rdEnDDS),
+    .Q(dataFromFifo64),
+    .Empty(emptyFlagDDS),
+    .Full(fullFlagDDS)
+);
+
+SpiM #(
+    .DATA_WIDTH(24)
+)SpiMLMX_inst(
+    .Clk_i(RdClkLMX_i),
+    .Rst_i(Rst_i),
+    .Val_i(rdEnLMX),
+    .SpiData_i(dataFromFifo24),
+    .Busy_o(BusySpiLMX)
+);
+
+SpiM #(
+    .DATA_WIDTH(64)
+)SpiMDDS_inst(
+    .Clk_i(RdClkDDS_i),
+    .Rst_i(Rst_i),
+    .Val_i(rdEnDDS),
+    .SpiData_i(dataFromFifo64),
+    .Busy_o(BusySpiDDS)
+);
+
+task drive_fifo64();
+    valFromSPI64 = 1'b0;
+    #300;
+    wait(!BusySpiDDS)
+    @ (posedge WrClk_i)
+    valFromSPI64 = 1'b1;
+    data = 24'h123456;
+    #10;
+    @(posedge WrClk_i)
+    valFromSPI64 = 1'b0;
+    #300;
+    wait(!BusySpiDDS)
+    @ (posedge WrClk_i)
+    valFromSPI64 = 1'b1;
+    data = 24'habcdef;
+    #10;
+    @ (posedge WrClk_i)
+    valFromSPI64 = 1'b0;
+    #300;
+    wait(!BusySpiDDS)
+    @ (posedge WrClk_i)
+    valFromSPI64 = 1'b1;
+    data = 24'h123456;
+    #10;
+    @(posedge WrClk_i)
+    valFromSPI64 = 1'b0;
+endtask
+
+task drive_fifo24();
+    Rst_i = 1'b1;
+    valFromSPI24 = 1'b0;
+    data = 24'h0;
+    #200;
+    Rst_i = 1'b0;
+    #300;
+    wait(!BusySpiLMX)
+    @ (posedge WrClk_i)
+    valFromSPI24 = 1'b1;
+    data = 24'h123456;
+    #10;
+    @(posedge WrClk_i)
+    valFromSPI24 = 1'b0;
+    #300;
+    wait(!BusySpiLMX)
+    @ (posedge WrClk_i)
+    valFromSPI24 = 1'b1;
+    data = 24'habcdef;
+    #10;
+    @ (posedge WrClk_i)
+    valFromSPI24 = 1'b0;
+    #300;
+    wait(!BusySpiLMX)
+    @ (posedge WrClk_i)
+    valFromSPI24 = 1'b1;
+    data = 24'h123456;
+    #10;
+    @(posedge WrClk_i)
+    valFromSPI24 = 1'b0;
+endtask
+
+
+initial begin 
+    WrClk_i = 1'b1;
+    RdClkDDS_i = 1'b1;
+    RdClkLMX_i = 1'b1;
+    drive_fifo24();
+    drive_fifo64();
+end
+
+endmodule

src/src/SPIm/SpiM.v

@@ -107,7 +107,7 @@ always @(negedge Clk_i) begin
         ssReg <= 1'b1;
     end
     else begin 
-        if (ssCnt < DATA_WIDTH) begin 
+        if ((ssCnt < DATA_WIDTH && ssCnt != 0) || Val_i) begin 
             ssReg <= 1'b0;
         end
         else begin