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Поднял скорости отправки SPI

Anatoliy Chigirinskiy 1 gadu atpakaļ
vecāks
revīzija
5c99996915
3 mainītis faili ar 17 papildinājumiem un 8 dzēšanām
  1. 1 1
      src/constr/SbTmsg.sdc
  2. 6 6
      src/src/Top/TopSbTmsg.v
  3. 10 1
      src/src/Top/TopSbTmsgTb.sv

+ 1 - 1
src/constr/SbTmsg.sdc

@@ -7,7 +7,7 @@ create_clock -name clk5 -period 200 -waveform {0 100} [get_nets {clk5}]
 create_clock -name clk60 -period 16.667 -waveform {0 8.334} [get_nets {clk60}]
 create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
 create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
-create_clock -name clk100 -period 10 -waveform {0 5} [get_nets {gclk100}]
+//create_clock -name clk100 -period 10 -waveform {0 5} [get_nets {gclk100}]
 set_clock_groups -asynchronous -group [get_clocks {Clk_i}] -group [get_clocks {Sck_i}]
 set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Clk_i}] 
 set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Sck_i}] 

+ 6 - 6
src/src/Top/TopSbTmsg.v

@@ -445,7 +445,7 @@ LmxWrapper #(
 	.DATA_WIDTH			(24)
 ) LmxWrapper(
 	.WrClk_i			(clk60),
-	.RdClk_i			(clk5),
+	.RdClk_i			(clk60),
 	.Rst_i				(initRst),
 	.Data_i				(spiData),
 	.Val_i				(valLmxDataToFifo),
@@ -465,7 +465,7 @@ DDSWrapper #(
 	.DATA_WIDTH			(80)
 ) DDSWrapper(
 	.WrClk_i			(clk60),
-	.RdClk_i			(clk5),
+	.RdClk_i			(clk50),
 	.Rst_i				(initRst),
 	.DdsWordNum_i		(ddsWordNum),
 	.DdsWordNumVal_i	(valWordNum),
@@ -501,7 +501,7 @@ DacWrapper #(
 	.DATA_WIDTH		(16)
 ) DacWrapper(
 	.WrClk_i		(clk60),
-	.RdClk_i		(clk5),
+	.RdClk_i		(clk50),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
 	.Val_i			(valDacDataToFifo),
@@ -517,7 +517,7 @@ AttenuatorWrapper #(
 	.DATA_WIDTH		(16)
 ) AttenuatorWrapper(
 	.WrClk_i		(clk60),
-	.RdClk_i		(clk5),
+	.RdClk_i		(clk50),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
 	.Val_i			(valAttDataToFifo),
@@ -533,7 +533,7 @@ ShiftRegWrapper #(
 	.DATA_WIDTH		(8)
 ) ShiftRegWrapper(
 	.WrClk_i		(clk60),
-	.RdClk_i		(clk5),
+	.RdClk_i		(clk26dot25),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
 	.Val_i			(valShRegDataToFifo),
@@ -549,7 +549,7 @@ Max2870Wrapper #(
 	.DATA_WIDTH		(32)
 ) Max2870Wrapper(
 	.WrClk_i		(clk60),
-	.RdClk_i		(clk5),
+	.RdClk_i		(clk20),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
 	.Val_i			(valMaxDataToFifo),

+ 10 - 1
src/src/Top/TopSbTmsgTb.sv

@@ -6,6 +6,9 @@ module TopSbTmsgTb(inout Mosi1_io);
     // Inputs
     logic Clk_i;
     logic Clk100;
+    logic Clk200;
+    logic Clk125;
+    logic Clk60;
     logic Clk20;
     logic Clk80;
     logic Clk50;
@@ -175,13 +178,16 @@ assign MisoLdLmx_i = 1'b1;
 assign emptyFlagTx = (trCnt > 71) ? 1'b1 : 1'b0;
 assign QSPITotalWordNum = LMXWordNum + DDSWordNum + POTWordNum + DACWordNum + ATTWordNum + ShRegWordNum + MaxWordNum + GPIOWordNum; 
 
-assign currClk = (modeSel) ? Clk10 : Clk10;
+assign currClk = (modeSel) ? Clk60 : Clk10;
 
 //***********************************************
 //	           CLOCK GENERATION
 //***********************************************
 always #(CLK_PERIOD/2) Clk_i = ~Clk_i;
 always #(10/2) Clk100 = ~Clk100;
+always #(5/2) Clk200 = ~Clk200;
+always #(8/2) Clk125 = ~Clk125;
+always #(16.67/2) Clk60 = ~Clk60;
 always #(20/2) Clk50 = ~Clk50;
 always #(12.5/2) Clk80 = ~Clk80;
 always #(41.67/2) Clk24 = ~Clk24;
@@ -196,6 +202,9 @@ initial begin
       // Initialize Inputs
       Clk_i = 1;
       Clk100= 1;
+      Clk200 = 1;
+      Clk125 = 1;
+      Clk60 = 1;
       Clk20 = 1;
       Clk50 = 1;
       Clk80 = 1;