Дополнены констрейны, исправлен InterfaceArbiter.

src/constr/SbTmsg.cst

@@ -5,7 +5,7 @@
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
 //Device Version: C
-//Created Time: Sat 04 27 17:55:23 2024
+//Created Time: Thu 05 02 13:46:56 2024
 
 IO_LOC "DataMax2870MixRf2_o" C1;
 IO_PORT "DataMax2870MixRf2_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;

src/constr/SbTmsg.sdc

@@ -2,7 +2,17 @@
 //All rights reserved.
 //File Title: Timing Constraints file
 //Tool Version: V1.9.9.02 
-//Created Time: 2024-04-27 18:00:03
-create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
+//Created Time: 2024-05-02 15:55:01
+create_clock -name clk5 -period 200 -waveform {0 100} [get_nets {clk5}]
+create_clock -name clk50 -period 20 -waveform {0 10} [get_nets {clk50}]
+create_clock -name clk26dot25 -period 38.095 -waveform {0 19.047} [get_nets {clk26dot25}]
+create_clock -name clk20 -period 50 -waveform {0 25} [get_nets {clk20}]
+create_clock -name clk100 -period 10 -waveform {0 5} [get_nets {gclk100}]
+create_clock -name clk210 -period 4.762 -waveform {0 2.381} [get_nets {ClkGen/clk210Mhz}]
 create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
-set_clock_groups -asynchronous -group [get_clocks {Clk_i Sck_i}]
+create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
+create_clock -name clk60 -period 16.667 -waveform {0 8.334} [get_nets {clk60}]
+set_clock_groups -asynchronous -group [get_clocks {Clk_i}] -group [get_clocks {Sck_i}]
+set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Clk_i}] 
+set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Sck_i}] 
+report_timing -setup -from_clock [get_clocks {clk100}] -max_paths 1000 -max_common_paths 1

src/src/InterfaceArbiter/InterfaceArbiter.v

@@ -90,9 +90,17 @@ module InterfaceArbiter
 	
 //================================================================================
 //  CODING
-	always @(posedge Sck_i or negedge Rst_i) begin
-		if (!Rst_i) begin
-			if (!Ss_i) begin
+	always @(posedge Sck_i or posedge Rst_i) begin 
+		if (Rst_i) begin 
+			captRegSspi <= 0;
+
+			captReg0 <= 0;
+			captReg1 <= 0;
+			captReg2 <= 0;
+			captReg3 <= 0;
+		end
+		else begin 
+			if (!Ss_i) begin 
 				captRegSspi <= {captRegSspi[OUTWORDWIDTH-2:0], Mosi0_i};
 				
 				captReg0 <= {captReg0[QSPIWORDWIDTH-2:0], Mosi0_i};
@@ -100,30 +108,25 @@ module InterfaceArbiter
 				captReg2 <= {captReg2[QSPIWORDWIDTH-2:0], Mosi2_i};
 				captReg3 <= {captReg3[QSPIWORDWIDTH-2:0], Mosi3_i};
 			end
-		end else begin
-			captRegSspi <= 0;
-				
-			captReg0 <= 0;
-			captReg1 <= 0;
-			captReg2 <= 0;
-			captReg3 <= 0;
 		end
 	end
 	
-	always @(posedge Sck_i or negedge Rst_i) begin
-		if (!Rst_i) begin
-			if (!Ss_i) begin
-				if (ssCnt == ssCntRstThresh) begin
-					ssCnt <= 0;
-				end else begin
-					ssCnt <= ssCnt+1;
+	always @(posedge Sck_i or posedge Rst_i) begin 
+		if (Rst_i) begin 
+			ssCnt <= 0;
+		end
+		else begin 
+			if (!Ss_i) begin 
+				if (ssCnt == ssCntRstThresh) begin 
+					ssCnt <= 0; 
+				end 
+				else begin 
+					ssCnt <= ssCnt+1; 
 				end
 			end
-		end else begin
-			ssCnt <= 0;
 		end
 	end
-	
+
 	always @(posedge Clk_i) begin
 		if (!Rst_i) begin
 			if (currState == DATARX) begin
@@ -146,19 +149,19 @@ module InterfaceArbiter
 		end
 	end
 	
-	always @(posedge Sck_i or negedge Rst_i) begin
-		if (!Rst_i) begin
-			if (currState == IDLE) begin
-				if (ssCnt == 1) begin
-					if (captRegSspi[0]) begin
-						spiMode <= 1'b1;	//quad
-					end else begin
-						spiMode <= 1'b0;	//single
-					end
+	always @(posedge Sck_i or posedge Rst_i) begin 
+		if (Rst_i) begin 
+			spiMode <= 1'b0;
+		end
+		else begin 
+			if (ssCnt == 1) begin 
+				if (captRegSspi[0]) begin 
+					spiMode <= 1'b1; 
+				end 
+				else begin 
+					spiMode <= 1'b0; 
 				end
 			end
-		end else begin
-			spiMode <= 1'b0;
 		end
 	end