Добавлены FIFO для всех устройств

src/src/FifoCtrl/Fifo16x3/Fifo16x3.ipc

@@ -0,0 +1,35 @@
+[General]
+ipc_version=4
+file=Fifo16x3
+module=Fifo16x3
+target_device=gw1n9-014
+type=fifo_hs
+version=1.0
+
+[Config]
+AlmostEmptyFlag=false
+AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter
+AlmostFullFlag=false
+AlmostFullFlagItem=Full_Single Threshold Constant Parameter
+BSRAM=true
+ControlledByRdEn=false
+ECCSelected=false
+EmptyClear=1
+EmptySet=1
+EnReset=true
+FirstWordFallThrough=false
+FullClear=1
+FullSet=1
+LANG=0
+OutputRegistersSelected=false
+REG=false
+ReadDataNum=false
+ReadDataWidth=16
+ReadDepth=2
+ResetSynchronization=true
+SSRAM=false
+StandardFIFO=true
+Synthesis_tool=GowinSynthesis
+WriteDataNum=false
+WriteDataWidth=16
+WriteDepth=2

src/src/FifoCtrl/Fifo16x3/Fifo16x3.v

@@ -0,0 +1,177 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Wed Apr 24 12:55:54 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=5808)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+`pragma protect end_protected
+module Fifo16x3 (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [15:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [15:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.Fifo16x3  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[15:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[15:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* Fifo16x3 */

src/src/FifoCtrl/Fifo16x3/Fifo16x3.vo

@@ -0,0 +1,331 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Post-PnR Simulation Model file
+//Tool Version: V1.9.9.02
+//Created Time: Wed Apr 24 12:55:54 2024
+
+`timescale 100 ps/100 ps
+module Fifo16x3(
+	Data,
+	Reset,
+	WrClk,
+	RdClk,
+	WrEn,
+	RdEn,
+	Q,
+	Empty,
+	Full
+);
+input [15:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [15:0] Q;
+output Empty;
+output Full;
+wire [15:0] Data;
+wire Empty;
+wire Full;
+wire GND;
+wire [15:0] Q;
+wire RdClk;
+wire RdEn;
+wire Reset;
+wire VCC;
+wire WrClk;
+wire WrEn;
+wire \fifo_inst/n20_5 ;
+wire \fifo_inst/n24_3 ;
+wire \fifo_inst/n167_3 ;
+wire \fifo_inst/n218_4 ;
+wire \fifo_inst/rempty_val ;
+wire \fifo_inst/wfull_val_7 ;
+wire \fifo_inst/wfull_val1 ;
+wire \fifo_inst/wfull_val1_0 ;
+wire \fifo_inst/Full_1 ;
+wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/rbin_num_next_0_9 ;
+wire \fifo_inst/rempty_val1 ;
+wire \fifo_inst/wfull_val1_2 ;
+wire \fifo_inst/wfull_val1_3 ;
+wire \fifo_inst/Full_1_2 ;
+wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n4_6 ;
+wire \fifo_inst/n9_6 ;
+wire [0:0] \fifo_inst/Equal.wgraynext ;
+wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:1] \fifo_inst/rbin_num_next ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
+wire [1:0] \fifo_inst/reset_r ;
+wire [1:0] \fifo_inst/reset_w ;
+wire [1:0] \fifo_inst/rbin_num ;
+wire [0:0] \fifo_inst/rptr ;
+wire [1:0] \fifo_inst/wptr ;
+wire [0:0] \fifo_inst/Equal.wbin ;
+wire [31:16] \fifo_inst/DO ;
+VCC VCC_cZ (
+  .V(VCC)
+);
+GND GND_cZ (
+  .G(GND)
+);
+GSR GSR (
+	.GSRI(VCC)
+);
+LUT4 \fifo_inst/n20_s1  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(WrEn),
+	.F(\fifo_inst/n20_5 )
+);
+defparam \fifo_inst/n20_s1 .INIT=16'h5300;
+LUT2 \fifo_inst/n24_s0  (
+	.I0(Empty),
+	.I1(RdEn),
+	.F(\fifo_inst/n24_3 )
+);
+defparam \fifo_inst/n24_s0 .INIT=4'h4;
+LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wgraynext [0])
+);
+defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
+LUT2 \fifo_inst/n167_s0  (
+	.I0(\fifo_inst/rempty_val ),
+	.I1(\fifo_inst/reset_r [1]),
+	.F(\fifo_inst/n167_3 )
+);
+defparam \fifo_inst/n167_s0 .INIT=4'hE;
+LUT2 \fifo_inst/n218_s1  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.F(\fifo_inst/n218_4 )
+);
+defparam \fifo_inst/n218_s1 .INIT=4'h4;
+LUT4 \fifo_inst/rempty_val_s3  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rempty_val )
+);
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h9009;
+LUT4 \fifo_inst/wfull_val_s3  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rptr [0]),
+	.F(\fifo_inst/wfull_val_7 )
+);
+defparam \fifo_inst/wfull_val_s3 .INIT=16'h1428;
+LUT3 \fifo_inst/wfull_val1_s9  (
+	.I0(\fifo_inst/wfull_val1_3 ),
+	.I1(\fifo_inst/wfull_val1_2 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1 )
+);
+defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
+LUT3 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val1_0 ),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/wfull_val1_0 )
+);
+defparam \fifo_inst/wfull_val1_s10 .INIT=8'h0E;
+LUT3 \fifo_inst/Full_d_s  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.F(Full)
+);
+defparam \fifo_inst/Full_d_s .INIT=8'hAC;
+LUT3 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/Full_1 ),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/Full_1 )
+);
+defparam \fifo_inst/Full_s8 .INIT=8'h0E;
+LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wbinnext_0_7 )
+);
+defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
+LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
+LUT4 \fifo_inst/rbin_num_next_1_s3  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s3 .INIT=16'hBF40;
+LUT3 \fifo_inst/rbin_num_next_0_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next_0_9 )
+);
+defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
+LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
+DFFP \fifo_inst/reset_r_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [0])
+);
+defparam \fifo_inst/reset_r_0_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_1_s0  (
+	.D(\fifo_inst/reset_w [0]),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [1])
+);
+defparam \fifo_inst/reset_w_1_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [0])
+);
+defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_1_s0  (
+	.D(\fifo_inst/rbin_num_next [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [1])
+);
+defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_0_s0  (
+	.D(\fifo_inst/rbin_num_next_0_9 ),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [0])
+);
+defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_0_s0  (
+	.D(\fifo_inst/Equal.rgraynext [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [0])
+);
+defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [1])
+);
+defparam \fifo_inst/wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_0_s0  (
+	.D(\fifo_inst/Equal.wgraynext [0]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [0])
+);
+defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_0_s0  (
+	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [0])
+);
+defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
+DFFP \fifo_inst/rempty_val1_s0  (
+	.D(\fifo_inst/rempty_val ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n167_3 ),
+	.Q(\fifo_inst/rempty_val1 )
+);
+defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val1 ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n167_3 ),
+	.Q(Empty)
+);
+defparam \fifo_inst/Empty_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_r_1_s0  (
+	.D(\fifo_inst/reset_r [0]),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [1])
+);
+defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
+DFFC \fifo_inst/wfull_val1_s0  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wfull_val1_2 )
+);
+defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
+DFFP \fifo_inst/wfull_val1_s1  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n218_4 ),
+	.Q(\fifo_inst/wfull_val1_3 )
+);
+defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
+DFFC \fifo_inst/Full_s0  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Full_1_2 )
+);
+defparam \fifo_inst/Full_s0 .INIT=1'b0;
+DFFP \fifo_inst/Full_s1  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n218_4 ),
+	.Q(\fifo_inst/Full_2 )
+);
+defparam \fifo_inst/Full_s1 .INIT=1'b1;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n20_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n24_3 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[15:0]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, GND, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND, GND}),
+	.DO({\fifo_inst/DO [31:16], Q[15:0]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=16;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=16;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+INV \fifo_inst/n4_s2  (
+	.I(RdClk),
+	.O(\fifo_inst/n4_6 )
+);
+INV \fifo_inst/n9_s2  (
+	.I(WrClk),
+	.O(\fifo_inst/n9_6 )
+);
+endmodule

src/src/FifoCtrl/Fifo16x3/Fifo16x3_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Wed Apr 24 12:55:54 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	Fifo16x3 your_instance_name(
+		.Data(Data_i), //input [15:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [15:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/FifoCtrl/Fifo16x3/temp/FIFOHS/FIFOHS.prj

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
+    <FileList>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/Fifo16x3/temp/FIFOHS"/>
+        <Option type="output_file" value="Fifo16x3.vg"/>
+        <Option type="output_template" value="Fifo16x3_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/FifoCtrl/Fifo16x3/temp/FIFOHS/Fifo16x3.log

@@ -0,0 +1,45 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'Fifo16x3'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+NOTE  (EX0101) : Current top module is "Fifo16x3"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\Fifo16x3\temp\FIFOHS\Fifo16x3.vg" completed
+Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\Fifo16x3\temp\FIFOHS\Fifo16x3_tmp.v" completed
+[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\Fifo16x3\temp\FIFOHS\Fifo16x3_syn.rpt.html" completed
+GowinSynthesis finish

src/src/FifoCtrl/Fifo16x3/temp/FIFOHS/Fifo16x3.vg

@@ -0,0 +1,177 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Wed Apr 24 12:55:54 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
+vahir674uzd2OiV3w+Bn5UM7bqyXNIfBVZd6eqmzcuorRygBunqP4eqIhVyXOS1sSnqfiX/x128w
+OswsCnNb9H26NFu2OM6ZKD2lja7iiBqBAZSG9YL+oppPlATFy282YLNHt4PWNohA2xmsXHf+33mZ
+MsgIQ/rjHRJeRnCETz1LqexF5DvqrAgpdDFY//lAHK2y1KyqlZZplE5j78p3tpKt/LPMdf76sK7s
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=5808)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+`pragma protect end_protected
+module Fifo16x3 (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [15:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [15:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.Fifo16x3  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[15:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[15:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* Fifo16x3 */

src/src/FifoCtrl/Fifo16x3/temp/FIFOHS/Fifo16x3_syn_resource.html

@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">Fifo16x3 (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">16</td>
+<td align = "center">-</td>
+<td align = "center">18</td>
+<td align = "center">-</td>
+<td align = "center">1</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/FifoCtrl/Fifo16x3/temp/FIFOHS/Fifo16x3_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="Fifo16x3" Register="16" Lut="18" Bsram="1" T_Register="16(16)" T_Lut="18(18)" T_Bsram="1(1)"/>

src/src/FifoCtrl/Fifo16x3/temp/FIFOHS/Fifo16x3_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Wed Apr 24 12:55:54 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	Fifo16x3 your_instance_name(
+		.Data(Data_i), //input [15:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [15:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/FifoCtrl/Fifo16x3/temp/FIFOHS/fifo_define.v

@@ -0,0 +1,4 @@
+`define module_name Fifo16x3
+`define EBR_BASED
+`define En_Reset
+`define Reset_Synchronization

src/src/FifoCtrl/Fifo16x3/temp/FIFOHS/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 2;
+parameter ASIZE = 1;
+parameter WDSIZE = 16;
+parameter RDEPTH = 2;
+parameter RASIZE = 1;
+parameter RDSIZE = 16;

src/src/FifoCtrl/Fifo16x3/temp/FIFOHS/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/FifoCtrl/FifoCtrl.v

@@ -32,7 +32,8 @@ module FifoCtrl #(
 
     output [OUT_WIDTH-1:0] Data_o,
     output reg ReadEn_o,
-    output reg  WriteEn_o
+    output reg  WriteEn_o,
+    output reg ValRdData_o
 
 );
 //================================================================================
@@ -132,16 +133,30 @@ always @(posedge WrClk_i) begin
     end
 end
 
-always @(posedge RdClk_i) begin
+always @(*) begin
     if (Rst_i) begin 
-        ReadEn_o <= 1'b0;
+        ReadEn_o = 1'b0;
     end
     else begin  
         if (!FifoEmpty_i && !BusySpiM_i) begin 
-            ReadEn_o <= 1'b1;
+            ReadEn_o = 1'b1;
         end
         else begin 
-            ReadEn_o <= 1'b0;
+            ReadEn_o = 1'b0;
+        end
+    end
+end
+
+always @(posedge RdClk_i) begin 
+    if (Rst_i) begin 
+        ValRdData_o <= 1'b0;
+    end
+    else begin 
+        if (ReadEn_o) begin 
+            ValRdData_o <= 1'b1;
+        end
+        else begin 
+            ValRdData_o <= 1'b0;
         end
     end
 end

src/src/FifoCtrl/FifoCtrl_tb.do

@@ -0,0 +1,39 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider FifoCtrlDDS
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/IN_WIDTH
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/WR_NUM
+add wave -noupdate -radix unsigned /FifoCtrl_tb/FifoCtrlDDS_inst/OUT_WIDTH
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/DATA_WIDTH
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/WrClk_i
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/RdClk_i
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/Rst_i
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/Data_i
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/Val_i
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/BusySpiM_i
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/FifoFull_i
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/FifoEmpty_i
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/Data_o
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/ReadEn_o
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/ValRdData_o
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/WriteEn_o
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/dataReg
+add wave -noupdate /FifoCtrl_tb/FifoCtrlDDS_inst/wrCnt
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {11121814 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {15750 ns}

src/src/FifoCtrl/FifoCtrl_tb.sv

@@ -48,7 +48,7 @@ localparam TWENTY_MHZ = 50;
 //	           CLOCK GENERATION
 //***********************************************
 always begin
-    #5 WrClk_i = ~WrClk_i;
+    #50 WrClk_i = ~WrClk_i;
     #(FIFTY_MHZ/2) RdClkDDS_i = ~RdClkDDS_i;
     #(SIXTY_MHZ/2) RdClkLMX_i = ~RdClkLMX_i;
     #(TWENTY_MHZ/2) RdClkMax_i = ~RdClkMax_i;
@@ -71,6 +71,7 @@ FifoCtrl#(
     .BusySpiM_i(BusySpiDDS),
     .Data_o(dataToFifo64),
     .ReadEn_o(rdEnDDS),
+    .ValRdData_o(valRdDDS),
     .WriteEn_o(wrEnDDS)
 );
 
@@ -89,6 +90,7 @@ FifoCtrl #(
     .BusySpiM_i(BusySpiLMX),
     .Data_o(dataToFifo24),
     .ReadEn_o(rdEnLMX),
+    .ValRdData_o(valRdLMX),
     .WriteEn_o(wrEnLMX)
 );
 
@@ -107,12 +109,14 @@ FifoCtrl #(
     .BusySpiM_i(BusySpiMax),
     .Data_o(dataToFifo32),
     .ReadEn_o(rdEnMax),
+    .ValRdData_o(valRdMax),
     .WriteEn_o(wrEnMax)
 );
 // Depth 16
 FifoLMX FifoLMX_inst (
     .Data(dataToFifo24),
     .WrClk(WrClk_i),
+    .Reset(Rst_i),
     .RdClk(RdClkLMX_i),
     .WrEn(wrEnLMX),
     .RdEn(rdEnLMX),
@@ -124,6 +128,7 @@ FifoLMX FifoLMX_inst (
 FifoDDS FifoDDS_inst (
     .Data(dataToFifo64),
     .WrClk(WrClk_i),
+    .Reset(Rst_i),
     .RdClk(RdClkDDS_i),
     .WrEn(wrEnDDS),
     .RdEn(rdEnDDS),
@@ -132,9 +137,10 @@ FifoDDS FifoDDS_inst (
     .Full(fullFlagDDS)
 );
 //Depth 4
-FifoMax FifoMax_inst (
+FifoMax2870 FifoMax_inst (
     .Data(dataToFifo32),
     .WrClk(WrClk_i),
+    .Reset(Rst_i),
     .RdClk(RdClkMax_i),
     .WrEn(wrEnMax),
     .RdEn(rdEnMax),
@@ -148,7 +154,7 @@ SpiM #(
 )SpiMLMX_inst(
     .Clk_i(RdClkLMX_i),
     .Rst_i(Rst_i),
-    .Val_i(rdEnLMX),
+    .Val_i(valRdLMX),
     .SpiData_i(dataFromFifo24),
     .Busy_o(BusySpiLMX)
 );
@@ -158,7 +164,7 @@ SpiM #(
 )SpiMDDS_inst(
     .Clk_i(RdClkDDS_i),
     .Rst_i(Rst_i),
-    .Val_i(rdEnDDS),
+    .Val_i(valRdDDS),
     .SpiData_i(dataFromFifo64),
     .Busy_o(BusySpiDDS)
 );
@@ -168,7 +174,7 @@ SpiM #(
 )SpiMMax_inst(
     .Clk_i(RdClkMax_i),
     .Rst_i(Rst_i),
-    .Val_i(rdEnMax),
+    .Val_i(valRdMax),
     .SpiData_i(dataFromFifo32),
     .Busy_o(BusySpiMax)
 );
@@ -178,7 +184,6 @@ SpiM #(
 task drive_fifo64();
     valFromSPI64 = 1'b0;
     #300;
-    wait(!BusySpiDDS)
     @ (posedge WrClk_i)
     valFromSPI64 = 1'b1;
     dataForDDS = {8'h0, 16'hFFFF};
@@ -186,7 +191,6 @@ task drive_fifo64();
     @(posedge WrClk_i)
     valFromSPI64 = 1'b0;
     #300;
-    wait(!BusySpiDDS)
     @ (posedge WrClk_i)
     valFromSPI64 = 1'b1;
     dataForDDS = 24'habcdef;
@@ -194,7 +198,6 @@ task drive_fifo64();
     @ (posedge WrClk_i)
     valFromSPI64 = 1'b0;
     #300;
-    wait(!BusySpiDDS)
     @ (posedge WrClk_i)
     valFromSPI64 = 1'b1;
     dataForDDS = 24'h123456;
@@ -242,7 +245,6 @@ task drive_fifo24();
     #200;
     Rst_i = 1'b0;
     #300;
-    wait(!BusySpiLMX)
     @ (posedge WrClk_i)
     valFromSPI24 = 1'b1;
     dataForLMX = 24'h123456;
@@ -250,7 +252,6 @@ task drive_fifo24();
     @(posedge WrClk_i)
     valFromSPI24 = 1'b0;
     #300;
-    wait(!BusySpiLMX)
     @ (posedge WrClk_i)
     valFromSPI24 = 1'b1;
     dataForLMX = 24'habcdef;

src/src/FifoCtrl/FifoDDS/FifoDDS.ipc

@@ -0,0 +1,35 @@
+[General]
+ipc_version=4
+file=FifoDDS
+module=FifoDDS
+target_device=gw1n9-014
+type=fifo_hs
+version=1.0
+
+[Config]
+AlmostEmptyFlag=false
+AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter
+AlmostFullFlag=false
+AlmostFullFlagItem=Full_Single Threshold Constant Parameter
+BSRAM=true
+ControlledByRdEn=false
+ECCSelected=false
+EmptyClear=1
+EmptySet=1
+EnReset=true
+FirstWordFallThrough=false
+FullClear=1
+FullSet=1
+LANG=0
+OutputRegistersSelected=false
+REG=false
+ReadDataNum=false
+ReadDataWidth=64
+ReadDepth=2
+ResetSynchronization=true
+SSRAM=false
+StandardFIFO=true
+Synthesis_tool=GowinSynthesis
+WriteDataNum=false
+WriteDataWidth=64
+WriteDepth=2

src/src/FifoCtrl/FifoDDS/FifoDDS.v

@@ -0,0 +1,189 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Wed Apr 24 12:25:14 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6464)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+S1uLEXyA72HuhqvzIqpFEi+qHnxy7mk=
+`pragma protect end_protected
+module FifoDDS (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [63:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [63:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoDDS  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[63:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[63:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoDDS */

src/src/FifoCtrl/FifoDDS/FifoDDS.vo

@@ -0,0 +1,351 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Post-PnR Simulation Model file
+//Tool Version: V1.9.9.02
+//Created Time: Wed Apr 24 12:25:14 2024
+
+`timescale 100 ps/100 ps
+module FifoDDS(
+	Data,
+	Reset,
+	WrClk,
+	RdClk,
+	WrEn,
+	RdEn,
+	Q,
+	Empty,
+	Full
+);
+input [63:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [63:0] Q;
+output Empty;
+output Full;
+wire [63:0] Data;
+wire Empty;
+wire Full;
+wire GND;
+wire [63:0] Q;
+wire RdClk;
+wire RdEn;
+wire Reset;
+wire VCC;
+wire WrClk;
+wire WrEn;
+wire \fifo_inst/n20_5 ;
+wire \fifo_inst/n24_3 ;
+wire \fifo_inst/n359_3 ;
+wire \fifo_inst/n458_4 ;
+wire \fifo_inst/rempty_val ;
+wire \fifo_inst/wfull_val_7 ;
+wire \fifo_inst/wfull_val1 ;
+wire \fifo_inst/wfull_val1_0 ;
+wire \fifo_inst/Full_1 ;
+wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/rbin_num_next_0_9 ;
+wire \fifo_inst/rempty_val1 ;
+wire \fifo_inst/wfull_val1_2 ;
+wire \fifo_inst/wfull_val1_3 ;
+wire \fifo_inst/Full_1_2 ;
+wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n4_6 ;
+wire \fifo_inst/n9_6 ;
+wire [0:0] \fifo_inst/Equal.wgraynext ;
+wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:1] \fifo_inst/rbin_num_next ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
+wire [1:0] \fifo_inst/reset_r ;
+wire [1:0] \fifo_inst/reset_w ;
+wire [1:0] \fifo_inst/rbin_num ;
+wire [0:0] \fifo_inst/rptr ;
+wire [1:0] \fifo_inst/wptr ;
+wire [0:0] \fifo_inst/Equal.wbin ;
+VCC VCC_cZ (
+  .V(VCC)
+);
+GND GND_cZ (
+  .G(GND)
+);
+GSR GSR (
+	.GSRI(VCC)
+);
+LUT4 \fifo_inst/n20_s1  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(WrEn),
+	.F(\fifo_inst/n20_5 )
+);
+defparam \fifo_inst/n20_s1 .INIT=16'h5300;
+LUT2 \fifo_inst/n24_s0  (
+	.I0(Empty),
+	.I1(RdEn),
+	.F(\fifo_inst/n24_3 )
+);
+defparam \fifo_inst/n24_s0 .INIT=4'h4;
+LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wgraynext [0])
+);
+defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
+LUT2 \fifo_inst/n359_s0  (
+	.I0(\fifo_inst/rempty_val ),
+	.I1(\fifo_inst/reset_r [1]),
+	.F(\fifo_inst/n359_3 )
+);
+defparam \fifo_inst/n359_s0 .INIT=4'hE;
+LUT2 \fifo_inst/n458_s1  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.F(\fifo_inst/n458_4 )
+);
+defparam \fifo_inst/n458_s1 .INIT=4'h4;
+LUT4 \fifo_inst/rempty_val_s3  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rempty_val )
+);
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h9009;
+LUT4 \fifo_inst/wfull_val_s3  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rptr [0]),
+	.F(\fifo_inst/wfull_val_7 )
+);
+defparam \fifo_inst/wfull_val_s3 .INIT=16'h1428;
+LUT3 \fifo_inst/wfull_val1_s9  (
+	.I0(\fifo_inst/wfull_val1_3 ),
+	.I1(\fifo_inst/wfull_val1_2 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1 )
+);
+defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
+LUT3 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val1_0 ),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/wfull_val1_0 )
+);
+defparam \fifo_inst/wfull_val1_s10 .INIT=8'h0E;
+LUT3 \fifo_inst/Full_d_s  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.F(Full)
+);
+defparam \fifo_inst/Full_d_s .INIT=8'hAC;
+LUT3 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/Full_1 ),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/Full_1 )
+);
+defparam \fifo_inst/Full_s8 .INIT=8'h0E;
+LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wbinnext_0_7 )
+);
+defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
+LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
+LUT4 \fifo_inst/rbin_num_next_1_s3  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s3 .INIT=16'hBF40;
+LUT3 \fifo_inst/rbin_num_next_0_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next_0_9 )
+);
+defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
+LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
+DFFP \fifo_inst/reset_r_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [0])
+);
+defparam \fifo_inst/reset_r_0_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_1_s0  (
+	.D(\fifo_inst/reset_w [0]),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [1])
+);
+defparam \fifo_inst/reset_w_1_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [0])
+);
+defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_1_s0  (
+	.D(\fifo_inst/rbin_num_next [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [1])
+);
+defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_0_s0  (
+	.D(\fifo_inst/rbin_num_next_0_9 ),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [0])
+);
+defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_0_s0  (
+	.D(\fifo_inst/Equal.rgraynext [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [0])
+);
+defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [1])
+);
+defparam \fifo_inst/wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_0_s0  (
+	.D(\fifo_inst/Equal.wgraynext [0]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [0])
+);
+defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_0_s0  (
+	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [0])
+);
+defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
+DFFP \fifo_inst/rempty_val1_s0  (
+	.D(\fifo_inst/rempty_val ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n359_3 ),
+	.Q(\fifo_inst/rempty_val1 )
+);
+defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val1 ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n359_3 ),
+	.Q(Empty)
+);
+defparam \fifo_inst/Empty_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_r_1_s0  (
+	.D(\fifo_inst/reset_r [0]),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [1])
+);
+defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
+DFFC \fifo_inst/wfull_val1_s0  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wfull_val1_2 )
+);
+defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
+DFFP \fifo_inst/wfull_val1_s1  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n458_4 ),
+	.Q(\fifo_inst/wfull_val1_3 )
+);
+defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
+DFFC \fifo_inst/Full_s0  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Full_1_2 )
+);
+defparam \fifo_inst/Full_s0 .INIT=1'b0;
+DFFP \fifo_inst/Full_s1  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n458_4 ),
+	.Q(\fifo_inst/Full_2 )
+);
+defparam \fifo_inst/Full_s1 .INIT=1'b1;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n20_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n24_3 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({Data[31:0]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND, GND, GND}),
+	.DO({Q[31:0]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_1_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n20_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n24_3 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({Data[63:32]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND, GND, GND}),
+	.DO({Q[63:32]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BIT_WIDTH_0=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BIT_WIDTH_1=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BLK_SEL_1=3'b000;
+INV \fifo_inst/n4_s2  (
+	.I(RdClk),
+	.O(\fifo_inst/n4_6 )
+);
+INV \fifo_inst/n9_s2  (
+	.I(WrClk),
+	.O(\fifo_inst/n9_6 )
+);
+endmodule

src/src/FifoCtrl/FifoDDS/FifoDDS_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Wed Apr 24 12:25:14 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoDDS your_instance_name(
+		.Data(Data_i), //input [63:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [63:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/FifoCtrl/FifoDDS/temp/FIFOHS/FIFOHS.prj

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
+    <FileList>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/fifo_hs/temp/FIFOHS"/>
+        <Option type="output_file" value="FifoDDS.vg"/>
+        <Option type="output_template" value="FifoDDS_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/FifoCtrl/FifoDDS/temp/FIFOHS/FifoDDS.log

@@ -0,0 +1,45 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoDDS'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+NOTE  (EX0101) : Current top module is "FifoDDS"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\fifo_hs\temp\FIFOHS\FifoDDS.vg" completed
+Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\fifo_hs\temp\FIFOHS\FifoDDS_tmp.v" completed
+[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\fifo_hs\temp\FIFOHS\FifoDDS_syn.rpt.html" completed
+GowinSynthesis finish

src/src/FifoCtrl/FifoDDS/temp/FIFOHS/FifoDDS.vg

@@ -0,0 +1,189 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Wed Apr 24 12:25:14 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+3lcjaqbvI4T9REBx2R3WmlHRx2Hq0N3AFEWgOQ==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6464)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+S1uLEXyA72HuhqvzIqpFEi+qHnxy7mk=
+`pragma protect end_protected
+module FifoDDS (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [63:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [63:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoDDS  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[63:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[63:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoDDS */

src/src/FifoCtrl/FifoDDS/temp/FIFOHS/FifoDDS_syn_resource.html

@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoDDS (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">16</td>
+<td align = "center">-</td>
+<td align = "center">18</td>
+<td align = "center">-</td>
+<td align = "center">2</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/FifoCtrl/FifoDDS/temp/FIFOHS/FifoDDS_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoDDS" Register="16" Lut="18" Bsram="2" T_Register="16(16)" T_Lut="18(18)" T_Bsram="2(2)"/>

src/src/FifoCtrl/FifoDDS/temp/FIFOHS/FifoDDS_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Wed Apr 24 12:25:14 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoDDS your_instance_name(
+		.Data(Data_i), //input [63:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [63:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/FifoCtrl/FifoDDS/temp/FIFOHS/fifo_define.v

@@ -0,0 +1,4 @@
+`define module_name FifoDDS
+`define EBR_BASED
+`define En_Reset
+`define Reset_Synchronization

src/src/FifoCtrl/FifoDDS/temp/FIFOHS/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 2;
+parameter ASIZE = 1;
+parameter WDSIZE = 64;
+parameter RDEPTH = 2;
+parameter RASIZE = 1;
+parameter RDSIZE = 64;

src/src/FifoCtrl/FifoDDS/temp/FIFOHS/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/FifoCtrl/FifoLMX/FifoLMX.ipc

@@ -0,0 +1,35 @@
+[General]
+ipc_version=4
+file=FifoLMX
+module=FifoLMX
+target_device=gw1n9-014
+type=fifo_hs
+version=1.0
+
+[Config]
+AlmostEmptyFlag=false
+AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter
+AlmostFullFlag=false
+AlmostFullFlagItem=Full_Single Threshold Constant Parameter
+BSRAM=true
+ControlledByRdEn=false
+ECCSelected=false
+EmptyClear=1
+EmptySet=1
+EnReset=true
+FirstWordFallThrough=false
+FullClear=1
+FullSet=1
+LANG=0
+OutputRegistersSelected=false
+REG=false
+ReadDataNum=false
+ReadDataWidth=24
+ReadDepth=16
+ResetSynchronization=true
+SSRAM=false
+StandardFIFO=true
+Synthesis_tool=GowinSynthesis
+WriteDataNum=false
+WriteDataWidth=24
+WriteDepth=16

src/src/FifoCtrl/FifoLMX/FifoLMX.v

@@ -0,0 +1,283 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Wed Apr 24 12:23:21 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=11824)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+h0CJ2e7b8jmTGvIdzhP2nVeDnFJTEUzP9g==
+`pragma protect end_protected
+module FifoLMX (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [23:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [23:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoLMX  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[23:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[23:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoLMX */

src/src/FifoCtrl/FifoLMX/FifoLMX.vo

@@ -0,0 +1,625 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Post-PnR Simulation Model file
+//Tool Version: V1.9.9.02
+//Created Time: Wed Apr 24 12:23:21 2024
+
+`timescale 100 ps/100 ps
+module FifoLMX(
+	Data,
+	Reset,
+	WrClk,
+	RdClk,
+	WrEn,
+	RdEn,
+	Q,
+	Empty,
+	Full
+);
+input [23:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [23:0] Q;
+output Empty;
+output Full;
+wire [23:0] Data;
+wire Empty;
+wire Full;
+wire GND;
+wire [23:0] Q;
+wire RdClk;
+wire RdEn;
+wire Reset;
+wire VCC;
+wire WrClk;
+wire WrEn;
+wire \fifo_inst/n23_5 ;
+wire \fifo_inst/n27_3 ;
+wire \fifo_inst/wfull_val ;
+wire \fifo_inst/n277_3 ;
+wire \fifo_inst/n372_4 ;
+wire \fifo_inst/wfull_val1 ;
+wire \fifo_inst/wfull_val1_0 ;
+wire \fifo_inst/Full_1 ;
+wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/Equal.rgraynext_2_4 ;
+wire \fifo_inst/Equal.wgraynext_1_4 ;
+wire \fifo_inst/Equal.wgraynext_2_4 ;
+wire \fifo_inst/Equal.wgraynext_3_4 ;
+wire \fifo_inst/wfull_val_4 ;
+wire \fifo_inst/wfull_val_5 ;
+wire \fifo_inst/n372_5 ;
+wire \fifo_inst/wfull_val1_16 ;
+wire \fifo_inst/Full_11 ;
+wire \fifo_inst/rbin_num_next_0_9 ;
+wire \fifo_inst/rempty_val ;
+wire \fifo_inst/rempty_val1 ;
+wire \fifo_inst/wfull_val1_2 ;
+wire \fifo_inst/wfull_val1_3 ;
+wire \fifo_inst/Full_1_2 ;
+wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n128_1_SUM ;
+wire \fifo_inst/n128_3 ;
+wire \fifo_inst/n129_1_SUM ;
+wire \fifo_inst/n129_3 ;
+wire \fifo_inst/n130_1_SUM ;
+wire \fifo_inst/n130_3 ;
+wire \fifo_inst/n131_1_SUM ;
+wire \fifo_inst/n131_3 ;
+wire \fifo_inst/n4_6 ;
+wire \fifo_inst/n9_6 ;
+wire [3:0] \fifo_inst/Equal.rgraynext ;
+wire [3:0] \fifo_inst/Equal.wgraynext ;
+wire [4:1] \fifo_inst/rbin_num_next ;
+wire [4:1] \fifo_inst/Equal.wbinnext ;
+wire [1:0] \fifo_inst/reset_r ;
+wire [1:0] \fifo_inst/reset_w ;
+wire [4:0] \fifo_inst/rbin_num ;
+wire [3:0] \fifo_inst/rptr ;
+wire [4:0] \fifo_inst/wptr ;
+wire [3:0] \fifo_inst/Equal.wbin ;
+wire [31:24] \fifo_inst/DO ;
+VCC VCC_cZ (
+  .V(VCC)
+);
+GND GND_cZ (
+  .G(GND)
+);
+GSR GSR (
+	.GSRI(VCC)
+);
+LUT4 \fifo_inst/n23_s1  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(WrEn),
+	.F(\fifo_inst/n23_5 )
+);
+defparam \fifo_inst/n23_s1 .INIT=16'h5300;
+LUT2 \fifo_inst/n27_s0  (
+	.I0(Empty),
+	.I1(RdEn),
+	.F(\fifo_inst/n27_3 )
+);
+defparam \fifo_inst/n27_s0 .INIT=4'h4;
+LUT4 \fifo_inst/Equal.rgraynext_1_s0  (
+	.I0(\fifo_inst/n27_3 ),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [2]),
+	.F(\fifo_inst/Equal.rgraynext [1])
+);
+defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=16'h07F8;
+LUT3 \fifo_inst/Equal.rgraynext_2_s0  (
+	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/rbin_num [3]),
+	.F(\fifo_inst/Equal.rgraynext [2])
+);
+defparam \fifo_inst/Equal.rgraynext_2_s0 .INIT=8'h1E;
+LUT4 \fifo_inst/Equal.rgraynext_3_s0  (
+	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/rbin_num [3]),
+	.I3(\fifo_inst/rbin_num [4]),
+	.F(\fifo_inst/Equal.rgraynext [3])
+);
+defparam \fifo_inst/Equal.rgraynext_3_s0 .INIT=16'h07F8;
+LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
+	.I0(\fifo_inst/n23_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.F(\fifo_inst/Equal.wgraynext [0])
+);
+defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
+LUT4 \fifo_inst/Equal.wgraynext_1_s0  (
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_1_4 ),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.I3(\fifo_inst/Equal.wbin [2]),
+	.F(\fifo_inst/Equal.wgraynext [1])
+);
+defparam \fifo_inst/Equal.wgraynext_1_s0 .INIT=16'h0BF4;
+LUT4 \fifo_inst/Equal.wgraynext_2_s0  (
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_2_4 ),
+	.I2(\fifo_inst/Equal.wbin [2]),
+	.I3(\fifo_inst/Equal.wbin [3]),
+	.F(\fifo_inst/Equal.wgraynext [2])
+);
+defparam \fifo_inst/Equal.wgraynext_2_s0 .INIT=16'h0BF4;
+LUT4 \fifo_inst/Equal.wgraynext_3_s0  (
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_3_4 ),
+	.I2(\fifo_inst/Equal.wbin [3]),
+	.I3(\fifo_inst/wptr [4]),
+	.F(\fifo_inst/Equal.wgraynext [3])
+);
+defparam \fifo_inst/Equal.wgraynext_3_s0 .INIT=16'h0BF4;
+LUT4 \fifo_inst/wfull_val_s0  (
+	.I0(\fifo_inst/wptr [4]),
+	.I1(\fifo_inst/rbin_num [4]),
+	.I2(\fifo_inst/wfull_val_4 ),
+	.I3(\fifo_inst/wfull_val_5 ),
+	.F(\fifo_inst/wfull_val )
+);
+defparam \fifo_inst/wfull_val_s0 .INIT=16'h6000;
+LUT2 \fifo_inst/n277_s0  (
+	.I0(\fifo_inst/rempty_val ),
+	.I1(\fifo_inst/reset_r [1]),
+	.F(\fifo_inst/n277_3 )
+);
+defparam \fifo_inst/n277_s0 .INIT=4'hE;
+LUT3 \fifo_inst/n372_s1  (
+	.I0(\fifo_inst/wfull_val_4 ),
+	.I1(\fifo_inst/wfull_val_5 ),
+	.I2(\fifo_inst/n372_5 ),
+	.F(\fifo_inst/n372_4 )
+);
+defparam \fifo_inst/n372_s1 .INIT=8'h80;
+LUT3 \fifo_inst/wfull_val1_s9  (
+	.I0(\fifo_inst/wfull_val1_3 ),
+	.I1(\fifo_inst/wfull_val1_2 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1 )
+);
+defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
+LUT4 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val_5 ),
+	.I1(\fifo_inst/n372_5 ),
+	.I2(\fifo_inst/wfull_val_4 ),
+	.I3(\fifo_inst/wfull_val1_16 ),
+	.F(\fifo_inst/wfull_val1_0 )
+);
+defparam \fifo_inst/wfull_val1_s10 .INIT=16'hFF80;
+LUT3 \fifo_inst/Full_d_s  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.F(Full)
+);
+defparam \fifo_inst/Full_d_s .INIT=8'hAC;
+LUT4 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/wfull_val_5 ),
+	.I1(\fifo_inst/n372_5 ),
+	.I2(\fifo_inst/wfull_val_4 ),
+	.I3(\fifo_inst/Full_11 ),
+	.F(\fifo_inst/Full_1 )
+);
+defparam \fifo_inst/Full_s8 .INIT=16'hFF80;
+LUT2 \fifo_inst/rbin_num_next_2_s3  (
+	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
+	.I1(\fifo_inst/rbin_num [2]),
+	.F(\fifo_inst/rbin_num_next [2])
+);
+defparam \fifo_inst/rbin_num_next_2_s3 .INIT=4'h6;
+LUT3 \fifo_inst/rbin_num_next_3_s3  (
+	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/rbin_num [3]),
+	.F(\fifo_inst/rbin_num_next [3])
+);
+defparam \fifo_inst/rbin_num_next_3_s3 .INIT=8'h78;
+LUT4 \fifo_inst/rbin_num_next_4_s2  (
+	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/rbin_num [3]),
+	.I3(\fifo_inst/rbin_num [4]),
+	.F(\fifo_inst/rbin_num_next [4])
+);
+defparam \fifo_inst/rbin_num_next_4_s2 .INIT=16'h7F80;
+LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
+	.I0(\fifo_inst/n23_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wbinnext_0_7 )
+);
+defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
+LUT3 \fifo_inst/Equal.wbinnext_2_s3  (
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_2_4 ),
+	.I2(\fifo_inst/Equal.wbin [2]),
+	.F(\fifo_inst/Equal.wbinnext [2])
+);
+defparam \fifo_inst/Equal.wbinnext_2_s3 .INIT=8'hB4;
+LUT3 \fifo_inst/Equal.wbinnext_3_s3  (
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_3_4 ),
+	.I2(\fifo_inst/Equal.wbin [3]),
+	.F(\fifo_inst/Equal.wbinnext [3])
+);
+defparam \fifo_inst/Equal.wbinnext_3_s3 .INIT=8'hB4;
+LUT4 \fifo_inst/Equal.wbinnext_4_s2  (
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_3_4 ),
+	.I2(\fifo_inst/Equal.wbin [3]),
+	.I3(\fifo_inst/wptr [4]),
+	.F(\fifo_inst/Equal.wbinnext [4])
+);
+defparam \fifo_inst/Equal.wbinnext_4_s2 .INIT=16'hBF40;
+LUT4 \fifo_inst/Equal.rgraynext_2_s1  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext_2_4 )
+);
+defparam \fifo_inst/Equal.rgraynext_2_s1 .INIT=16'h4000;
+LUT2 \fifo_inst/Equal.wgraynext_1_s1  (
+	.I0(WrEn),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wgraynext_1_4 )
+);
+defparam \fifo_inst/Equal.wgraynext_1_s1 .INIT=4'h8;
+LUT3 \fifo_inst/Equal.wgraynext_2_s1  (
+	.I0(WrEn),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.F(\fifo_inst/Equal.wgraynext_2_4 )
+);
+defparam \fifo_inst/Equal.wgraynext_2_s1 .INIT=8'h80;
+LUT4 \fifo_inst/Equal.wgraynext_3_s1  (
+	.I0(WrEn),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.I3(\fifo_inst/Equal.wbin [2]),
+	.F(\fifo_inst/Equal.wgraynext_3_4 )
+);
+defparam \fifo_inst/Equal.wgraynext_3_s1 .INIT=16'h8000;
+LUT4 \fifo_inst/wfull_val_s1  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.I3(\fifo_inst/rptr [1]),
+	.F(\fifo_inst/wfull_val_4 )
+);
+defparam \fifo_inst/wfull_val_s1 .INIT=16'h9009;
+LUT4 \fifo_inst/wfull_val_s2  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rptr [2]),
+	.I2(\fifo_inst/wptr [3]),
+	.I3(\fifo_inst/rptr [3]),
+	.F(\fifo_inst/wfull_val_5 )
+);
+defparam \fifo_inst/wfull_val_s2 .INIT=16'h0990;
+LUT3 \fifo_inst/n372_s2  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/wptr [4]),
+	.I2(\fifo_inst/rbin_num [4]),
+	.F(\fifo_inst/n372_5 )
+);
+defparam \fifo_inst/n372_s2 .INIT=8'h14;
+LUT2 \fifo_inst/wfull_val1_s11  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1_16 )
+);
+defparam \fifo_inst/wfull_val1_s11 .INIT=4'h4;
+LUT2 \fifo_inst/Full_s9  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/Full_1 ),
+	.F(\fifo_inst/Full_11 )
+);
+defparam \fifo_inst/Full_s9 .INIT=4'h4;
+LUT4 \fifo_inst/Equal.wbinnext_1_s4  (
+	.I0(Full),
+	.I1(WrEn),
+	.I2(\fifo_inst/Equal.wbin [0]),
+	.I3(\fifo_inst/Equal.wbin [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s4 .INIT=16'hBF40;
+LUT4 \fifo_inst/rbin_num_next_1_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s4 .INIT=16'hBF40;
+LUT3 \fifo_inst/rbin_num_next_0_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next_0_9 )
+);
+defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
+LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
+LUT3 \fifo_inst/rempty_val_s2  (
+	.I0(\fifo_inst/wptr [4]),
+	.I1(\fifo_inst/rbin_num [4]),
+	.I2(\fifo_inst/n131_3 ),
+	.F(\fifo_inst/rempty_val )
+);
+defparam \fifo_inst/rempty_val_s2 .INIT=8'h09;
+DFFP \fifo_inst/reset_r_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [0])
+);
+defparam \fifo_inst/reset_r_0_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_1_s0  (
+	.D(\fifo_inst/reset_w [0]),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [1])
+);
+defparam \fifo_inst/reset_w_1_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [0])
+);
+defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_4_s0  (
+	.D(\fifo_inst/rbin_num_next [4]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [4])
+);
+defparam \fifo_inst/rbin_num_4_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_3_s0  (
+	.D(\fifo_inst/rbin_num_next [3]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [3])
+);
+defparam \fifo_inst/rbin_num_3_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_2_s0  (
+	.D(\fifo_inst/rbin_num_next [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [2])
+);
+defparam \fifo_inst/rbin_num_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_1_s0  (
+	.D(\fifo_inst/rbin_num_next [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [1])
+);
+defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_0_s0  (
+	.D(\fifo_inst/rbin_num_next_0_9 ),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [0])
+);
+defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_3_s0  (
+	.D(\fifo_inst/Equal.rgraynext [3]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [3])
+);
+defparam \fifo_inst/rptr_3_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_2_s0  (
+	.D(\fifo_inst/Equal.rgraynext [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [2])
+);
+defparam \fifo_inst/rptr_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_1_s0  (
+	.D(\fifo_inst/Equal.rgraynext [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [1])
+);
+defparam \fifo_inst/rptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_0_s0  (
+	.D(\fifo_inst/Equal.rgraynext [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [0])
+);
+defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_4_s0  (
+	.D(\fifo_inst/Equal.wbinnext [4]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [4])
+);
+defparam \fifo_inst/wptr_4_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_3_s0  (
+	.D(\fifo_inst/Equal.wgraynext [3]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [3])
+);
+defparam \fifo_inst/wptr_3_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_2_s0  (
+	.D(\fifo_inst/Equal.wgraynext [2]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [2])
+);
+defparam \fifo_inst/wptr_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_1_s0  (
+	.D(\fifo_inst/Equal.wgraynext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [1])
+);
+defparam \fifo_inst/wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_0_s0  (
+	.D(\fifo_inst/Equal.wgraynext [0]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [0])
+);
+defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_3_s0  (
+	.D(\fifo_inst/Equal.wbinnext [3]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [3])
+);
+defparam \fifo_inst/Equal.wbin_3_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_2_s0  (
+	.D(\fifo_inst/Equal.wbinnext [2]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [2])
+);
+defparam \fifo_inst/Equal.wbin_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [1])
+);
+defparam \fifo_inst/Equal.wbin_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_0_s0  (
+	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [0])
+);
+defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
+DFFP \fifo_inst/rempty_val1_s0  (
+	.D(\fifo_inst/rempty_val ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n277_3 ),
+	.Q(\fifo_inst/rempty_val1 )
+);
+defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val1 ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n277_3 ),
+	.Q(Empty)
+);
+defparam \fifo_inst/Empty_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_r_1_s0  (
+	.D(\fifo_inst/reset_r [0]),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [1])
+);
+defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
+DFFC \fifo_inst/wfull_val1_s0  (
+	.D(\fifo_inst/wfull_val ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wfull_val1_2 )
+);
+defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
+DFFP \fifo_inst/wfull_val1_s1  (
+	.D(\fifo_inst/wfull_val ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n372_4 ),
+	.Q(\fifo_inst/wfull_val1_3 )
+);
+defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
+DFFC \fifo_inst/Full_s0  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Full_1_2 )
+);
+defparam \fifo_inst/Full_s0 .INIT=1'b0;
+DFFP \fifo_inst/Full_s1  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n372_4 ),
+	.Q(\fifo_inst/Full_2 )
+);
+defparam \fifo_inst/Full_s1 .INIT=1'b1;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n23_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n27_3 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({GND, GND, GND, GND, GND, GND, GND, GND, Data[23:0]}),
+	.ADA({GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [3:0], GND, VCC, VCC, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, \fifo_inst/rbin_num [3:0], GND, GND, GND, GND, GND}),
+	.DO({\fifo_inst/DO [31:24], Q[23:0]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+ALU \fifo_inst/n128_s0  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
+	.I3(GND),
+	.CIN(GND),
+	.COUT(\fifo_inst/n128_3 ),
+	.SUM(\fifo_inst/n128_1_SUM )
+);
+defparam \fifo_inst/n128_s0 .ALU_MODE=3;
+ALU \fifo_inst/n129_s0  (
+	.I0(\fifo_inst/wptr [1]),
+	.I1(\fifo_inst/rptr [1]),
+	.I3(GND),
+	.CIN(\fifo_inst/n128_3 ),
+	.COUT(\fifo_inst/n129_3 ),
+	.SUM(\fifo_inst/n129_1_SUM )
+);
+defparam \fifo_inst/n129_s0 .ALU_MODE=3;
+ALU \fifo_inst/n130_s0  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rptr [2]),
+	.I3(GND),
+	.CIN(\fifo_inst/n129_3 ),
+	.COUT(\fifo_inst/n130_3 ),
+	.SUM(\fifo_inst/n130_1_SUM )
+);
+defparam \fifo_inst/n130_s0 .ALU_MODE=3;
+ALU \fifo_inst/n131_s0  (
+	.I0(\fifo_inst/wptr [3]),
+	.I1(\fifo_inst/rptr [3]),
+	.I3(GND),
+	.CIN(\fifo_inst/n130_3 ),
+	.COUT(\fifo_inst/n131_3 ),
+	.SUM(\fifo_inst/n131_1_SUM )
+);
+defparam \fifo_inst/n131_s0 .ALU_MODE=3;
+INV \fifo_inst/n4_s2  (
+	.I(RdClk),
+	.O(\fifo_inst/n4_6 )
+);
+INV \fifo_inst/n9_s2  (
+	.I(WrClk),
+	.O(\fifo_inst/n9_6 )
+);
+endmodule

src/src/FifoCtrl/FifoLMX/FifoLMX_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Wed Apr 24 12:23:21 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoLMX your_instance_name(
+		.Data(Data_i), //input [23:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [23:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/FifoCtrl/FifoLMX/temp/FIFOHS/FIFOHS.prj

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
+    <FileList>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/temp/FIFOHS"/>
+        <Option type="output_file" value="FifoLMX.vg"/>
+        <Option type="output_template" value="FifoLMX_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/FifoCtrl/FifoLMX/temp/FIFOHS/FifoLMX.log

@@ -0,0 +1,45 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoLMX'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+NOTE  (EX0101) : Current top module is "FifoLMX"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\temp\FIFOHS\FifoLMX.vg" completed
+Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\temp\FIFOHS\FifoLMX_tmp.v" completed
+[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\temp\FIFOHS\FifoLMX_syn.rpt.html" completed
+GowinSynthesis finish

src/src/FifoCtrl/FifoLMX/temp/FIFOHS/FifoLMX.vg

@@ -0,0 +1,283 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Wed Apr 24 12:23:21 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=11824)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+h0CJ2e7b8jmTGvIdzhP2nVeDnFJTEUzP9g==
+`pragma protect end_protected
+module FifoLMX (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [23:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [23:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoLMX  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[23:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[23:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoLMX */

src/src/FifoCtrl/FifoLMX/temp/FIFOHS/FifoLMX_syn_resource.html

@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoLMX (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">28</td>
+<td align = "center">4</td>
+<td align = "center">39</td>
+<td align = "center">-</td>
+<td align = "center">1</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/FifoCtrl/FifoLMX/temp/FIFOHS/FifoLMX_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoLMX" Register="28" Alu="4" Lut="39" Bsram="1" T_Register="28(28)" T_Alu="4(4)" T_Lut="39(39)" T_Bsram="1(1)"/>

src/src/FifoCtrl/FifoLMX/temp/FIFOHS/FifoLMX_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Wed Apr 24 12:23:21 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoLMX your_instance_name(
+		.Data(Data_i), //input [23:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [23:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/FifoCtrl/FifoLMX/temp/FIFOHS/fifo_define.v

@@ -0,0 +1,4 @@
+`define module_name FifoLMX
+`define EBR_BASED
+`define En_Reset
+`define Reset_Synchronization

src/src/FifoCtrl/FifoLMX/temp/FIFOHS/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 16;
+parameter ASIZE = 4;
+parameter WDSIZE = 24;
+parameter RDEPTH = 16;
+parameter RASIZE = 4;
+parameter RDSIZE = 24;

src/src/FifoCtrl/FifoLMX/temp/FIFOHS/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/FifoCtrl/FifoMax2870/FifoMax2870.ipc

@@ -0,0 +1,35 @@
+[General]
+ipc_version=4
+file=FifoMax2870
+module=FifoMax2870
+target_device=gw1n9-014
+type=fifo_hs
+version=1.0
+
+[Config]
+AlmostEmptyFlag=false
+AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter
+AlmostFullFlag=false
+AlmostFullFlagItem=Full_Single Threshold Constant Parameter
+BSRAM=true
+ControlledByRdEn=false
+ECCSelected=false
+EmptyClear=1
+EmptySet=1
+EnReset=true
+FirstWordFallThrough=false
+FullClear=1
+FullSet=1
+LANG=0
+OutputRegistersSelected=false
+REG=false
+ReadDataNum=false
+ReadDataWidth=32
+ReadDepth=4
+ResetSynchronization=true
+SSRAM=false
+StandardFIFO=true
+Synthesis_tool=GowinSynthesis
+WriteDataNum=false
+WriteDataWidth=32
+WriteDepth=4

src/src/FifoCtrl/FifoMax2870/FifoMax2870.v

@@ -0,0 +1,214 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Wed Apr 24 12:27:38 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
+SddClgFUnFcYNNNFe/GREt+yYcvvDamaqjoPQfIWM0LA235wZ3uxWgdlVE6ogq3z8rJcDNh2Vk6n
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7888)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+`pragma protect end_protected
+module FifoMax2870 (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [31:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [31:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoMax2870  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[31:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[31:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoMax2870 */

src/src/FifoCtrl/FifoMax2870/FifoMax2870.vo

@@ -0,0 +1,438 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Post-PnR Simulation Model file
+//Tool Version: V1.9.9.02
+//Created Time: Wed Apr 24 12:27:39 2024
+
+`timescale 100 ps/100 ps
+module FifoMax2870(
+	Data,
+	Reset,
+	WrClk,
+	RdClk,
+	WrEn,
+	RdEn,
+	Q,
+	Empty,
+	Full
+);
+input [31:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [31:0] Q;
+output Empty;
+output Full;
+wire [31:0] Data;
+wire Empty;
+wire Full;
+wire GND;
+wire [31:0] Q;
+wire RdClk;
+wire RdEn;
+wire Reset;
+wire VCC;
+wire WrClk;
+wire WrEn;
+wire \fifo_inst/n21_5 ;
+wire \fifo_inst/n25_3 ;
+wire \fifo_inst/n257_3 ;
+wire \fifo_inst/wfull_val1 ;
+wire \fifo_inst/wfull_val1_0 ;
+wire \fifo_inst/Full_1 ;
+wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/Equal.wgraynext_1_4 ;
+wire \fifo_inst/wfull_val_4 ;
+wire \fifo_inst/wfull_val_5 ;
+wire \fifo_inst/n336_6 ;
+wire \fifo_inst/wfull_val ;
+wire \fifo_inst/rbin_num_next_0_9 ;
+wire \fifo_inst/rempty_val ;
+wire \fifo_inst/rempty_val1 ;
+wire \fifo_inst/wfull_val1_2 ;
+wire \fifo_inst/wfull_val1_3 ;
+wire \fifo_inst/Full_1_2 ;
+wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n156_1_SUM ;
+wire \fifo_inst/n156_3 ;
+wire \fifo_inst/n157_1_SUM ;
+wire \fifo_inst/n157_3 ;
+wire \fifo_inst/n4_6 ;
+wire \fifo_inst/n9_6 ;
+wire [1:0] \fifo_inst/Equal.rgraynext ;
+wire [1:0] \fifo_inst/Equal.wgraynext ;
+wire [2:1] \fifo_inst/rbin_num_next ;
+wire [2:1] \fifo_inst/Equal.wbinnext ;
+wire [1:0] \fifo_inst/reset_r ;
+wire [1:0] \fifo_inst/reset_w ;
+wire [2:0] \fifo_inst/rbin_num ;
+wire [1:0] \fifo_inst/rptr ;
+wire [2:0] \fifo_inst/wptr ;
+wire [1:0] \fifo_inst/Equal.wbin ;
+VCC VCC_cZ (
+  .V(VCC)
+);
+GND GND_cZ (
+  .G(GND)
+);
+GSR GSR (
+	.GSRI(VCC)
+);
+LUT4 \fifo_inst/n21_s1  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(WrEn),
+	.F(\fifo_inst/n21_5 )
+);
+defparam \fifo_inst/n21_s1 .INIT=16'h5300;
+LUT2 \fifo_inst/n25_s0  (
+	.I0(Empty),
+	.I1(RdEn),
+	.F(\fifo_inst/n25_3 )
+);
+defparam \fifo_inst/n25_s0 .INIT=4'h4;
+LUT4 \fifo_inst/Equal.rgraynext_1_s0  (
+	.I0(\fifo_inst/n25_3 ),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [2]),
+	.F(\fifo_inst/Equal.rgraynext [1])
+);
+defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=16'h07F8;
+LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.F(\fifo_inst/Equal.wgraynext [0])
+);
+defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
+LUT4 \fifo_inst/Equal.wgraynext_1_s0  (
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_1_4 ),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.I3(\fifo_inst/wptr [2]),
+	.F(\fifo_inst/Equal.wgraynext [1])
+);
+defparam \fifo_inst/Equal.wgraynext_1_s0 .INIT=16'h0BF4;
+LUT2 \fifo_inst/n257_s0  (
+	.I0(\fifo_inst/rempty_val ),
+	.I1(\fifo_inst/reset_r [1]),
+	.F(\fifo_inst/n257_3 )
+);
+defparam \fifo_inst/n257_s0 .INIT=4'hE;
+LUT3 \fifo_inst/wfull_val1_s9  (
+	.I0(\fifo_inst/wfull_val1_3 ),
+	.I1(\fifo_inst/wfull_val1_2 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1 )
+);
+defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
+LUT4 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val_4 ),
+	.I1(\fifo_inst/wfull_val_5 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.I3(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/wfull_val1_0 )
+);
+defparam \fifo_inst/wfull_val1_s10 .INIT=16'h00F8;
+LUT3 \fifo_inst/Full_d_s  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.F(Full)
+);
+defparam \fifo_inst/Full_d_s .INIT=8'hAC;
+LUT4 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/wfull_val_4 ),
+	.I1(\fifo_inst/wfull_val_5 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/Full_1 )
+);
+defparam \fifo_inst/Full_s8 .INIT=16'h00F8;
+LUT4 \fifo_inst/rbin_num_next_2_s2  (
+	.I0(\fifo_inst/n25_3 ),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [2]),
+	.F(\fifo_inst/rbin_num_next [2])
+);
+defparam \fifo_inst/rbin_num_next_2_s2 .INIT=16'h7F80;
+LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wbinnext_0_7 )
+);
+defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
+LUT4 \fifo_inst/Equal.wbinnext_2_s2  (
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_1_4 ),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.I3(\fifo_inst/wptr [2]),
+	.F(\fifo_inst/Equal.wbinnext [2])
+);
+defparam \fifo_inst/Equal.wbinnext_2_s2 .INIT=16'hBF40;
+LUT2 \fifo_inst/Equal.wgraynext_1_s1  (
+	.I0(WrEn),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wgraynext_1_4 )
+);
+defparam \fifo_inst/Equal.wgraynext_1_s1 .INIT=4'h8;
+LUT2 \fifo_inst/wfull_val_s1  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rbin_num [2]),
+	.F(\fifo_inst/wfull_val_4 )
+);
+defparam \fifo_inst/wfull_val_s1 .INIT=4'h6;
+LUT4 \fifo_inst/wfull_val_s2  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.I3(\fifo_inst/rptr [1]),
+	.F(\fifo_inst/wfull_val_5 )
+);
+defparam \fifo_inst/wfull_val_s2 .INIT=16'h0990;
+LUT4 \fifo_inst/Equal.wbinnext_1_s4  (
+	.I0(Full),
+	.I1(WrEn),
+	.I2(\fifo_inst/Equal.wbin [0]),
+	.I3(\fifo_inst/Equal.wbin [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s4 .INIT=16'hBF40;
+LUT4 \fifo_inst/n336_s2  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/reset_w [1]),
+	.I3(\fifo_inst/wfull_val_5 ),
+	.F(\fifo_inst/n336_6 )
+);
+defparam \fifo_inst/n336_s2 .INIT=16'h0600;
+LUT3 \fifo_inst/wfull_val_s3  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/wfull_val_5 ),
+	.F(\fifo_inst/wfull_val )
+);
+defparam \fifo_inst/wfull_val_s3 .INIT=8'h60;
+LUT4 \fifo_inst/rbin_num_next_1_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s4 .INIT=16'hBF40;
+LUT3 \fifo_inst/rbin_num_next_0_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next_0_9 )
+);
+defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
+LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
+LUT3 \fifo_inst/rempty_val_s2  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/n157_3 ),
+	.F(\fifo_inst/rempty_val )
+);
+defparam \fifo_inst/rempty_val_s2 .INIT=8'h09;
+DFFP \fifo_inst/reset_r_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [0])
+);
+defparam \fifo_inst/reset_r_0_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_1_s0  (
+	.D(\fifo_inst/reset_w [0]),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [1])
+);
+defparam \fifo_inst/reset_w_1_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [0])
+);
+defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_2_s0  (
+	.D(\fifo_inst/rbin_num_next [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [2])
+);
+defparam \fifo_inst/rbin_num_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_1_s0  (
+	.D(\fifo_inst/rbin_num_next [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [1])
+);
+defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_0_s0  (
+	.D(\fifo_inst/rbin_num_next_0_9 ),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [0])
+);
+defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_1_s0  (
+	.D(\fifo_inst/Equal.rgraynext [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [1])
+);
+defparam \fifo_inst/rptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_0_s0  (
+	.D(\fifo_inst/Equal.rgraynext [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [0])
+);
+defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_2_s0  (
+	.D(\fifo_inst/Equal.wbinnext [2]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [2])
+);
+defparam \fifo_inst/wptr_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_1_s0  (
+	.D(\fifo_inst/Equal.wgraynext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [1])
+);
+defparam \fifo_inst/wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_0_s0  (
+	.D(\fifo_inst/Equal.wgraynext [0]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [0])
+);
+defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [1])
+);
+defparam \fifo_inst/Equal.wbin_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_0_s0  (
+	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [0])
+);
+defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
+DFFP \fifo_inst/rempty_val1_s0  (
+	.D(\fifo_inst/rempty_val ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n257_3 ),
+	.Q(\fifo_inst/rempty_val1 )
+);
+defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val1 ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n257_3 ),
+	.Q(Empty)
+);
+defparam \fifo_inst/Empty_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_r_1_s0  (
+	.D(\fifo_inst/reset_r [0]),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [1])
+);
+defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
+DFFC \fifo_inst/wfull_val1_s0  (
+	.D(\fifo_inst/wfull_val ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wfull_val1_2 )
+);
+defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
+DFFP \fifo_inst/wfull_val1_s1  (
+	.D(\fifo_inst/wfull_val ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n336_6 ),
+	.Q(\fifo_inst/wfull_val1_3 )
+);
+defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
+DFFC \fifo_inst/Full_s0  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Full_1_2 )
+);
+defparam \fifo_inst/Full_s0 .INIT=1'b0;
+DFFP \fifo_inst/Full_s1  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n336_6 ),
+	.Q(\fifo_inst/Full_2 )
+);
+defparam \fifo_inst/Full_s1 .INIT=1'b1;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n21_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n25_3 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({Data[31:0]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [1:0], GND, VCC, VCC, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [1:0], GND, GND, GND, GND, GND}),
+	.DO({Q[31:0]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+ALU \fifo_inst/n156_s0  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
+	.I3(GND),
+	.CIN(GND),
+	.COUT(\fifo_inst/n156_3 ),
+	.SUM(\fifo_inst/n156_1_SUM )
+);
+defparam \fifo_inst/n156_s0 .ALU_MODE=3;
+ALU \fifo_inst/n157_s0  (
+	.I0(\fifo_inst/wptr [1]),
+	.I1(\fifo_inst/rptr [1]),
+	.I3(GND),
+	.CIN(\fifo_inst/n156_3 ),
+	.COUT(\fifo_inst/n157_3 ),
+	.SUM(\fifo_inst/n157_1_SUM )
+);
+defparam \fifo_inst/n157_s0 .ALU_MODE=3;
+INV \fifo_inst/n4_s2  (
+	.I(RdClk),
+	.O(\fifo_inst/n4_6 )
+);
+INV \fifo_inst/n9_s2  (
+	.I(WrClk),
+	.O(\fifo_inst/n9_6 )
+);
+endmodule

src/src/FifoCtrl/FifoMax2870/FifoMax2870_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Wed Apr 24 12:27:38 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoMax2870 your_instance_name(
+		.Data(Data_i), //input [31:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [31:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/FifoCtrl/FifoMax2870/temp/FIFOHS/FIFOHS.prj

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
+    <FileList>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/FifoMax2870/fifo_hs/temp/FIFOHS"/>
+        <Option type="output_file" value="FifoMax2870.vg"/>
+        <Option type="output_template" value="FifoMax2870_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/FifoCtrl/FifoMax2870/temp/FIFOHS/FifoMax2870.log

@@ -0,0 +1,45 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoMax2870'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+NOTE  (EX0101) : Current top module is "FifoMax2870"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\fifo_hs\temp\FIFOHS\FifoMax2870.vg" completed
+Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\fifo_hs\temp\FIFOHS\FifoMax2870_tmp.v" completed
+[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\fifo_hs\temp\FIFOHS\FifoMax2870_syn.rpt.html" completed
+GowinSynthesis finish

src/src/FifoCtrl/FifoMax2870/temp/FIFOHS/FifoMax2870.vg

@@ -0,0 +1,214 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Wed Apr 24 12:27:38 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
+SddClgFUnFcYNNNFe/GREt+yYcvvDamaqjoPQfIWM0LA235wZ3uxWgdlVE6ogq3z8rJcDNh2Vk6n
+WmtkYDkltTV3ZakkUI9hoihHOZ0kEEg0ENfIBQY7LI/v1uOaRbVBDT7xONJxBZWqblaKX8JD7gl9
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+C5SLMTV3Jrp7q+HDrwaqg3pSNYd+cDEDG/p1RQ==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7888)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+6E4yevchwVEOhr/h4l1dGiLo+4R65Q==
+`pragma protect end_protected
+module FifoMax2870 (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [31:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [31:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoMax2870  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[31:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[31:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoMax2870 */

src/src/FifoCtrl/FifoMax2870/temp/FIFOHS/FifoMax2870_syn_resource.html

@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoMax2870 (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">20</td>
+<td align = "center">2</td>
+<td align = "center">25</td>
+<td align = "center">-</td>
+<td align = "center">1</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/FifoCtrl/FifoMax2870/temp/FIFOHS/FifoMax2870_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoMax2870" Register="20" Alu="2" Lut="25" Bsram="1" T_Register="20(20)" T_Alu="2(2)" T_Lut="25(25)" T_Bsram="1(1)"/>

src/src/FifoCtrl/FifoMax2870/temp/FIFOHS/FifoMax2870_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Wed Apr 24 12:27:38 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoMax2870 your_instance_name(
+		.Data(Data_i), //input [31:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [31:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/FifoCtrl/FifoMax2870/temp/FIFOHS/fifo_define.v

@@ -0,0 +1,4 @@
+`define module_name FifoMax2870
+`define EBR_BASED
+`define En_Reset
+`define Reset_Synchronization

src/src/FifoCtrl/FifoMax2870/temp/FIFOHS/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 4;
+parameter ASIZE = 2;
+parameter WDSIZE = 32;
+parameter RDEPTH = 4;
+parameter RASIZE = 2;
+parameter RDSIZE = 32;

src/src/FifoCtrl/FifoMax2870/temp/FIFOHS/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/FifoCtrl/FifoShiftReg/FifoShiftReg.ipc

@@ -0,0 +1,35 @@
+[General]
+ipc_version=4
+file=FifoShiftReg
+module=FifoShiftReg
+target_device=gw1n9-014
+type=fifo_hs
+version=1.0
+
+[Config]
+AlmostEmptyFlag=false
+AlmostEmptyFlagItem=Empty_Single Threshold Constant Parameter
+AlmostFullFlag=false
+AlmostFullFlagItem=Full_Single Threshold Constant Parameter
+BSRAM=true
+ControlledByRdEn=false
+ECCSelected=false
+EmptyClear=1
+EmptySet=1
+EnReset=true
+FirstWordFallThrough=false
+FullClear=1
+FullSet=1
+LANG=0
+OutputRegistersSelected=false
+REG=false
+ReadDataNum=false
+ReadDataWidth=8
+ReadDepth=2
+ResetSynchronization=true
+SSRAM=false
+StandardFIFO=true
+Synthesis_tool=GowinSynthesis
+WriteDataNum=false
+WriteDataWidth=8
+WriteDepth=2

src/src/FifoCtrl/FifoShiftReg/FifoShiftReg.v

@@ -0,0 +1,178 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Wed Apr 24 14:54:26 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
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+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=5840)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+sV7+/rQKRBAMCUDVtSYhFepC2389xlMHIWg=
+`pragma protect end_protected
+module FifoShiftReg (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [7:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [7:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoShiftReg  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[7:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[7:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoShiftReg */

src/src/FifoCtrl/FifoShiftReg/FifoShiftReg.vo

@@ -0,0 +1,331 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Post-PnR Simulation Model file
+//Tool Version: V1.9.9.02
+//Created Time: Wed Apr 24 14:54:26 2024
+
+`timescale 100 ps/100 ps
+module FifoShiftReg(
+	Data,
+	Reset,
+	WrClk,
+	RdClk,
+	WrEn,
+	RdEn,
+	Q,
+	Empty,
+	Full
+);
+input [7:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [7:0] Q;
+output Empty;
+output Full;
+wire [7:0] Data;
+wire Empty;
+wire Full;
+wire GND;
+wire [7:0] Q;
+wire RdClk;
+wire RdEn;
+wire Reset;
+wire VCC;
+wire WrClk;
+wire WrEn;
+wire \fifo_inst/n20_5 ;
+wire \fifo_inst/n24_3 ;
+wire \fifo_inst/n135_3 ;
+wire \fifo_inst/n178_4 ;
+wire \fifo_inst/rempty_val ;
+wire \fifo_inst/wfull_val_7 ;
+wire \fifo_inst/wfull_val1 ;
+wire \fifo_inst/wfull_val1_0 ;
+wire \fifo_inst/Full_1 ;
+wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/rbin_num_next_0_9 ;
+wire \fifo_inst/rempty_val1 ;
+wire \fifo_inst/wfull_val1_2 ;
+wire \fifo_inst/wfull_val1_3 ;
+wire \fifo_inst/Full_1_2 ;
+wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n4_6 ;
+wire \fifo_inst/n9_6 ;
+wire [0:0] \fifo_inst/Equal.wgraynext ;
+wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:1] \fifo_inst/rbin_num_next ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
+wire [1:0] \fifo_inst/reset_r ;
+wire [1:0] \fifo_inst/reset_w ;
+wire [1:0] \fifo_inst/rbin_num ;
+wire [0:0] \fifo_inst/rptr ;
+wire [1:0] \fifo_inst/wptr ;
+wire [0:0] \fifo_inst/Equal.wbin ;
+wire [31:8] \fifo_inst/DO ;
+VCC VCC_cZ (
+  .V(VCC)
+);
+GND GND_cZ (
+  .G(GND)
+);
+GSR GSR (
+	.GSRI(VCC)
+);
+LUT4 \fifo_inst/n20_s1  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.I3(WrEn),
+	.F(\fifo_inst/n20_5 )
+);
+defparam \fifo_inst/n20_s1 .INIT=16'h5300;
+LUT2 \fifo_inst/n24_s0  (
+	.I0(Empty),
+	.I1(RdEn),
+	.F(\fifo_inst/n24_3 )
+);
+defparam \fifo_inst/n24_s0 .INIT=4'h4;
+LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wgraynext [0])
+);
+defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
+LUT2 \fifo_inst/n135_s0  (
+	.I0(\fifo_inst/rempty_val ),
+	.I1(\fifo_inst/reset_r [1]),
+	.F(\fifo_inst/n135_3 )
+);
+defparam \fifo_inst/n135_s0 .INIT=4'hE;
+LUT2 \fifo_inst/n178_s1  (
+	.I0(\fifo_inst/reset_w [1]),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.F(\fifo_inst/n178_4 )
+);
+defparam \fifo_inst/n178_s1 .INIT=4'h4;
+LUT4 \fifo_inst/rempty_val_s3  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rempty_val )
+);
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h9009;
+LUT4 \fifo_inst/wfull_val_s3  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rptr [0]),
+	.F(\fifo_inst/wfull_val_7 )
+);
+defparam \fifo_inst/wfull_val_s3 .INIT=16'h1428;
+LUT3 \fifo_inst/wfull_val1_s9  (
+	.I0(\fifo_inst/wfull_val1_3 ),
+	.I1(\fifo_inst/wfull_val1_2 ),
+	.I2(\fifo_inst/wfull_val1_0 ),
+	.F(\fifo_inst/wfull_val1 )
+);
+defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
+LUT3 \fifo_inst/wfull_val1_s10  (
+	.I0(\fifo_inst/wfull_val1_0 ),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/wfull_val1_0 )
+);
+defparam \fifo_inst/wfull_val1_s10 .INIT=8'h0E;
+LUT3 \fifo_inst/Full_d_s  (
+	.I0(\fifo_inst/Full_2 ),
+	.I1(\fifo_inst/Full_1_2 ),
+	.I2(\fifo_inst/Full_1 ),
+	.F(Full)
+);
+defparam \fifo_inst/Full_d_s .INIT=8'hAC;
+LUT3 \fifo_inst/Full_s8  (
+	.I0(\fifo_inst/Full_1 ),
+	.I1(\fifo_inst/wfull_val_7 ),
+	.I2(\fifo_inst/reset_w [1]),
+	.F(\fifo_inst/Full_1 )
+);
+defparam \fifo_inst/Full_s8 .INIT=8'h0E;
+LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wbinnext_0_7 )
+);
+defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
+LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
+LUT4 \fifo_inst/rbin_num_next_1_s3  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s3 .INIT=16'hBF40;
+LUT3 \fifo_inst/rbin_num_next_0_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next_0_9 )
+);
+defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
+LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
+DFFP \fifo_inst/reset_r_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [0])
+);
+defparam \fifo_inst/reset_r_0_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_1_s0  (
+	.D(\fifo_inst/reset_w [0]),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [1])
+);
+defparam \fifo_inst/reset_w_1_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_w_0_s0  (
+	.D(GND),
+	.CLK(\fifo_inst/n9_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_w [0])
+);
+defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
+DFFC \fifo_inst/rbin_num_1_s0  (
+	.D(\fifo_inst/rbin_num_next [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [1])
+);
+defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/rbin_num_0_s0  (
+	.D(\fifo_inst/rbin_num_next_0_9 ),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rbin_num [0])
+);
+defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/rptr_0_s0  (
+	.D(\fifo_inst/Equal.rgraynext [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/rptr [0])
+);
+defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_1_s0  (
+	.D(\fifo_inst/Equal.wbinnext [1]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [1])
+);
+defparam \fifo_inst/wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/wptr_0_s0  (
+	.D(\fifo_inst/Equal.wgraynext [0]),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wptr [0])
+);
+defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.wbin_0_s0  (
+	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Equal.wbin [0])
+);
+defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
+DFFP \fifo_inst/rempty_val1_s0  (
+	.D(\fifo_inst/rempty_val ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n135_3 ),
+	.Q(\fifo_inst/rempty_val1 )
+);
+defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val1 ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n135_3 ),
+	.Q(Empty)
+);
+defparam \fifo_inst/Empty_s0 .INIT=1'b1;
+DFFP \fifo_inst/reset_r_1_s0  (
+	.D(\fifo_inst/reset_r [0]),
+	.CLK(\fifo_inst/n4_6 ),
+	.PRESET(Reset),
+	.Q(\fifo_inst/reset_r [1])
+);
+defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
+DFFC \fifo_inst/wfull_val1_s0  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/wfull_val1_2 )
+);
+defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
+DFFP \fifo_inst/wfull_val1_s1  (
+	.D(\fifo_inst/wfull_val_7 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n178_4 ),
+	.Q(\fifo_inst/wfull_val1_3 )
+);
+defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
+DFFC \fifo_inst/Full_s0  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.CLEAR(\fifo_inst/reset_w [1]),
+	.Q(\fifo_inst/Full_1_2 )
+);
+defparam \fifo_inst/Full_s0 .INIT=1'b0;
+DFFP \fifo_inst/Full_s1  (
+	.D(\fifo_inst/wfull_val1 ),
+	.CLK(WrClk),
+	.PRESET(\fifo_inst/n178_4 ),
+	.Q(\fifo_inst/Full_2 )
+);
+defparam \fifo_inst/Full_s1 .INIT=1'b1;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n20_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n24_3 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[7:0]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND}),
+	.DO({\fifo_inst/DO [31:8], Q[7:0]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=8;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=8;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
+INV \fifo_inst/n4_s2  (
+	.I(RdClk),
+	.O(\fifo_inst/n4_6 )
+);
+INV \fifo_inst/n9_s2  (
+	.I(WrClk),
+	.O(\fifo_inst/n9_6 )
+);
+endmodule

src/src/FifoCtrl/FifoShiftReg/FifoShiftReg_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Wed Apr 24 14:54:26 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoShiftReg your_instance_name(
+		.Data(Data_i), //input [7:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [7:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/FifoCtrl/FifoShiftReg/temp/FIFOHS/FIFOHS.prj

@@ -0,0 +1,20 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE gowin-synthesis-project>
+<Project>
+    <Version>beta</Version>
+    <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
+    <FileList>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+    </FileList>
+    <OptionList>
+        <Option type="disable_insert_pad" value="1"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/FifoShiftReg/temp/FIFOHS"/>
+        <Option type="output_file" value="FifoShiftReg.vg"/>
+        <Option type="output_template" value="FifoShiftReg_tmp.v"/>
+        <Option type="ram_balance" value="1"/>
+        <Option type="ram_rw_check" value="1"/>
+        <Option type="verilog_language" value="sysv-2017"/>
+    </OptionList>
+</Project>

src/src/FifoCtrl/FifoShiftReg/temp/FIFOHS/FifoShiftReg.log

@@ -0,0 +1,45 @@
+GowinSynthesis start
+Running parser ...
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoShiftReg'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+NOTE  (EX0101) : Current top module is "FifoShiftReg"
+[5%] Running netlist conversion ...
+Running device independent optimization ...
+[10%] Optimizing Phase 0 completed
+[15%] Optimizing Phase 1 completed
+[25%] Optimizing Phase 2 completed
+Running inference ...
+[30%] Inferring Phase 0 completed
+[40%] Inferring Phase 1 completed
+[50%] Inferring Phase 2 completed
+[55%] Inferring Phase 3 completed
+Running technical mapping ...
+[60%] Tech-Mapping Phase 0 completed
+[65%] Tech-Mapping Phase 1 completed
+[75%] Tech-Mapping Phase 2 completed
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0101) : The netlist is not one directed acyclic graph
+[80%] Tech-Mapping Phase 3 completed
+[90%] Tech-Mapping Phase 4 completed
+[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoShiftReg\temp\FIFOHS\FifoShiftReg.vg" completed
+Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoShiftReg\temp\FIFOHS\FifoShiftReg_tmp.v" completed
+[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoShiftReg\temp\FIFOHS\FifoShiftReg_syn.rpt.html" completed
+GowinSynthesis finish

src/src/FifoCtrl/FifoShiftReg/temp/FIFOHS/FifoShiftReg.vg

@@ -0,0 +1,178 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9.02"
+//Wed Apr 24 14:54:26 2024
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
+ri3/2MaA3o2gl+75xxjukQm5K0YP3OMlgHDQSNqiqnaALpa036lSBs3wfql9tudIILGRZvaEM5nF
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+TCiBKnj8AtxX/hjF5wT9nW2SWG6/F2zIdPpJqw==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=5840)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
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+sV7+/rQKRBAMCUDVtSYhFepC2389xlMHIWg=
+`pragma protect end_protected
+module FifoShiftReg (
+  Data,
+  Reset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Q,
+  Empty,
+  Full
+)
+;
+input [7:0] Data;
+input Reset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output [7:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.FifoShiftReg  fifo_inst (
+    .Reset(Reset),
+    .RdClk(RdClk),
+    .WrClk(WrClk),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[7:0]),
+    .Empty(Empty),
+    .Full(Full),
+    .Q(Q[7:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* FifoShiftReg */

src/src/FifoCtrl/FifoShiftReg/temp/FIFOHS/FifoShiftReg_syn_resource.html

@@ -0,0 +1,46 @@
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
+<html>
+<head>
+<title>Hierarchy Module Resource</title>
+<style type="text/css">
+body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
+div#main_wrapper{ width: 100%; }
+h1 {text-align: center; }
+h1 {margin-top: 36px; }
+table, th, td { border: 1px solid #aaa; }
+table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
+th, td { align = "center"; padding: 5px 2px 5px 5px; }
+th { color: #fff; font-weight: bold; background-color: #0084ff; }
+table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
+</style>
+</head>
+<body>
+<div id="main_wrapper">
+<div id="content">
+<h1>Hierarchy Module Resource</h1>
+<table>
+<tr>
+<th class="label">MODULE NAME</th>
+<th class="label">REG NUMBER</th>
+<th class="label">ALU NUMBER</th>
+<th class="label">LUT NUMBER</th>
+<th class="label">DSP NUMBER</th>
+<th class="label">BSRAM NUMBER</th>
+<th class="label">SSRAM NUMBER</th>
+<th class="label">ROM16 NUMBER</th>
+</tr>
+<tr>
+<td class="label">FifoShiftReg (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">16</td>
+<td align = "center">-</td>
+<td align = "center">18</td>
+<td align = "center">-</td>
+<td align = "center">1</td>
+<td align = "center">-</td>
+<td align = "center">-</td>
+</tr>
+</table>
+</div><!-- content -->
+</div><!-- main_wrapper -->
+</body>
+</html>

src/src/FifoCtrl/FifoShiftReg/temp/FIFOHS/FifoShiftReg_syn_rsc.xml

@@ -0,0 +1,2 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Module name="FifoShiftReg" Register="16" Lut="18" Bsram="1" T_Register="16(16)" T_Lut="18(18)" T_Bsram="1(1)"/>

src/src/FifoCtrl/FifoShiftReg/temp/FIFOHS/FifoShiftReg_tmp.v

@@ -0,0 +1,24 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.9.02
+//Part Number: GW1N-LV9PG256C6/I5
+//Device: GW1N-
+//Created Time: Wed Apr 24 14:54:26 2024
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+	FifoShiftReg your_instance_name(
+		.Data(Data_i), //input [7:0] Data
+		.Reset(Reset_i), //input Reset
+		.WrClk(WrClk_i), //input WrClk
+		.RdClk(RdClk_i), //input RdClk
+		.WrEn(WrEn_i), //input WrEn
+		.RdEn(RdEn_i), //input RdEn
+		.Q(Q_o), //output [7:0] Q
+		.Empty(Empty_o), //output Empty
+		.Full(Full_o) //output Full
+	);
+
+//--------Copy end-------------------

src/src/FifoCtrl/FifoShiftReg/temp/FIFOHS/fifo_define.v

@@ -0,0 +1,4 @@
+`define module_name FifoShiftReg
+`define EBR_BASED
+`define En_Reset
+`define Reset_Synchronization

src/src/FifoCtrl/FifoShiftReg/temp/FIFOHS/fifo_parameter.v

@@ -0,0 +1,6 @@
+parameter WDEPTH = 2;
+parameter ASIZE = 1;
+parameter WDSIZE = 8;
+parameter RDEPTH = 2;
+parameter RASIZE = 1;
+parameter RDSIZE = 8;

src/src/FifoCtrl/FifoShiftReg/temp/FIFOHS/project.ini

@@ -0,0 +1 @@
+RESOURCE_CHECK=false

src/src/Top/TopSbTmsg.v

@@ -59,15 +59,75 @@ module TopSbTmsg
 
 //================================================================================
 //  REG/WIRE
-
-	wire clk360;
+	wire gclk;
 	wire clk100;
-	wire clk75;
-	wire clk50;
-	wire clk40;
-	wire clk20;
-	wire clk30;
 	wire clk5;
+	wire clk20;
+	wire clk50;
+	wire clk26dot25;
+	wire clk60;
+
+	//FifoLMX
+	wire [23:0] dataFromLmxFifo;
+	wire [23:0] dataFromLmxFifoCtrl;
+	wire readEnLmx;
+	wire writeEnLmx;
+	wire lmxFifoEmpty;
+	wire lmxFifoFull;
+	wire valRdDataLMX;
+
+	//FifoDDS
+	wire [63:0] dataFromDdsFifo;
+	wire [63:0] dataFromDdsFifoCtrl;
+	wire readEnDds;
+	wire writeEnDds;
+	wire ddsFifoEmpty;
+	wire ddsFifoFull;
+	wire valRdDataDDS;
+
+	//FifoPot
+	wire [15:0] dataFromPotFifo;
+	wire [15:0] dataFromPotFifoCtrl;
+	wire readEnPot;
+	wire writeEnPot;
+	wire potFifoEmpty;
+	wire potFifoFull;
+	wire valRdDataPOT;
+
+	//FifoDAC
+	wire [15:0] dataFromDacFifo;
+	wire [15:0] dataFromDacFifoCtrl;
+	wire readEnDac;
+	wire writeEnDac;
+	wire dacFifoEmpty;
+	wire dacFifoFull;
+
+	//FifoAtt
+	wire [15:0] dataFromAttFifo;
+	wire [15:0] dataFromAttFifoCtrl;
+	wire readEnAtt;
+	wire writeEnAtt;
+	wire attFifoEmpty;
+	wire attFifoFull;
+	wire valRdDataATT;
+
+	//FifoShReg
+	wire [7:0] dataFromShRegFifo;
+	wire [7:0] dataFromShRegFifoCtrl;
+	wire readEnShReg;
+	wire writeEnShReg;
+	wire shRegFifoEmpty;
+	wire shRegFifoFull;
+	wire valRdDataShReg;
+
+	//FifoMax
+	wire [31:0] dataFromMaxFifo;
+	wire [31:0] dataFromMaxFifoCtrl;
+	wire readEnMax;
+	wire writeEnMax;
+	wire maxFifoEmpty;
+	wire maxFifoFull;
+	wire valRdDataMAX;
 
 	wire spiDataVal;
 	wire [WORDWIDTH-1:0] spiData;
@@ -104,41 +164,49 @@ module TopSbTmsg
 
 //================================================================================
 //  CODING
+ClkGen ClkGen_inst (
+	.Clk24Mhz_i			(Clk_i),
+	.Clk24Mhz_o			(gclk),
+	.Clk100Mhz_o		(clk100),
+	.Clk5Mhz_o			(clk5),
+	.Clk20Mhz_o			(clk20),
+	.Clk50Mhz_o			(clk50),
+	.Clk26dot25Mhz_o 	(clk26dot25),
+	.Clk60Mhz_o			(clk60)
+);
 
 InterfaceArbiter 
 #(	
-	.OUTWORDWIDTH (WORDWIDTH),
-	.SSPIWORDWIDTH (SSPIWORDWIDTH)
+	.OUTWORDWIDTH	(WORDWIDTH),
+	.SSPIWORDWIDTH	(SSPIWORDWIDTH)
 )
 SpiSlaveArbiter
 (
-	.Rst_i		(Rst_i),
-	// .Clk_i		(clk100),
-	.Clk_i		(Clk_i),
-	
-	.Sck_i		(Sck_i),
-	.Ss_i		(Ss_i),
-	
-	.Mosi0_i	(Mosi0_i),
-	.Mosi1_i	(Mosi1_io),
-	.Mosi2_i	(Mosi2_i),
-	.Mosi3_i	(Mosi3_i),
-	
-	
-	.DataVal_o	(spiDataVal),
-	.Data_o		(spiData)
+	.Rst_i			(Rst_i),
+	.Clk_i			(clk100),
+		
+	.Sck_i			(Sck_i),
+	.Ss_i			(Ss_i),
+		
+	.Mosi0_i		(Mosi0_i),
+	.Mosi1_i		(Mosi1_io),
+	.Mosi2_i		(Mosi2_i),
+	.Mosi3_i		(Mosi3_i),
+		
+		
+	.DataVal_o		(spiDataVal),
+	.Data_o			(spiData)
 );
 
 PacketAnalyzer4Mosi PacketAnalyzer4Mosi
 (
-	// .Clk_i	(clk100),
-	.Clk_i	(Clk_i),
-	.Rst_i	(Rst_i),
+	.Clk_i					(clk100),
+	.Rst_i					(Rst_i),
 
-	.DataFromSpi_i		(spiData),
-	.ValDataFromSpi_i	(spiDataVal),
+	.DataFromSpi_i			(spiData),
+	.ValDataFromSpi_i		(spiDataVal),
 
-	.BusyMosi1_i	(busyMosi1),
+	.BusyMosi1_i			(busyMosi1),
 
 	.ValLmxDataToFifo_o		(valLmxDataToFifo),
 	.ValDdsDataToFifo_o		(valDdsDataToFifo),
@@ -149,19 +217,18 @@ PacketAnalyzer4Mosi PacketAnalyzer4Mosi
 	.ValMaxDataToFifo_o		(valMaxDataToFifo),
 	.ValGpioDataToFifo_o	(valGpioDataToFifo),
 
-	.Busy_o	(busyMosi4)
+	.Busy_o					(busyMosi4)
 );
 
 PacketAnalyzer1Mosi PacketAnalyzer1Mosi
 (
-	// .Clk_i	(clk100),
-	.Clk_i	(Clk_i),
-	.Rst_i	(Rst_i),
+	.Clk_i				(clk100),
+	.Rst_i				(Rst_i),
 
 	.DataFromSpi_i		(spiData),
 	.ValDataFromSpi_i	(spiDataVal),
 
-	.BusyMosi4_i	(busyMosi4),
+	.BusyMosi4_i		(busyMosi4),
 
 	.FlagDirectLmx_o	(flagDirectLmx),
 	.FlagDirectDds_o	(flagDirectDds),
@@ -173,7 +240,343 @@ PacketAnalyzer1Mosi PacketAnalyzer1Mosi
 	.FlagDirectGpio_o	(flagDirectGpio),
 	.FlagDirectTemp_o	(flagDirectTemp),
 
-	.Busy_o	(busyMosi1)
+	.Busy_o				(busyMosi1)
+);
+
+//***********************************************
+//	           LMX2594
+//***********************************************
+FifoCtrl #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(24)
+) FifoCtrlLmx
+(
+	.WrClk_i		(clk100),
+	.RdClk_i		(clk60),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valLmxDataToFifo),
+	.BusySpiM_i		(busySpiMLmx),
+	.FifoFull_i		(lmxFifoFull),
+	.FifoEmpty_i	(lmxFifoEmpty),
+	.Data_o			(dataFromLmxFifoCtrl),
+	.ReadEn_o		(readEnLmx),
+	.WriteEn_o		(writeEnLmx),
+	.ValRdData_o	(valRdDataLMX)
+);
+
+FifoLMX FifoLMX_inst (
+	.Data	(dataFromLmxFifoCtrl),
+	.WrClk	(clk100),
+	.RdClk	(clk60),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnLmx),
+	.RdEn	(readEnLmx),
+	.Full	(lmxFifoFull),
+	.Empty	(lmxFifoEmpty),
+	.Q		(dataFromLmxFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(24)
+)SpiMLmx(
+	.Clk_i		(clk60),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataLMX),
+	.SpiData_i	(dataFromLmxFifo),
+	.Busy_o	    (busySpiMLmx),
+	.Ss_o		(),
+	.Mosi_o		(),
+	.Sck_o		()
+);
+
+//***********************************************
+//	           		DDS
+//***********************************************
+FifoCtrl #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(3),
+	.OUT_WIDTH		(64)
+) FifoCtrlDDS
+(
+	.WrClk_i		(clk100),
+	.RdClk_i		(clk50),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valDdsDataToFifo),
+	.BusySpiM_i		(busySpiMDds),
+	.FifoFull_i		(ddsFifoFull),
+	.FifoEmpty_i	(ddsFifoEmpty),
+	.Data_o			(dataFromDdsFifoCtrl),
+	.ReadEn_o		(readEnDds),
+	.WriteEn_o		(writeEnDds),
+	.ValRdData_o	(valRdDataDDS)
+);
+
+FifoDDS FifoDDS_inst (
+	.Data	(dataFromDdsFifoCtrl),
+	.WrClk	(clk100),
+	.RdClk	(clk50),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnDds),
+	.RdEn	(readEnDds),
+	.Full	(ddsFifoFull),
+	.Empty	(ddsFifoEmpty),
+	.Q		(dataFromDdsFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(64)
+)SpiMDDS(
+	.Clk_i		(clk50),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataDDS),
+	.SpiData_i	(dataFromDdsFifo),
+	.Busy_o	    (busySpiMDds),
+	.Ss_o		(),
+	.Mosi_o		(),
+	.Sck_o		()
+);
+
+//***********************************************
+//	           		POT
+//***********************************************
+FifoCtrl #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(16)
+) FifoCtrlPot
+(
+	.WrClk_i		(clk100),
+	.RdClk_i		(clk5),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valPotDataToFifo),
+	.BusySpiM_i		(busySpiMPot),
+	.FifoFull_i		(potFifoFull),
+	.FifoEmpty_i	(potFifoEmpty),
+	.Data_o			(dataFromPotFifoCtrl),
+	.ReadEn_o		(readEnPot),
+	.WriteEn_o		(writeEnPot),
+	.ValRdData_o	(valRdDataPOT)
+);
+
+Fifo16x3 FifoPot_inst (
+	.Data	(dataFromPotFifoCtrl),
+	.WrClk	(clk100),
+	.RdClk	(clk5),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnPot),
+	.RdEn	(readEnPot),
+	.Full	(potFifoFull),
+	.Empty	(potFifoEmpty),
+	.Q		(dataFromPotFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(16)
+)SpiMPot(
+	.Clk_i		(clk5),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataPOT),
+	.SpiData_i	(dataFromPotFifo),
+	.Busy_o	    (busySpiMPot),
+	.Ss_o		(),
+	.Mosi_o		(),
+	.Sck_o		()
+);
+
+//***********************************************
+//	           		DAC
+//***********************************************
+FifoCtrl #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(16)
+) FifoCtrlDac
+(
+	.WrClk_i		(clk100),
+	.RdClk_i		(clk5),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valDacDataToFifo),
+	.BusySpiM_i		(busySpiMDac),
+	.FifoFull_i		(dacFifoFull),
+	.FifoEmpty_i	(dacFifoEmpty),
+	.Data_o			(dataFromDacFifoCtrl),
+	.ReadEn_o		(readEnDac),
+	.WriteEn_o		(writeEnDac),
+	.ValRdData_o	(valRdDataDAC)
+);
+
+Fifo16x3 FifoDAC_inst (
+	.Data	(dataFromDacFifoCtrl),
+	.WrClk	(clk100),
+	.RdClk	(clk50),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnDac),
+	.RdEn	(readEnDac),
+	.Full	(dacFifoFull),
+	.Empty	(dacFifoEmpty),
+	.Q		(dataFromDacFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(16)
+)SpiMDac(
+	.Clk_i		(clk50),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataDAC),
+	.SpiData_i	(dataFromDacFifo),
+	.Busy_o	    (busySpiMDac),
+	.Ss_o		(),
+	.Mosi_o		(),
+	.Sck_o		()
+);
+
+//***********************************************
+//	           		ATT
+//***********************************************
+FifoCtrl #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(16)
+) FifoCtrlAtt
+(
+	.WrClk_i		(clk100),
+	.RdClk_i		(clk50),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valAttDataToFifo),
+	.BusySpiM_i		(busySpiMAtt),
+	.FifoFull_i		(attFifoFull),
+	.FifoEmpty_i	(attFifoEmpty),
+	.Data_o			(dataFromAttFifoCtrl),
+	.ReadEn_o		(readEnAtt),
+	.WriteEn_o		(writeEnAtt),
+	.ValRdData_o	(valRdDataATT)
+);
+
+Fifo16x3 FifoAtt_inst (
+	.Data	(dataFromAttFifoCtrl),
+	.WrClk	(clk100),
+	.RdClk	(clk50),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnAtt),
+	.RdEn	(readEnAtt),
+	.Full	(attFifoFull),
+	.Empty	(attFifoEmpty),
+	.Q		(dataFromAttFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(16)
+)SpiMAtt(
+	.Clk_i		(clk50),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataATT),
+	.SpiData_i	(dataFromAttFifo),
+	.Busy_o	    (busySpiMAtt),
+	.Ss_o		(),
+	.Mosi_o		(),
+	.Sck_o		()
+);
+
+//***********************************************
+//	           		ShiftRegister
+//***********************************************
+FifoCtrl #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(8)
+) FifoCtrlShReg
+(
+	.WrClk_i		(clk100),
+	.RdClk_i		(clk26dot25),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valShRegDataToFifo),
+	.BusySpiM_i		(busySpiMShReg),
+	.FifoFull_i		(shRegFifoFull),
+	.FifoEmpty_i	(shRegFifoEmpty),
+	.Data_o			(dataFromShRegFifoCtrl),
+	.ReadEn_o		(readEnShReg),
+	.WriteEn_o		(writeEnShReg),
+	.ValRdData_o	(valRdDataShReg)
+);
+
+FifoShiftReg FifoShReg_inst (
+	.Data	(dataFromShRegFifoCtrl),
+	.WrClk	(clk100),
+	.RdClk	(clk26dot25),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnShReg),
+	.RdEn	(readEnShReg),
+	.Full	(shRegFifoFull),
+	.Empty	(shRegFifoEmpty),
+	.Q		(dataFromShRegFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(8)
+)SpiMShReg(
+	.Clk_i		(clk26dot25),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataShReg),
+	.SpiData_i	(dataFromShRegFifo),
+	.Busy_o	    (busySpiMShReg),
+	.Ss_o		(),
+	.Mosi_o		(),
+	.Sck_o		()
+);
+
+//***********************************************
+//	           		MAX2870
+//***********************************************
+FifoCtrl #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(2),
+	.OUT_WIDTH		(32)
+) FifoCtrlMax
+(
+	.WrClk_i		(clk100),
+	.RdClk_i		(clk50),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valMaxDataToFifo),
+	.BusySpiM_i		(busySpiMMax),
+	.FifoFull_i		(maxFifoFull),
+	.FifoEmpty_i	(maxFifoEmpty),
+	.Data_o			(dataFromMaxFifoCtrl),
+	.ReadEn_o		(readEnMax),
+	.WriteEn_o		(writeEnMax),
+	.ValRdData_o	(valRdDataMAX)
+);
+
+FifoMax2870 FifoMax2870_inst (
+	.Data	(dataFromMaxFifoCtrl),
+	.WrClk	(clk100),
+	.RdClk	(clk50),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnMax),
+	.RdEn	(readEnMax),
+	.Full	(maxFifoFull),
+	.Empty	(maxFifoEmpty),
+	.Q		(dataFromMaxFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(32)
+)SpiMMax(
+	.Clk_i		(clk50),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataMAX),
+	.SpiData_i	(dataFromMaxFifo),
+	.Busy_o	    (busySpiMMax),
+	.Ss_o		(),
+	.Mosi_o		(),
+	.Sck_o		()
 );
 
 endmodule