Merge branch 'dev' into Mikhail/feature_TempRead

src/src/InterfaceArbiter/InterfaceArbiter.v

@@ -71,7 +71,7 @@ module InterfaceArbiter
 	reg dataValReg;
 	
 	reg [OUTWORDWIDTH/4-1:0] ssCnt;
-	reg [OUTWORDWIDTH/4-1:0] wordsCnt;
+	reg [16:0] wordsCnt;
 	wire [OUTWORDWIDTH/4-1:0] ssCntRstThresh = (spiMode) ? QSPIWORDWIDTH-1:SSPIWORDWIDTH-1;
 	
 	reg [16:0] wordsNum;
@@ -90,7 +90,7 @@ module InterfaceArbiter
 	
 //================================================================================
 //  CODING
-	always @(posedge Sck_i) begin
+	always @(posedge Sck_i or posedge Rst_i) begin
 		if (!Rst_i) begin
 			if (!Ss_i) begin
 				captRegSspi <= {captRegSspi[OUTWORDWIDTH-2:0], Mosi0_i};
@@ -110,7 +110,7 @@ module InterfaceArbiter
 		end
 	end
 	
-	always @(posedge Sck_i) begin
+	always @(posedge Sck_i or posedge Rst_i) begin
 		if (!Rst_i) begin
 			if (!Ss_i) begin
 				if (ssCnt == ssCntRstThresh) begin
@@ -124,7 +124,7 @@ module InterfaceArbiter
 		end
 	end
 	
-	always @(posedge Clk_i) begin
+	always @(posedge Clk_i or posedge Rst_i) begin
 		if (!Rst_i) begin
 			if (currState == DATARX) begin
 				if (ssPos) begin
@@ -146,7 +146,7 @@ module InterfaceArbiter
 		end
 	end
 	
-	always @(posedge Clk_i) begin
+	always @(posedge Sck_i or posedge Rst_i) begin
 		if (!Rst_i) begin
 			if (currState == IDLE) begin
 				if (ssCnt == 1) begin
@@ -162,7 +162,7 @@ module InterfaceArbiter
 		end
 	end 
 	
-	always @(posedge Clk_i) begin
+	always @(posedge Clk_i or posedge Rst_i) begin
 		if (!Rst_i) begin
 			if (currState == IDLE) begin
 				if (!spiMode) begin
@@ -176,7 +176,7 @@ module InterfaceArbiter
 		end
 	end 
 	
-	always @(posedge Clk_i) begin
+	always @(posedge Clk_i or posedge Rst_i) begin
 		if (!Rst_i) begin
 			ssReg <= Ss_i;
 			ssRegR <= ssReg;
@@ -190,7 +190,7 @@ module InterfaceArbiter
 		end
 	end 
 	
-	always @(posedge Clk_i) begin
+	always @(posedge Clk_i or posedge Rst_i) begin
 		if (!Rst_i) begin
 			if (ssPos) begin
 				dataRegSSpi <= captRegSspi;
@@ -206,16 +206,16 @@ module InterfaceArbiter
 		end
 	end
 
-	always	@(posedge	Clk_i)	begin
-		if	(Rst_i)	begin
-			currState	<=	IDLE;
-		end	else	begin
-			currState	<=	nextState;
+	always @(posedge Clk_i or posedge Rst_i) begin
+		if (Rst_i) begin
+			currState <= IDLE;
+		end else begin
+			currState <= nextState;
 		end
 	end
 
 	always @(*) begin
-		nextState	=	IDLE;
+		nextState = IDLE;
 		case(currState)
 		IDLE		:begin
 						if (ssPosR)	begin

src/src/Top/ExtQspiMEmul.v

@@ -24,13 +24,13 @@ module ExtQSpiMEmul
 	localparam [1:0] PAUSE = 3;
 
 	parameter MODE = 1'h1;
-	parameter [3:0] LMX = 4'h1;
-	parameter [1:0] DDS = 2'h1;
+	parameter [3:0] LMX = 4'h3;
+	parameter [1:0] DDS = 2'h2;
 	parameter POT = 1'h1;
 	parameter DAC = 1'h1;
 	parameter ATT = 1'h1;
-	parameter [1:0] SHREG = 2'h1;
-	parameter [2:0] MAX2870 = 3'h1;
+	parameter [1:0] SHREG = 2'h3;
+	parameter [2:0] MAX2870 = 3'h3;
 	parameter [1:0] GPIO = 2'h1;
 	parameter [5:0] RESERVED = 6'h0;
 	parameter EOPBIT = 1'b0;
@@ -60,7 +60,7 @@ module ExtQSpiMEmul
 //================================================================================
 //  ASSIGNMENTS
 
-assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b1;
+assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b0;
 assign	TxDone_o	=	(txStop & (currState== CMD));
 
 //================================================================================
@@ -136,16 +136,16 @@ always	@(posedge Clk_i)	begin
 			Mosi2_o	<=	dspSpiData[11];
 			Mosi3_o	<=	dspSpiData[5];
 		end	else	begin
-			Mosi0_o	<=	1'b1;
-			Mosi1_o	<=	1'b1;
-			Mosi2_o	<=	1'b1;
-			Mosi3_o	<=	1'b1;
+			Mosi0_o	<=	1'b0;
+			Mosi1_o	<=	1'b0;
+			Mosi2_o	<=	1'b0;
+			Mosi3_o	<=	1'b0;
 		end
 	end	else	begin
-		Mosi0_o	<=	1'b1;
-		Mosi1_o	<=	1'b1;
-		Mosi2_o	<=	1'b1;
-		Mosi3_o	<=	1'b1;
+		Mosi0_o	<=	1'b0;
+		Mosi1_o	<=	1'b0;
+		Mosi2_o	<=	1'b0;
+		Mosi3_o	<=	1'b0;
 	end
 end
 

src/src/Top/ExtSpiMEmul.v

@@ -23,7 +23,7 @@ module ExtSpiMEmul
 
 	parameter MODE = 1'h0;
 	parameter [4:0] DEVID = 5'h1;
-	parameter [16:0] WORDSNUM = 17'h3;
+	parameter [16:0] WORDSNUM = 17'd24;
 	parameter EOPBIT = 1'b1;
 	
 //================================================================================
@@ -46,7 +46,7 @@ module ExtSpiMEmul
 //================================================================================
 //  ASSIGNMENTS
 
-assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b1;
+assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b0;
 assign	TxDone_o	=	(txStop & (currState== CMD));
 
 //================================================================================
@@ -119,10 +119,10 @@ always	@(posedge Clk_i)	begin
 		if	(txCnt	>=	7'd0)	begin
 			Mosi_o	<=	dspSpiData[23];
 		end	else	begin
-			Mosi_o	<=	1'b1;
+			Mosi_o	<=	1'b0;
 		end
 	end	else	begin
-		Mosi_o	<=	1'b1;
+		Mosi_o	<=	1'b0;
 	end
 end
 

src/src/Top/TopSbTmsg.v

@@ -60,14 +60,13 @@ module TopSbTmsg
 //================================================================================
 //  REG/WIRE
 
-	wire clk360;
-	wire clk100;
-	wire clk75;
-	wire clk50;
-	wire clk40;
-	wire clk20;
-	wire clk30;
+	wire clk24;
+	wire gclk100;
 	wire clk5;
+	wire clk20;
+	wire clk50;
+	wire clk26dot25;
+	wire clk60;
 
 	wire spiDataVal;
 	wire [WORDWIDTH-1:0] spiData;
@@ -94,7 +93,6 @@ module TopSbTmsg
 	wire flagDirectGpio;	
 	wire flagDirectTemp;	
 	
-	
 //================================================================================
 //  ASSIGNMENTS
 
@@ -105,16 +103,28 @@ module TopSbTmsg
 //================================================================================
 //  CODING
 
+ClkGen ClkGen
+(
+	.Clk24Mhz_i			(Clk_i),
+	
+	.Clk24Mhz_o			(clk24),
+	.Clk100Mhz_o		(gclk100),
+	.Clk5Mhz_o			(clk5),
+	.Clk20Mhz_o			(clk20),
+	.Clk50Mhz_o			(clk50),
+	.Clk26dot25Mhz_o	(clk26dot25),
+	.Clk60Mhz_o			(clk60)
+);
+
 InterfaceArbiter 
 #(	
-	.OUTWORDWIDTH (WORDWIDTH),
-	.SSPIWORDWIDTH (SSPIWORDWIDTH)
+	.OUTWORDWIDTH	(WORDWIDTH),
+	.SSPIWORDWIDTH	(SSPIWORDWIDTH)
 )
 SpiSlaveArbiter
 (
 	.Rst_i		(Rst_i),
-	// .Clk_i		(clk100),
-	.Clk_i		(Clk_i),
+	.Clk_i		(gclk100),
 	
 	.Sck_i		(Sck_i),
 	.Ss_i		(Ss_i),
@@ -131,14 +141,13 @@ SpiSlaveArbiter
 
 PacketAnalyzer4Mosi PacketAnalyzer4Mosi
 (
-	// .Clk_i	(clk100),
-	.Clk_i	(Clk_i),
-	.Rst_i	(Rst_i),
+	.Clk_i					(gclk100),
+	.Rst_i					(Rst_i),
 
-	.DataFromSpi_i		(spiData),
-	.ValDataFromSpi_i	(spiDataVal),
+	.DataFromSpi_i			(spiData),
+	.ValDataFromSpi_i		(spiDataVal),
 
-	.BusyMosi1_i	(busyMosi1),
+	.BusyMosi1_i			(busyMosi1),
 
 	.ValLmxDataToFifo_o		(valLmxDataToFifo),
 	.ValDdsDataToFifo_o		(valDdsDataToFifo),
@@ -149,31 +158,42 @@ PacketAnalyzer4Mosi PacketAnalyzer4Mosi
 	.ValMaxDataToFifo_o		(valMaxDataToFifo),
 	.ValGpioDataToFifo_o	(valGpioDataToFifo),
 
-	.Busy_o	(busyMosi4)
+	.Busy_o					(busyMosi4)
 );
 
-PacketAnalyzer1Mosi PacketAnalyzer1Mosi
+PacketAnalyzer1Mosi	PacketAnalyzer1Mosi
 (
-	// .Clk_i	(clk100),
-	.Clk_i	(Clk_i),
-	.Rst_i	(Rst_i),
-
-	.DataFromSpi_i		(spiData),
-	.ValDataFromSpi_i	(spiDataVal),
-
-	.BusyMosi4_i	(busyMosi4),
-
-	.FlagDirectLmx_o	(flagDirectLmx),
-	.FlagDirectDds_o	(flagDirectDds),
-	.FlagDirectPot_o	(flagDirectPot),
-	.FlagDirectDac_o	(flagDirectDac),
-	.FlagDirectAtt_o	(flagDirectAtt),
-	.FlagDirectShReg_o	(flagDirectShReg),
-	.FlagDirectMax_o	(flagDirectMax),
-	.FlagDirectGpio_o	(flagDirectGpio),
-	.FlagDirectTemp_o	(flagDirectTemp),
-
-	.Busy_o	(busyMosi1)
+	.Clk_i					(gclk100),
+	.Rst_i					(Rst_i),
+	
+	.DataFromSpi_i			(spiData),
+	.ValDataFromSpi_i		(spiDataVal),
+	
+	.BusyMosi4_i			(busyMosi4),
+	
+	.FlagDirectLmx_o		(flagDirectLmx),
+	.FlagDirectDds_o		(flagDirectDds),
+	.FlagDirectPot_o		(flagDirectPot),
+	.FlagDirectDac_o		(flagDirectDac),
+	.FlagDirectAtt_o		(flagDirectAtt),
+	.FlagDirectShReg_o		(flagDirectShReg),
+	.FlagDirectMax_o		(flagDirectMax),
+	.FlagDirectGpio_o		(flagDirectGpio),
+	.FlagDirectTemp_o		(flagDirectTemp),
+	
+	.Busy_o					(busyMosi1)
 );
 
+GpioCtrl GpioCtrl
+(
+	.Clk_i					(gclk100),
+	.Rst_i					(Rst_i),
+	
+	.ValGpioDataToFifo_i	(valGpioDataToFifo),
+	.Data_i					(spiData),
+
+	.GpioReg_o				(Gpio_o)
+);
+
+
 endmodule