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@@ -185,6 +185,11 @@ initial begin
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#(700000-60) rstForFPGA = 1;
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#(CLK_PERIOD*74) rstForFPGA = 0;
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#(165000) Start_i = 1; // Start SPI transaction
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+ wait (trCnt == 45) begin
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+ Start_i = 0;
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+ end
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+ #(CLK_PERIOD*100)
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+ Start_i = 1; // Start SPI transaction
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wait (trCnt == 70) begin
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Start_i = 0;
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end
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@@ -193,7 +198,7 @@ initial begin
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end
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//***********************************************
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-always_ff @(posedge Clk50) begin
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+always_ff @(posedge Clk100) begin
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if (Rst_i) begin
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trCnt <= 0;
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end
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@@ -258,7 +263,7 @@ always_comb begin
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end
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end
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-always_ff @(posedge Clk50) begin
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+always_ff @(posedge Clk100) begin
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if (Rst_i) begin
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randData<=0;
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randData32 <= 0;
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@@ -336,7 +341,7 @@ always_comb begin
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GSR GSR(.GSRI(1'b1));
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ExtSpiMEmul ExtSpiMEmul_inst (
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- .Clk_i(Clk50),
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+ .Clk_i(Clk100),
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.Rst_i(Rst_i || modeSel),
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.Start_i(Start_i),
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.ClockPhase_i(CPHA_i),
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@@ -356,7 +361,7 @@ always_comb begin
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);
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ExtQspiMEmul ExtQspiMEmul_inst (
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- .Clk_i(Clk50),
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+ .Clk_i(Clk100),
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.Rst_i(Rst_i || !modeSel),
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.Start_i(Start_i),
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.ClockPhase_i(CPHA_i),
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