Синхронизирован сигнал валидности от InterFaceArbiter. Остальная логика работает на частоте 60 МГц.

src/constr/SbTmsg.sdc

@@ -2,11 +2,14 @@
 //All rights reserved.
 //File Title: Timing Constraints file
 //Tool Version: V1.9.9.03 (64-bit) 
-//Created Time: 2024-05-29 16:56:41
-create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
-//create_clock -name clk100 -period 10 -waveform {0 5} [get_nets {gclk100}]
-create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
+//Created Time: 2024-05-31 16:04:42
 create_clock -name clk5 -period 200 -waveform {0 100} [get_nets {clk5}]
+create_clock -name clk60 -period 16.667 -waveform {0 8.334} [get_nets {clk60}]
+create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
+create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
+create_clock -name clk100 -period 10 -waveform {0 5} [get_nets {gclk100}]
 set_clock_groups -asynchronous -group [get_clocks {Clk_i}] -group [get_clocks {Sck_i}]
 set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Clk_i}] 
 set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Sck_i}] 
+set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {clk60}] 
+set_false_path -from [get_clocks {clk60}] -to [get_clocks {Sck_i}] 

src/src/CDC/Sync1bit.v

@@ -47,7 +47,7 @@ reg plsToggleSyncC;
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
-assign Signal_o = plsToggleSyncA^plsToggle;
+assign Signal_o = plsToggleSyncB^plsToggleSyncA;
 //================================================================================
 //	CODING
 //================================================================================

src/src/Top/TopSbTmsg.v

@@ -352,7 +352,7 @@ InterfaceArbiter
 SpiSlaveArbiter
 (
 	.Rst_i		(Rst_i),
-	.Clk_i		(clk60),
+	.Clk_i		(gclk100),
 	
 	.Sck_i		(Sck_i),
 	.Ss_i		(Ss_i),