Merge branch 'Anatoliy/feature_SPIm' of zaytsev.mikhail/SB_TMSG44V1_FPGA into dev

src/src/SPIm/ExtSpiSlaveEmul.v

@@ -0,0 +1,65 @@
+module ExtSpiSlaveEmul (
+    input Clk_i,
+    input Rst_i,
+
+    input Sck_i,
+    input Ss_i,
+    input Mosi0_i,
+
+    output reg [23:0] Data_o,
+    output reg Val_o
+);
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+    reg ssReg;
+    reg ssRegR;  
+    reg [23:0] shiftReg;
+
+//===============================================================================
+//  ASSIGNMENTS
+
+//================================================================================
+//	CODING
+//================================================================================
+    always	@(posedge	Clk_i)	begin
+    	ssReg	<=	Ss_i;
+    	ssRegR	<=	ssReg;
+    end
+
+    always @(posedge Clk_i) begin 
+        if (Rst_i) begin 
+            Data_o <= 24'h0;
+        end
+        else begin 
+            if (ssReg && !ssRegR) begin 
+                Data_o <= shiftReg;
+            end
+        end
+    end
+
+    always @(posedge Sck_i or posedge Rst_i) begin 
+        if (Rst_i) begin 
+            shiftReg<= 24'h0;
+        end
+        else begin  
+            if (!Ss_i) begin 
+                shiftReg<= {shiftReg[22:0], Mosi0_i};
+            end
+            else begin 
+                shiftReg<= 24'h0;
+            end
+        end
+    end
+    
+    always @(posedge Clk_i) begin
+        if (ssReg && !ssRegR) begin 
+            Val_o <= 1'b1;
+        end
+        else begin 
+            Val_o <= 1'b0;
+        end
+    end
+
+    endmodule

src/src/SPIm/SPIm.v

@@ -0,0 +1,119 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     SPIm
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:     This module implements SPI master interface
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module SpiM #(
+    parameter DATA_WIDTH = 24
+)(
+    input Clk_i,
+    input Rst_i,
+    input Val_i,
+    input [DATA_WIDTH-1:0] SpiData_i,
+
+    output Ss_o,
+    output Mosi_o,
+    output Sck_o,
+    output Busy_o
+);
+
+//================================================================================
+//FUNCTIONS
+//================================================================================
+function integer log2;
+input [31:0] value;
+	begin
+		log2 = 0;
+		while (value > 1) begin
+			value   = value >> 1;
+			log2    = log2 + 1;
+		end
+		if	((2**log2)<DATA_WIDTH)	begin
+			log2	=	log2+1;
+		end	
+	end
+endfunction
+
+//================================================================================
+//	REG/WIRE
+//================================================================================
+reg [log2(DATA_WIDTH)-1:0] ssCnt;
+reg [DATA_WIDTH-1:0] mosiReg;
+reg	ssReg;
+
+//================================================================================
+//  ASSIGNMENTS
+//================================================================================
+assign Ss_o = ssReg;
+assign Mosi_o = (!ssReg) ? mosiReg[DATA_WIDTH-1] : 1'b0;
+assign Sck_o = (!ssReg) ? Clk_i : 1'b0;
+assign Busy_o = !ssReg;
+
+//================================================================================
+//	CODING
+//================================================================================
+always @(negedge Clk_i) begin 
+    if (Rst_i) begin 
+        ssCnt <= 7'h0;
+    end
+    else begin
+        if (ssCnt == 0) begin 
+            if (Val_i) begin 
+                ssCnt <= ssCnt + 1;
+            end
+        end
+        else begin 
+            if (ssCnt < DATA_WIDTH) begin 
+                ssCnt <= ssCnt + 1;
+            end
+            else begin 
+                ssCnt <= 7'h0;
+            end
+        end
+    end
+end
+
+always @(negedge Clk_i) begin 
+    if (Rst_i) begin 
+        mosiReg <= 0;
+    end
+    else begin 
+        if (!ssReg) begin 
+            mosiReg <= mosiReg << 1;
+        end
+        else begin
+            if (Val_i) begin
+                mosiReg <= SpiData_i;
+            end
+        end
+    end
+end
+
+always @(negedge Clk_i) begin 
+    if (Rst_i) begin 
+        ssReg <= 1'b1;
+    end
+    else begin 
+        if (ssCnt < DATA_WIDTH) begin 
+            ssReg <= 1'b0;
+        end
+        else begin 
+            ssReg <= 1'b1;
+        end
+    end
+end
+
+endmodule

src/src/SPIm/SPIm_tb.do

@@ -0,0 +1,43 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider DUT
+add wave -noupdate /SpiM_tb/DUT/Clk_i
+add wave -noupdate /SpiM_tb/DUT/Rst_i
+add wave -noupdate /SpiM_tb/DUT/Val_i
+add wave -noupdate /SpiM_tb/DUT/SpiData_i
+add wave -noupdate /SpiM_tb/DUT/Ss_o
+add wave -noupdate /SpiM_tb/DUT/Mosi_o
+add wave -noupdate /SpiM_tb/DUT/Sck_o
+add wave -noupdate /SpiM_tb/DUT/Busy_o
+add wave -noupdate /SpiM_tb/DUT/ssCnt
+add wave -noupdate /SpiM_tb/DUT/mosiReg
+add wave -noupdate /SpiM_tb/DUT/ssReg
+add wave -noupdate -divider SPIs
+add wave -noupdate /SpiM_tb/ExtSpiSlaveEmul_inst/Clk_i
+add wave -noupdate /SpiM_tb/ExtSpiSlaveEmul_inst/Rst_i
+add wave -noupdate /SpiM_tb/ExtSpiSlaveEmul_inst/Sck_i
+add wave -noupdate /SpiM_tb/ExtSpiSlaveEmul_inst/Ss_i
+add wave -noupdate /SpiM_tb/ExtSpiSlaveEmul_inst/Mosi0_i
+add wave -noupdate /SpiM_tb/ExtSpiSlaveEmul_inst/Data_o
+add wave -noupdate /SpiM_tb/ExtSpiSlaveEmul_inst/Val_o
+add wave -noupdate /SpiM_tb/ExtSpiSlaveEmul_inst/ssReg
+add wave -noupdate /SpiM_tb/ExtSpiSlaveEmul_inst/ssRegR
+add wave -noupdate /SpiM_tb/ExtSpiSlaveEmul_inst/shiftReg
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {3560000 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {10500 ns}

src/src/SPIm/SPIm_tb.sv

@@ -0,0 +1,165 @@
+`timescale 1ns / 1ps
+module SpiM_tb;
+logic Clk_i;
+logic Rst_i;
+logic [23:0] spiData;
+
+//***********************************************
+//	            LOCALPARAMS
+//***********************************************
+localparam N = 16;
+
+//***********************************************
+//	            SIGNALS
+//***********************************************
+logic [23:0] randData;
+logic [23:0] spiQueue [N-1:0];
+logic [23:0] spisQueue [N-1:0];
+logic busyFromSpi;
+logic valToSpi;
+logic [4:0] numOfWords;
+logic [4:0] numOfWordsSPIs;
+logic valFromSPIs;
+logic sck;
+logic ss;
+logic mosi;
+logic [23:0] spiDataFromDUT;
+
+//***********************************************
+//	            CLASSES
+//***********************************************
+
+class Packet;
+    rand bit [23:0] data;
+endclass
+
+Packet pkt;
+
+
+//***********************************************
+//	           CLOCK GENERATION
+//***********************************************
+always begin
+    #5 Clk_i = ~Clk_i;
+end
+
+//***********************************************
+//	           INITIALIZATION
+//***********************************************
+initial begin 
+    Clk_i =1'b1;
+    pkt = new();
+    Rst_i = 1'b1;
+    #50 Rst_i = 1'b0;
+    foreach(spiQueue[i]) begin
+        spiQueue[i] = $urandom();
+    end
+    wait(numOfWordsSPIs == 5'h10);
+    if (spiQueue == spisQueue) begin
+        $display("Test Passed");
+    end
+    else begin
+        $display("Test Failed");
+    end
+end
+
+//***********************************************
+//	           CODING
+//***********************************************
+always_ff @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        randData<=0;
+    end
+    else begin 
+        randData <= pkt.randomize(data);
+    end
+end
+
+always_ff @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        numOfWords<=5'h10;
+    end
+    else begin 
+        if (valToSpi) begin 
+            numOfWords <= numOfWords - 1;
+        end
+    end
+end
+
+always_ff @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        valToSpi <= 1'b0;
+    end
+    else begin 
+        if (!busyFromSpi && numOfWords != 0) begin 
+            valToSpi <= 1'b1;
+        end
+        else begin 
+            valToSpi <= 1'b0;
+        end
+    end
+end
+
+always_ff @(*) begin 
+    if (Rst_i) begin 
+        spiData=0;
+    end
+    else begin 
+        if (valToSpi) begin 
+            spiData = spiQueue[numOfWords-1];
+        end
+    end
+end
+
+always_ff @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        numOfWordsSPIs<=5'h0;
+    end
+    else begin
+        if (valFromSPIs) begin 
+            numOfWordsSPIs <= numOfWordsSPIs + 1;
+        end
+    end
+end
+
+
+
+always_ff @(posedge Clk_i) begin
+    if (Rst_i) begin 
+        foreach(spisQueue[i]) begin
+            spisQueue[i] <= 0;
+        end
+    end
+    else begin 
+        if (valFromSPIs) begin 
+            spisQueue[(N-1)-numOfWordsSPIs] <= spiDataFromDUT;
+        end
+    end
+end
+
+
+//***********************************************
+//	           DUT INSTANTIATION
+//***********************************************
+SpiM DUT (
+    .Clk_i(Clk_i),
+    .Rst_i(Rst_i),
+    .SpiData_i(spiData),
+    .Val_i(valToSpi),
+    .Sck_o(sck),
+    .Ss_o(ss),
+    .Mosi_o(mosi),
+    .Busy_o(busyFromSpi)
+);
+
+ExtSpiSlaveEmul ExtSpiSlaveEmul_inst (
+    .Clk_i(Clk_i),
+    .Rst_i(Rst_i),
+    .Sck_i(sck),
+    .Ss_i(ss),
+    .Mosi0_i(mosi),
+    .Data_o(spiDataFromDUT),
+    .Val_o(valFromSPIs)
+);
+
+endmodule