Переработан автомат и логика захвата данных, чтобы успевать в ситуации когда между посылками 1 такт задержки.

src/src/InterfaceArbiter/ExtQspiMEmul.v

@@ -46,9 +46,12 @@ module ExtQSpiMEmul
 
 	
 	
-	wire	txStop	=	(cmdCnt	>=	LMX+DDS+POT+DAC+ATT+SHREG+MAX2870+GPIO+1);
+	// wire	txStop	=	(cmdCnt	>=	LMX+DDS+POT+DAC+ATT+SHREG+MAX2870+GPIO+1);
+	wire	txStop	=	(cmdCnt	== 2);
 	
-	reg [23:0] headerCmd = {MODE,LMX,DDS,POT,DAC,ATT,SHREG,MAX2870,GPIO,RESERVED,EOPBIT};
+	//reg [23:0] headerCmd = {MODE,LMX,DDS,POT,DAC,ATT,SHREG,MAX2870,GPIO,RESERVED,EOPBIT};
+	reg [23:0] headerCmd = 24'h81811e;
+	wire [16:0] testWordsNum =  headerCmd[21:19]+headerCmd[17:16]+headerCmd[15:12]+headerCmd[10:9]+headerCmd[7:6]+headerCmd[4:3]+headerCmd[2]+headerCmd[1];
 	reg [23:0] spiData;
 	
 	reg	[23:0]	dspSpiData;
@@ -60,7 +63,7 @@ module ExtQSpiMEmul
 //================================================================================
 //  ASSIGNMENTS
 
-assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b1;
+assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b0;
 assign	TxDone_o	=	(txStop & (currState== CMD));
 
 //================================================================================
@@ -198,18 +201,14 @@ always @(*) begin
 
 	TX		:	begin
 					if (txCnt==6'd5) begin
-						nextState  = PAUSE;
+						nextState  = CMD;
 					end	else begin
 						nextState  = TX;
 					end
 				end
         
 	PAUSE	:	begin
-					if (pauseCnt==4'd2) begin
-						nextState  = CMD;
-					end	else begin
-						nextState  = PAUSE;
-					end
+					nextState  = CMD;
 				end
 	endcase
 end

src/src/InterfaceArbiter/ExtSpiMEmul.v

@@ -46,7 +46,7 @@ module ExtSpiMEmul
 //================================================================================
 //  ASSIGNMENTS
 
-assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b1;
+assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b0;
 assign	TxDone_o	=	(txStop & (currState== CMD));
 
 //================================================================================
@@ -165,18 +165,14 @@ always @(*) begin
 
 	TX		:	begin
 					if (txCnt==6'd23) begin
-						nextState  = PAUSE;
+						nextState  = CMD;
 					end	else begin
 						nextState  = TX;
 					end
 				end
         
 	PAUSE	:	begin
-					if (pauseCnt==4'd2) begin
-						nextState  = CMD;
-					end	else begin
-						nextState  = PAUSE;
-					end
+					nextState  = CMD;
 				end
 	endcase
 end

src/src/InterfaceArbiter/InterfaceArbiter.v

@@ -46,11 +46,18 @@ module InterfaceArbiter
 //  REG/WIRE
 
 	localparam [1:0] IDLE = 0;
-	localparam [1:0] DATARX = 1;
+	localparam [1:0] DEL = 1;
+	localparam [1:0] DATARX = 2;
 	
 	reg [OUTWORDWIDTH-1:0] dataRegSSpi;
 	reg [OUTWORDWIDTH-1:0] dataRegQSpi;
+
+	reg [OUTWORDWIDTH-1:0] dataRegSSpiR;
+	reg [OUTWORDWIDTH-1:0] dataRegQSpiR;
 	
+	reg [OUTWORDWIDTH-1:0] dataRegSSpiRR;
+	reg [OUTWORDWIDTH-1:0] dataRegQSpiRR;
+
 	reg [OUTWORDWIDTH-1:0] captRegSspi;
 	
 	reg [QSPIWORDWIDTH-1:0] captReg0;
@@ -176,10 +183,18 @@ module InterfaceArbiter
 		if (Rst_i) begin 
 			spiModeSyncA <= 1'b0;
 			spiModeSyncB <= 1'b0;
+			dataRegSSpiR <= 0;
+			dataRegQSpiR <= 0;
+			dataRegSSpiRR <= 0;
+			dataRegQSpiRR <= 0;
 		end
 		else begin 
 			spiModeSyncA <= spiMode;
 			spiModeSyncB <= spiModeSyncA;
+			dataRegSSpiR  <= captRegSspi;
+			dataRegQSpiR  <= {captReg0,captReg1,captReg2,captReg3};
+			dataRegSSpiRR <= dataRegSSpiR;
+			dataRegQSpiRR <= dataRegQSpiR;
 		end
 	end
 
@@ -187,8 +202,8 @@ module InterfaceArbiter
 		if (!Rst_i) begin
 			dataValReg <= dataVal;
 			if (dataVal) begin
-				dataRegSSpi <= captRegSspi;
-				dataRegQSpi <= {captReg0,captReg1,captReg2,captReg3};
+				dataRegSSpi <= dataRegSSpiRR;
+				dataRegQSpi <= dataRegQSpiRR;
 			end 
 		end else begin
 			dataRegSSpi <= 0;
@@ -199,11 +214,11 @@ module InterfaceArbiter
 
 	always @(posedge Clk_i) begin
 		if (!Rst_i) begin
-			if (currState == IDLE) begin
+			if (currState == DEL) begin
 				if (!spiModeSyncB) begin
-					wordsNum <= dataRegSSpi[17:1];
+					wordsNum <= dataRegSSpiRR[17:1];
 				end else begin
-					wordsNum <= dataRegQSpi[21:19]+dataRegQSpi[17:16]+dataRegQSpi[15:12]+dataRegQSpi[10:9]+dataRegQSpi[7:6]+dataRegQSpi[4:3]+dataRegQSpi[2]+dataRegQSpi[1];
+					wordsNum <= dataRegQSpiRR[21:19]+dataRegQSpiRR[17:16]+dataRegQSpiRR[15:12]+dataRegQSpiRR[10:9]+dataRegQSpiRR[7:6]+dataRegQSpiRR[4:3]+dataRegQSpiRR[2]+dataRegQSpiRR[1];
 				end 
 			end
 		end else begin
@@ -223,13 +238,21 @@ module InterfaceArbiter
 		nextState = IDLE;
 		case(currState)
 		IDLE		:begin
-						if (dataValReg)	begin
-							nextState = DATARX;
+						if (ssCnt == 6)	begin
+							nextState = DEL;
 						end	else begin
 							nextState = IDLE;
 						end
 					end
 
+		DEL		:begin
+						if (dataVal)	begin
+							nextState = DATARX;
+						end	else begin
+							nextState = DEL;
+						end
+					end
+
 		DATARX		:begin
 						if (rxDone) begin
 							nextState  = IDLE;

src/src/InterfaceArbiter/InterfaceArbiterTb.v

@@ -40,8 +40,8 @@ module InterfaceArbiterTb();
 	reg [31:0] delCnt;
 	reg stateCnt;
 	
-	reg Clk100;
-	reg Clk10;
+	reg Clk60;
+	reg Sck60;
 	
 	reg [1:0] currState;
 	reg [1:0] nextState;
@@ -79,22 +79,22 @@ module InterfaceArbiterTb();
 	assign mosi3 = (currState==SINGLE) ? 1'b1:mosi3Q;
 //================================================================================
 //clocks gen
-	always	#5 Clk100	=	~Clk100;	
-	always	#50 Clk10	=	~Clk10;	
+	always	#8.3333333333335 Clk60	=	~Clk60;	
+	always	#8.3333333333335 Sck60	=	~Sck60;	
 	
 	
 //================================================================================
 //  CODING
 
 initial begin
-	Clk100	=	1'b1;
-	Clk10	=	1'b1;
+	Clk60	=	1'b1;
+	Sck60	=	1'b1;
 	rst		=	1'b1;
 #100;
 	rst		=	1'b0;
 end	
 	
-always	@(negedge	Clk100)	begin
+always	@(negedge	Clk60)	begin
 	if	(!rst)		begin
 		tbCnt	<=	tbCnt+1;
 	end	else	begin
@@ -102,7 +102,7 @@ always	@(negedge	Clk100)	begin
 	end
 end
 
-always	@(posedge	Clk100)	begin
+always	@(posedge	Clk60)	begin
 	if	(!rst)		begin
 		if (currState == DELAY) begin
 			delCnt	<=	delCnt+1;
@@ -114,7 +114,7 @@ always	@(posedge	Clk100)	begin
 	end
 end
 
-always	@(negedge	Clk10)	begin
+always	@(negedge	Sck60)	begin
 	if	(!rst)		begin
 		if (txDoneS|txDoneQ) begin
 			stateCnt	<=	stateCnt+1;
@@ -124,14 +124,14 @@ always	@(negedge	Clk10)	begin
 	end
 end
 
-always	@(posedge	Clk100)	begin
+always	@(posedge	Clk60)	begin
 	if	(!rst)		begin
 		case (stateCnt)
 			0:	begin
-					SPIMODE <= 1'b0;
+					SPIMODE <= 1'b1;
 				end
 			1:	begin
-					SPIMODE <= 1'b1;
+					SPIMODE <= 1'b0;
 				end
 			default:begin
 						SPIMODE <= 1'b0;
@@ -142,7 +142,7 @@ always	@(posedge	Clk100)	begin
 	end
 end
 
-always	@(posedge	Clk100)	begin
+always	@(posedge	Clk60)	begin
 	if	(rst)	begin
 		currState	<=	IDLE;
 	end	else	begin
@@ -198,7 +198,7 @@ end
 ExtSpiMEmul SingleSpiSm
 (
 	.Rst_i		(rst),
-	.Clk_i		(Clk10),
+	.Clk_i		(Sck60),
 	
 	.Start_i	((currState==SINGLE)),
 	.TxDone_o	(txDoneS),
@@ -212,7 +212,7 @@ ExtSpiMEmul SingleSpiSm
 ExtQSpiMEmul QuadSpiSm
 (
 	.Rst_i		(rst),
-	.Clk_i		(Clk10),
+	.Clk_i		(Sck60),
 	
 	.Start_i	((currState==QUAD)),
 	.TxDone_o	(txDoneQ),
@@ -229,7 +229,7 @@ ExtQSpiMEmul QuadSpiSm
 InterfaceArbiter InterfaceArbiter
 (
 	.Rst_i		(rst),
-	.Clk_i		(Clk100),
+	.Clk_i		(Clk60),
 	
 	.Sck_i		(sck),
 	.Ss_i		(ss),