Merge branch 'Mikhail/bug_PacketAnalyzer1MosiCntData' of zaytsev.mikhail/SB_TMSG44V1_FPGA into dev

src/src/PacketAnalyzer1Mosi/PacketAnalyzer1Mosi.v

@@ -82,15 +82,21 @@ always @(posedge Clk_i) begin
 		cntData <= 17'b0;
 	end 
 	else if (ValDataFromSpi_i) begin
-		if ((cntData == 0) && (DataFromSpi_i[23] == 0)) begin
-			cntData <= DataFromSpi_i[17:1];
-			devId 	<= DataFromSpi_i[22:18];
-		end
+		if (cntData == 0) begin 
+			if (DataFromSpi_i[23] == 0) begin
+				cntData <= DataFromSpi_i[17:1];
+				devId 	<= DataFromSpi_i[22:18];
+			end
+			else begin
+				cntData <= 5'b0;
+				devId 	<= 17'b0;
+			end
+		end	
 		else begin
 			cntData <= cntData - 1'b1;	
 		end
 	end
-	else if (cntData == 17'b0) begin
+	else if (cntData == 0) begin
 		devId <= 5'b0;
 	end
 end