浏览代码

Добавил управление пином FpgaAmCtrl в основной ветке

Anatoliy Chigirinskiy 11 月之前
父节点
当前提交
926361496c
共有 3 个文件被更改,包括 9 次插入6 次删除
  1. 4 3
      src/constr/SbTmsg.cst
  2. 2 2
      src/src/Gpio1Ctrl/Gpio1Ctrl.v
  3. 3 1
      src/src/Top/TopSbTmsg.v

+ 4 - 3
src/constr/SbTmsg.cst

@@ -1,11 +1,10 @@
 //Copyright (C)2014-2024 Gowin Semiconductor Corporation.
 //Copyright (C)2014-2024 Gowin Semiconductor Corporation.
 //All rights reserved. 
 //All rights reserved. 
 //File Title: Physical Constraints file
 //File Title: Physical Constraints file
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.9.03 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
 //Device: GW1N-9
-//Device Version: C
-//Created Time: Thu 05 02 13:46:56 2024
+//Created Time: Fri 12 27 16:05:36 2024
 
 
 IO_LOC "DataMax2870MixRf2_o" C1;
 IO_LOC "DataMax2870MixRf2_o" C1;
 IO_PORT "DataMax2870MixRf2_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_PORT "DataMax2870MixRf2_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
@@ -49,6 +48,8 @@ IO_LOC "ClkLmx94_o" G2;
 IO_PORT "ClkLmx94_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_PORT "ClkLmx94_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_LOC "CsLmx94_o" F1;
 IO_LOC "CsLmx94_o" F1;
 IO_PORT "CsLmx94_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_PORT "CsLmx94_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
+IO_LOC "FpgaAmCtrl_o" A15;
+IO_PORT "FpgaAmCtrl_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_LOC "DdsSaw1Fpga_o" E1;
 IO_LOC "DdsSaw1Fpga_o" E1;
 IO_PORT "DdsSaw1Fpga_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_PORT "DdsSaw1Fpga_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
 IO_LOC "GpioAdRfV2_o" C16;
 IO_LOC "GpioAdRfV2_o" C16;

+ 2 - 2
src/src/Gpio1Ctrl/Gpio1Ctrl.v

@@ -25,12 +25,12 @@ module Gpio1Ctrl (
 
 
 	input FlagDirectGpio1_i,
 	input FlagDirectGpio1_i,
 
 
-	output reg [21:0] GpioReg_o
+	output reg [23:0] GpioReg_o
 );
 );
 
 
 always @(posedge Clk_i) begin 
 always @(posedge Clk_i) begin 
 	if (ValGpioDataToFifo_i || (FlagDirectGpio1_i && ValDataFromSpi_i)) begin 
 	if (ValGpioDataToFifo_i || (FlagDirectGpio1_i && ValDataFromSpi_i)) begin 
-		GpioReg_o <= Data_i[21:0];
+		GpioReg_o <= Data_i[23:0];
 	end
 	end
 end
 end
 
 

+ 3 - 1
src/src/Top/TopSbTmsg.v

@@ -72,6 +72,7 @@ module TopSbTmsg
 	output GpioAdRfV1_o,
 	output GpioAdRfV1_o,
 	output GpioAdRfV2_o,
 	output GpioAdRfV2_o,
 	output DdsSaw1Fpga_o,
 	output DdsSaw1Fpga_o,
+	output FpgaAmCtrl_o,
 
 
 	//Output SPI devices
 	//Output SPI devices
 	output reg CsLmx94_o,
 	output reg CsLmx94_o,
@@ -124,7 +125,7 @@ localparam [11:0] FIRMWARE_VER	= 12'h1;
 	wire spiDataVal;
 	wire spiDataVal;
 	wire spiDataValSync;
 	wire spiDataValSync;
 	wire [WORDWIDTH-1:0] spiData;
 	wire [WORDWIDTH-1:0] spiData;
-	wire [21:0] gpio1CtrlData;
+	wire [23:0] gpio1CtrlData;
 	
 	
 	wire busyMosi1;
 	wire busyMosi1;
 	wire busyMosi4;
 	wire busyMosi4;
@@ -201,6 +202,7 @@ localparam [11:0] FIRMWARE_VER	= 12'h1;
 //================================================================================
 //================================================================================
 //  ASSIGNMENTS
 //  ASSIGNMENTS
 //================================================================================
 //================================================================================
+assign FpgaAmCtrl_o			= gpio1CtrlData[22];
 assign DdsSaw1Fpga_o 		= gpio1CtrlData[21];
 assign DdsSaw1Fpga_o 		= gpio1CtrlData[21];
 assign GpioAdRfV2_o 		= gpio1CtrlData[20];
 assign GpioAdRfV2_o 		= gpio1CtrlData[20];
 assign GpioAdRfV1_o 		= gpio1CtrlData[19];
 assign GpioAdRfV1_o 		= gpio1CtrlData[19];