Исправлены ошибки в FifoCtrl и SpiM, дополнен тестбенч.

src/src/FifoCtrl/FifoCtrl.v

@@ -24,7 +24,7 @@ module FifoCtrl #(
     input WrClk_i,
     input RdClk_i,
     input Rst_i,
-    input [23:0] Data_i,
+    input [IN_WIDTH-1:0] Data_i,
     input Val_i,
     input BusySpiM_i,
     input FifoFull_i,
@@ -72,24 +72,49 @@ always @(posedge WrClk_i) begin
     if (Rst_i) begin 
         dataReg <= 0;
     end
-    else begin 
-        case (wrCnt)
-        0 : begin 
-            if (Val_i) begin 
-                dataReg[IN_WIDTH-1:0] <= Data_i;
+    else begin
+        if (WR_NUM>1) begin
+            case (WR_NUM)  
+            3: begin
+                case (wrCnt)
+                0 : begin 
+                    if (Val_i) begin 
+                        dataReg[(3*IN_WIDTH)-1:(2*IN_WIDTH)] <= Data_i;
+                    end
+                end
+                1 : begin 
+                    if (Val_i) begin 
+                        dataReg[(2*IN_WIDTH)-1:IN_WIDTH] <= Data_i;
+                    end
+                end
+                2 : begin 
+                    if (Val_i) begin 
+                        dataReg[IN_WIDTH-1:0] <= Data_i;
+                    end
+                end
+                endcase
             end
-        end
-        1 : begin 
-            if (Val_i) begin 
-                dataReg[(2*IN_WIDTH)-1:IN_WIDTH] <= Data_i;
+            2 : begin 
+                case (wrCnt)
+                0: begin 
+                    if (Val_i) begin 
+                        dataReg[(2*IN_WIDTH)-1:IN_WIDTH] <= Data_i;
+                    end
+                end
+                1: begin 
+                    if (Val_i) begin 
+                        dataReg[IN_WIDTH-1:0] <= Data_i;
+                    end
+                end
+                endcase
             end
+            endcase
         end
-        2 : begin 
+        else begin
             if (Val_i) begin 
-                dataReg[(3*IN_WIDTH)-1:(2*IN_WIDTH)] <= Data_i;
+                dataReg[IN_WIDTH-1:0] <= Data_i;
             end
         end
-        endcase
     end
 end
 

src/src/FifoCtrl/FifoCtrl_tb.sv

@@ -3,11 +3,16 @@ module FifoCtrl_tb;
 logic WrClk_i;
 logic RdClkDDS_i;
 logic RdClkLMX_i;
+logic RdClkMax_i;
 logic Rst_i;
-logic [23:0] data;
+logic [23:0] dataForDDS;
+logic [23:0] dataForLMX;
+logic [23:0] dataForMAX;
 logic BusySpiLMX;
 logic BusySpiDDS;
+logic BusySpiMax;
 logic valFromSPI64;
+logic valFromSPI32;
 logic valFromSPI24;
 
 logic wrEnDDS;
@@ -23,21 +28,21 @@ logic fullFlagDDS;
 logic emptyFlagDDS;
 
 logic [23:0] dataToFifo24;
+logic [31:0] dataToFifo32;
 logic [63:0] dataToFifo64;
 logic [23:0] dataFromFifo24;
+logic [31:0] dataFromFifo32;
 logic [63:0] dataFromFifo64;
 
-
-
 logic [6:0] OUT_WIDTH;
 logic [1:0] WR_NUM;
 
-
 //***********************************************
 //	           LOCALPARAMS
 //***********************************************
 localparam FIFTY_MHZ = 20;
 localparam SIXTY_MHZ = 16;
+localparam TWENTY_MHZ = 50;
 
 //***********************************************
 //	           CLOCK GENERATION
@@ -46,12 +51,11 @@ always begin
     #5 WrClk_i = ~WrClk_i;
     #(FIFTY_MHZ/2) RdClkDDS_i = ~RdClkDDS_i;
     #(SIXTY_MHZ/2) RdClkLMX_i = ~RdClkLMX_i;
+    #(TWENTY_MHZ/2) RdClkMax_i = ~RdClkMax_i;
 end
-
 //***********************************************
 //	           DUT INSTANTIATION
 //***********************************************
-
 FifoCtrl#(
     .IN_WIDTH(24),
     .WR_NUM(3),
@@ -60,7 +64,7 @@ FifoCtrl#(
     .WrClk_i(WrClk_i),
     .RdClk_i(RdClkDDS_i),
     .Rst_i(Rst_i),
-    .Data_i(data),
+    .Data_i(dataForDDS),
     .Val_i(valFromSPI64),
     .FifoFull_i(fullFlagDDS),
     .FifoEmpty_i(emptyFlagDDS),
@@ -78,7 +82,7 @@ FifoCtrl #(
     .WrClk_i(WrClk_i),
     .RdClk_i(RdClkLMX_i),
     .Rst_i(Rst_i),
-    .Data_i(data),
+    .Data_i(dataForLMX),
     .Val_i(valFromSPI24),
     .FifoFull_i(fullFlagLMX),
     .FifoEmpty_i(emptyFlagLMX),
@@ -88,6 +92,24 @@ FifoCtrl #(
     .WriteEn_o(wrEnLMX)
 );
 
+FifoCtrl #(
+    .IN_WIDTH(24),
+    .WR_NUM(2),
+    .OUT_WIDTH(32)
+) FifoCtrlMax_inst (
+    .WrClk_i(WrClk_i),
+    .RdClk_i(RdClkMax_i),
+    .Rst_i(Rst_i),
+    .Data_i(dataForMAX),
+    .Val_i(valFromSPI32),
+    .FifoFull_i(fullFlagMax),
+    .FifoEmpty_i(emptyFlagMax),
+    .BusySpiM_i(BusySpiMax),
+    .Data_o(dataToFifo32),
+    .ReadEn_o(rdEnMax),
+    .WriteEn_o(wrEnMax)
+);
+// Depth 16
 FifoLMX FifoLMX_inst (
     .Data(dataToFifo24),
     .WrClk(WrClk_i),
@@ -98,7 +120,7 @@ FifoLMX FifoLMX_inst (
     .Empty(emptyFlagLMX),
     .Full(fullFlagLMX)
 );
-
+// Depth 2
 FifoDDS FifoDDS_inst (
     .Data(dataToFifo64),
     .WrClk(WrClk_i),
@@ -109,6 +131,17 @@ FifoDDS FifoDDS_inst (
     .Empty(emptyFlagDDS),
     .Full(fullFlagDDS)
 );
+//Depth 4
+FifoMax FifoMax_inst (
+    .Data(dataToFifo32),
+    .WrClk(WrClk_i),
+    .RdClk(RdClkMax_i),
+    .WrEn(wrEnMax),
+    .RdEn(rdEnMax),
+    .Q(dataFromFifo32),
+    .Empty(emptyFlagMax),
+    .Full(fullFlagMax)
+);
 
 SpiM #(
     .DATA_WIDTH(24)
@@ -130,13 +163,25 @@ SpiM #(
     .Busy_o(BusySpiDDS)
 );
 
+SpiM #(
+    .DATA_WIDTH(32)
+)SpiMMax_inst(
+    .Clk_i(RdClkMax_i),
+    .Rst_i(Rst_i),
+    .Val_i(rdEnMax),
+    .SpiData_i(dataFromFifo32),
+    .Busy_o(BusySpiMax)
+);
+//***********************************************
+//	           TASKS
+//***********************************************
 task drive_fifo64();
     valFromSPI64 = 1'b0;
     #300;
     wait(!BusySpiDDS)
     @ (posedge WrClk_i)
     valFromSPI64 = 1'b1;
-    data = 24'h123456;
+    dataForDDS = {8'h0, 16'hFFFF};
     #10;
     @(posedge WrClk_i)
     valFromSPI64 = 1'b0;
@@ -144,7 +189,7 @@ task drive_fifo64();
     wait(!BusySpiDDS)
     @ (posedge WrClk_i)
     valFromSPI64 = 1'b1;
-    data = 24'habcdef;
+    dataForDDS = 24'habcdef;
     #10;
     @ (posedge WrClk_i)
     valFromSPI64 = 1'b0;
@@ -152,23 +197,55 @@ task drive_fifo64();
     wait(!BusySpiDDS)
     @ (posedge WrClk_i)
     valFromSPI64 = 1'b1;
-    data = 24'h123456;
+    dataForDDS = 24'h123456;
     #10;
     @(posedge WrClk_i)
     valFromSPI64 = 1'b0;
 endtask
 
+task drive_fifo32();
+    valFromSPI32 = 1'b0;
+    #300;
+    @ (posedge WrClk_i)
+    valFromSPI32 = 1'b1;
+    dataForMAX = {16'h0, 8'h12};
+    #10;
+    @(posedge WrClk_i)
+    valFromSPI32 = 1'b0;
+    #300;
+    @ (posedge WrClk_i)
+    valFromSPI32 = 1'b1;
+    dataForMAX = 24'habcdef;
+    #10;
+    @ (posedge WrClk_i)
+    valFromSPI32 = 1'b0;
+    #300;
+    @ (posedge WrClk_i)
+    valFromSPI32 = 1'b1;
+    dataForMAX = {16'h0, 8'h12};
+    #10;
+    @(posedge WrClk_i)
+    valFromSPI32 = 1'b0;
+    #300;
+    @ (posedge WrClk_i)
+    valFromSPI32 = 1'b1;
+    dataForMAX = $urandom();
+    #10;
+    @(posedge WrClk_i)
+    valFromSPI32 = 1'b0;
+endtask
+
 task drive_fifo24();
     Rst_i = 1'b1;
     valFromSPI24 = 1'b0;
-    data = 24'h0;
+    dataForLMX = 24'h0;
     #200;
     Rst_i = 1'b0;
     #300;
     wait(!BusySpiLMX)
     @ (posedge WrClk_i)
     valFromSPI24 = 1'b1;
-    data = 24'h123456;
+    dataForLMX = 24'h123456;
     #10;
     @(posedge WrClk_i)
     valFromSPI24 = 1'b0;
@@ -176,26 +253,28 @@ task drive_fifo24();
     wait(!BusySpiLMX)
     @ (posedge WrClk_i)
     valFromSPI24 = 1'b1;
-    data = 24'habcdef;
+    dataForLMX = 24'habcdef;
     #10;
     @ (posedge WrClk_i)
     valFromSPI24 = 1'b0;
     #300;
-    wait(!BusySpiLMX)
     @ (posedge WrClk_i)
     valFromSPI24 = 1'b1;
-    data = 24'h123456;
+    dataForLMX = 24'h123456;
     #10;
     @(posedge WrClk_i)
     valFromSPI24 = 1'b0;
 endtask
-
-
+//***********************************************
+//	           INITIALIZATION
+//***********************************************
 initial begin 
     WrClk_i = 1'b1;
     RdClkDDS_i = 1'b1;
     RdClkLMX_i = 1'b1;
+    RdClkMax_i = 1'b1;
     drive_fifo24();
+    drive_fifo32();
     drive_fifo64();
 end
 

src/src/SPIm/SpiM.v

@@ -70,19 +70,11 @@ always @(negedge Clk_i) begin
         ssCnt <= 7'h0;
     end
     else begin
-        if (ssCnt == 0) begin 
-            if (Val_i) begin 
-                ssCnt <= ssCnt + 1;
-            end
-        end
-        else begin 
-            if (ssCnt < DATA_WIDTH) begin 
-                ssCnt <= ssCnt + 1;
-            end
-            else begin 
-                ssCnt <= 7'h0;
-            end
-        end
+        if (!ssReg) begin
+			ssCnt <= ssCnt+1;
+		end else begin
+			ssCnt <= 0;
+		end
     end
 end
 
@@ -107,12 +99,12 @@ always @(negedge Clk_i) begin
         ssReg <= 1'b1;
     end
     else begin 
-        if ((ssCnt < DATA_WIDTH && ssCnt != 0) || Val_i) begin 
-            ssReg <= 1'b0;
-        end
-        else begin 
-            ssReg <= 1'b1;
-        end
+        if (Val_i) begin
+			ssReg <= 0;
+		end
+		if (ssCnt == DATA_WIDTH-1) begin
+			ssReg <= 1;
+		end
     end
 end