Рефакторинг,добавление шапки в SPIm и do-файла

src/src/SPIm/SPIm.v

@@ -1,3 +1,22 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:      TAIR
+// Engineer:    Chigrinskiy A. 
+// 
+// Create Date:    18/04/2024 
+// Design Name: 
+// Module Name:    SPIm
+// Project Name:  SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:  This module implements SPI master interface
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+
 module SPIm #(
     parameter ssNum = 24
 )(
@@ -22,7 +41,6 @@ reg             ssReg;
 reg startFlag;
 reg ssR;
 
-
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
@@ -34,7 +52,6 @@ assign Busy_o = !Ss_o;
 //================================================================================
 //	CODING
 //================================================================================
-
 always @(negedge Clk_i) begin 
     if (Rst_i) begin 
         ssCnt <= 7'h0;

src/src/SPIm/SPIm_tb.do

@@ -0,0 +1,49 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -radix unsigned /SPIm_tb/DUT/ssNum
+add wave -noupdate /SPIm_tb/DUT/Clk_i
+add wave -noupdate /SPIm_tb/DUT/Rst_i
+add wave -noupdate /SPIm_tb/DUT/Val_i
+add wave -noupdate /SPIm_tb/DUT/SpiData_i
+add wave -noupdate /SPIm_tb/DUT/Ss_o
+add wave -noupdate /SPIm_tb/DUT/Mosi_o
+add wave -noupdate /SPIm_tb/DUT/Sck_o
+add wave -noupdate /SPIm_tb/DUT/Busy_o
+add wave -noupdate -radix unsigned /SPIm_tb/DUT/ssCnt
+add wave -noupdate /SPIm_tb/DUT/mosiReg
+add wave -noupdate /SPIm_tb/DUT/ssReg
+add wave -noupdate /SPIm_tb/DUT/startFlag
+add wave -noupdate /SPIm_tb/DUT/ssR
+add wave -noupdate /SPIm_tb/spiQueue
+add wave -noupdate -radix unsigned /SPIm_tb/numOfWords
+add wave -noupdate -divider SPIs
+add wave -noupdate /SPIm_tb/SPIs_inst/Clk_i
+add wave -noupdate /SPIm_tb/SPIs_inst/Rst_i
+add wave -noupdate /SPIm_tb/SPIs_inst/Sck_i
+add wave -noupdate /SPIm_tb/SPIs_inst/Ss_i
+add wave -noupdate /SPIm_tb/SPIs_inst/Mosi0_i
+add wave -noupdate /SPIm_tb/SPIs_inst/Data_o
+add wave -noupdate /SPIm_tb/SPIs_inst/Addr_o
+add wave -noupdate /SPIm_tb/SPIs_inst/DataToRxFifo_o
+add wave -noupdate /SPIm_tb/SPIs_inst/Val_o
+add wave -noupdate /SPIm_tb/SPIs_inst/ssReg
+add wave -noupdate /SPIm_tb/SPIs_inst/ssRegR
+add wave -noupdate /SPIm_tb/SPIs_inst/shiftReg
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {290000 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {163546 ps} {376454 ps}

src/src/SPIm/SPIm_tb.sv

@@ -1,26 +1,22 @@
 `timescale 1ns / 1ps
 module SPIm_tb;
-
-
-
 logic Clk_i;
 logic Rst_i;
-
-
 logic [23:0] spiData;
 
-
+//***********************************************
+//	            LOCALPARAMS
+//***********************************************
 localparam N = 16;
 
-
-
+//***********************************************
+//	            SIGNALS
+//***********************************************
 logic [23:0] randData;
-
 logic [23:0] spiQueue [N-1:0];
 logic busyFromSpi;
 logic valToSpi;
 logic [4:0] numOfWords;
-
 logic sck;
 logic ss;
 logic mosi;
@@ -38,18 +34,13 @@ Packet pkt;
 //***********************************************
 //	           CLOCK GENERATION
 //***********************************************
-
 always begin
     #5 Clk_i = ~Clk_i;
 end
 
-
-
-
 //***********************************************
 //	           INITIALIZATION
 //***********************************************
-
 initial begin 
     Clk_i =1'b1;
     pkt = new();
@@ -94,10 +85,6 @@ always_ff @(posedge Clk_i) begin
     end
 end
 
-
-
-
-
 always_ff @(*) begin 
     if (Rst_i) begin 
         spiData=0;
@@ -109,12 +96,9 @@ always_ff @(*) begin
     end
 end
 
-
-
 //***********************************************
 //	           DUT INSTANTIATION
 //***********************************************
-
 SPIm DUT (
     .Clk_i(Clk_i),
     .Rst_i(Rst_i),
@@ -126,7 +110,6 @@ SPIm DUT (
     .Busy_o(busyFromSpi)
 );
 
-
 SPIs_tb SPIs_inst (
     .Clk_i(Clk_i),
     .Rst_i(Rst_i),
@@ -137,14 +120,4 @@ SPIs_tb SPIs_inst (
     .Val_o(valFromDUT)
 );
 
-
-
-
-
-
-
-
-
-
-
 endmodule

src/src/SPIm/SPIs_tb.v

@@ -15,12 +15,9 @@ module SPIs_tb (
 //================================================================================
 //	REG/WIRE
 //================================================================================
-
     reg ssReg;
     reg ssRegR;  
     reg [23:0] shiftReg;
-    
- 
 
 //===============================================================================
 //  ASSIGNMENTS
@@ -37,9 +34,6 @@ module SPIs_tb (
     	ssRegR	<=	ssReg;
     end
 
-
-
-
     always @(posedge Clk_i) begin 
         if (Rst_i) begin 
             Data_o <= 18'h0;
@@ -62,7 +56,6 @@ module SPIs_tb (
         end
     end
 
-
     always @(posedge Sck_i or posedge Rst_i) begin 
         if (Rst_i) begin 
             shiftReg<= 24'h0;
@@ -77,9 +70,6 @@ module SPIs_tb (
         end
     end
     
-        
-
-
     always @(posedge Clk_i) begin
         if (ssReg && !ssRegR) begin 
             Val_o <= 1'b1;
@@ -89,7 +79,4 @@ module SPIs_tb (
         end
     end
 
-
-
-
     endmodule