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Изменение логики работы двунаправленной линии. Изменения в тестбенче.

Anatoliy Chigirinskiy hai 1 ano
pai
achega
a4311927c9
Modificáronse 2 ficheiros con 22 adicións e 8 borrados
  1. 4 4
      src/src/Top/TopSbTmsg.v
  2. 18 4
      src/src/Top/TopSbTmsgTb.sv

+ 4 - 4
src/src/Top/TopSbTmsg.v

@@ -152,11 +152,11 @@ assign CtrlAmSw3_o 			= gpio1CtrlData[2];
 assign RfSw2_o 				= gpio1CtrlData[1];
 assign RfSw1_o 				= gpio1CtrlData[0];
 
-assign anyFlag = flagDirectTemp | flagDirectMax | flagDirectDds | flagDirectLmx | flagDirectGpio2;
+assign anyFlag = flagDirectTemp | flagDirectMax | flagDirectDds | flagDirectLmx | flagDirectGpio2;//Debug-only
 
 assign RfLd_o = MisoLdLmx_i && MisoLdMax2870_i;
-assign Miso1_io = (anyFlag) ? misoReg : 1'bz;
-assign AnyFlag_o = anyFlag;
+assign Mosi1_io = misoReg;
+assign AnyFlag_o = anyFlag;//Debug-only
 
 //================================================================================
 //  CODING
@@ -181,7 +181,7 @@ always @(*) begin
 			misoReg = misoGpio2;
 		end
 		else begin 
-			misoReg = 1'b0;
+			misoReg = 1'bz;
 		end
 	end
 end

+ 18 - 4
src/src/Top/TopSbTmsgTb.sv

@@ -1,4 +1,4 @@
-`timescale 1ns/1ps
+`timescale 1ns/1ns
 
 module TopSbTmsgTb(inout Mosi1_io);
    parameter CLK_PERIOD = 8.13; // Clock period in ns
@@ -47,6 +47,8 @@ module TopSbTmsgTb(inout Mosi1_io);
     wire locked;
     wire rstInit;
 
+    logic mosi1Reg;
+
     logic [16:0] trCnt;
     logic [4:0] trCntSync;
 
@@ -109,6 +111,7 @@ localparam [23:0] TempSensHeader        = {1'h0, DeviceIdTemp, TempSensWordNum,
 localparam [23:0] InitLMX2594Header     = {1'h0, DeviceIdLmx2594, Lmx2594InitWordNum, 1'h1};
 localparam [23:0] InitDDSHeader         = {1'h0, DeviceIdDDS, DDSInitWordNum, 1'h1};
 localparam [23:0] InitMAX2870Header     = {1'h0, DeviceIdMax2870, MaxInitWordNum, 1'h1};
+// localparam [23:0] InitPot
 localparam [3:0]  LMXWordNum = 4'd14;
 localparam [1:0]  DDSWordNum = 2'd3;
 localparam        POTWordNum = 1'd1;
@@ -172,7 +175,7 @@ initial begin
       #(CLK_PERIOD*10) Rst_i = 0;
       #(300000-60) rstForFPGA = 1;
       #(CLK_PERIOD*74) rstForFPGA = 0;
-      #(20) Start_i = 1; // Start SPI transaction
+      #(165000) Start_i = 1; // Start SPI transaction
     
   end
 //***********************************************
@@ -188,13 +191,24 @@ always_ff @(posedge Clk10) begin
     end
 end
 
+always_comb begin 
+    if (Rst_i) begin 
+        mosi1Reg = 0;
+    end
+    else begin 
+        mosi1Reg = Mosi1_io;
+    end
+end
+
+
+
 genvar i;
 always_comb begin 
     if (Rst_i) begin 
         WidthSel_i = 2'd0;
     end
     else begin 
-        if (trCnt > 152 && trCnt < 159) begin 
+        if (trCnt > 158 && trCnt < 165) begin 
             WidthSel_i = 2'd3;
         end
         else begin 
@@ -208,7 +222,7 @@ always_comb begin
         modeSel = 0;
     end
     else begin 
-        if (trCnt == 159) begin 
+        if (trCnt == 165) begin 
             modeSel = 1;
         end
     end