Реализован модуль разбора пакетов для режима 1Mosi. Написан тестбенч. Написана документация.

src/src/PacketAnalyzer1Mosi/PacketAnalyzer1Mosi.v

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+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		Zaytsev Mikhail
+// 
+// Create Date:		19/04/2024 
+// Design Name: 
+// Module Name:		PacketAnalyzer1Mosi 
+// Project Name:	SB_TMSG44V1_FPGA
+// Target Devices:	Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:		The module analyzes the data on the DataFromSpi_i[23:0] bus using the 
+// 					ValDataFromSpi_i validity signal.  When a configuration packet is received, 
+// 					data is captured into the two internal registers devId and cntData. 
+// 					Next, the cntData register is decremented with each incoming data parcel 
+// 					until it becomes zero. If the value in the register is equal to zero means 
+// 					that the module is ready to receive the next configuration packet. 
+// 					As long as the value of cntData is not equal to zero at the output of the 
+// 					module is active signal FlagDirect..._o for the device specified in the 
+// 					register devId. The module also has an output signal Busy_o, which signals 
+// 					that the module is in the state of processing data received in 1MOSI mode.
+// Dependencies:	
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module PacketAnalyzer1Mosi (
+	input Clk_i,
+	input Rst_i,
+
+	input [23:0] DataFromSpi_i,
+	input ValDataFromSpi_i,
+
+	input BusyMosi4_i,
+
+	output reg FlagDirectLmx_o,
+	output reg FlagDirectDds_o,
+	output reg FlagDirectPot_o,
+	output reg FlagDirectDac_o,
+	output reg FlagDirectAtt_o,
+	output reg FlagDirectShReg_o,
+	output reg FlagDirectMax_o,
+	output reg FlagDirectGpio_o,
+	output reg FlagDirectTemp_o,
+
+	output reg Busy_o
+);
+
+//==========================================
+// Registers
+//==========================================
+reg [4:0] devId;
+reg [16:0] cntData;
+
+//==========================================
+// Wires
+//==========================================
+
+//==========================================
+// Parameters
+//==========================================
+localparam DEV_ID_LMX 		= 5'd0;
+localparam DEV_ID_DDS 		= 5'd1;
+localparam DEV_ID_POT 		= 5'd2;
+localparam DEV_ID_DAC 		= 5'd3;
+localparam DEV_ID_ATT 		= 5'd4;
+localparam DEV_ID_SH_REG 	= 5'd5;
+localparam DEV_ID_MAX 		= 5'd6;
+localparam DEV_ID_GPIO 		= 5'd7;
+localparam DEV_ID_TEMP 		= 5'd8;
+
+//==========================================
+// Assignments
+//==========================================
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+always @(posedge Clk_i) begin
+	if(Rst_i || BusyMosi4_i) begin
+		devId 	<= 5'b0;
+		cntData <= 17'b0;
+	end 
+	else if (ValDataFromSpi_i) begin
+		if ((cntData == 0) && (DataFromSpi_i[23] == 0)) begin
+			cntData <= DataFromSpi_i[17:1];
+			devId 	<= DataFromSpi_i[22:18];
+		end
+		else begin
+			cntData <= cntData - 1'b1;	
+		end
+	end
+	else if (cntData == 17'b0) begin
+		devId <= 5'b0;
+	end
+end
+
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		FlagDirectLmx_o 	<= 1'b0;
+		FlagDirectDds_o 	<= 1'b0;
+		FlagDirectPot_o 	<= 1'b0;
+		FlagDirectDac_o 	<= 1'b0;
+		FlagDirectAtt_o 	<= 1'b0;
+		FlagDirectShReg_o 	<= 1'b0;
+		FlagDirectMax_o 	<= 1'b0;
+		FlagDirectGpio_o 	<= 1'b0;
+		FlagDirectTemp_o 	<= 1'b0;
+	end
+	else if (cntData != 0) begin
+		case (devId)
+			DEV_ID_LMX : begin
+				FlagDirectLmx_o <= 1'b1;
+			end
+			DEV_ID_DDS : begin
+				FlagDirectDds_o <= 1'b1;
+			end
+			DEV_ID_POT : begin
+				FlagDirectPot_o <= 1'b1;
+			end
+			DEV_ID_DAC : begin
+				FlagDirectDac_o <= 1'b1;
+			end
+			DEV_ID_ATT : begin
+				FlagDirectAtt_o <= 1'b1;
+			end
+			DEV_ID_SH_REG : begin
+				FlagDirectShReg_o <= 1'b1;
+			end
+			DEV_ID_MAX : begin
+				FlagDirectMax_o <= 1'b1;
+			end
+			DEV_ID_GPIO : begin
+				FlagDirectGpio_o <= 1'b1;
+			end
+			DEV_ID_TEMP : begin
+				FlagDirectTemp_o <= 1'b1;
+			end
+			default : begin
+				FlagDirectLmx_o 	<= 1'b0;
+				FlagDirectDds_o 	<= 1'b0;
+				FlagDirectPot_o 	<= 1'b0;
+				FlagDirectDac_o 	<= 1'b0;
+				FlagDirectAtt_o 	<= 1'b0;
+				FlagDirectShReg_o 	<= 1'b0;
+				FlagDirectMax_o 	<= 1'b0;
+				FlagDirectGpio_o 	<= 1'b0;
+				FlagDirectTemp_o 	<= 1'b0;
+			end
+		endcase
+	end
+	else begin
+		FlagDirectLmx_o 	<= 1'b0;
+		FlagDirectDds_o 	<= 1'b0;
+		FlagDirectPot_o 	<= 1'b0;
+		FlagDirectDac_o 	<= 1'b0;
+		FlagDirectAtt_o 	<= 1'b0;
+		FlagDirectShReg_o 	<= 1'b0;
+		FlagDirectMax_o 	<= 1'b0;
+		FlagDirectGpio_o 	<= 1'b0;
+		FlagDirectTemp_o 	<= 1'b0;
+	end
+end
+
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		Busy_o <= 1'b0;
+	end
+	else if (cntData != 0) begin
+		Busy_o <= 1'b1;
+	end
+	else begin
+		Busy_o <= 1'b0;
+	end
+end
+
+endmodule

src/src/PacketAnalyzer1Mosi/PacketAnalyzer1MosiTb.v

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+`timescale 1ns / 1ns
+
+module PacketAnalyzer1MosiTb (
+);
+
+localparam [4:0] LMX_ID 		= 5'd0;
+localparam [4:0] DDS_ID 		= 5'd1;
+localparam [4:0] POT_ID 		= 5'd2;
+localparam [4:0] DAC_ID 		= 5'd3;
+localparam [4:0] ATT_ID 		= 5'd4;
+localparam [4:0] SH_REG_ID 		= 5'd5;
+localparam [4:0] MAX_ID 		= 5'd6;
+localparam [4:0] GPIO_ID 		= 5'd7;
+localparam [4:0] TEMP_ID 		= 5'd8;
+
+//===============USER DEFINE===================
+localparam [16:0] CNT_DATA_WORDS = 7;
+localparam [4:0] DEV_ID = ATT_ID;
+//===============USER DEFINE_END===============
+
+localparam MODE_4MOSI = 1'b1;
+localparam MODE_1MOSI = 1'b0;
+
+//===============USER DEFINE===================
+localparam MODE_SELECT = MODE_1MOSI;
+//===============USER DEFINE_END===============
+
+localparam [23:0] CFG_REG = {MODE_SELECT, DEV_ID, CNT_DATA_WORDS, 1'b0};
+
+reg clkMain_tb;
+reg rstMain_tb;
+reg busyMosi4_tb;
+
+reg [23:0] DataFromSpi_tb;
+reg ValDataFromSpi_tb;
+
+reg [4:0] test;
+
+always #10 clkMain_tb = ~clkMain_tb;
+
+initial begin
+	clkMain_tb = 0;
+	rstMain_tb = 1;
+	busyMosi4_tb = 0;
+	test = DEV_ID;
+	#100
+	rstMain_tb = 0;
+end
+
+reg	[7:0]	state; 
+reg	[63:0]	cnt;
+reg	[63:0]	countState;
+
+always @(posedge clkMain_tb) begin
+	if (rstMain_tb) begin
+		cnt <= 0;
+		state <= 0;
+		ValDataFromSpi_tb <= 0;	
+		DataFromSpi_tb <= 0;
+		countState <= 0;
+	end
+	else begin
+		case(state)
+			0: begin
+				DataFromSpi_tb <= CFG_REG;
+
+				if (cnt == 6) begin
+					cnt <= 0;
+					ValDataFromSpi_tb <= 1;
+					state <= state + 1;
+				end
+				else begin
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			1: begin
+				ValDataFromSpi_tb <= 0;
+				if (cnt == 1) begin
+					cnt <= 0;
+					state <= state + 1;
+				end
+				else begin
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			2: begin
+				DataFromSpi_tb <= 24'hA; //DATA0
+
+				if (cnt == 6) begin
+					cnt <= 0;
+					ValDataFromSpi_tb <= 1;
+					state <= state + 1;
+					countState <= countState + 1;
+				end
+				else begin
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			3: begin
+				ValDataFromSpi_tb <= 0;
+				if (countState == CNT_DATA_WORDS) begin
+					state <= 5;
+				end
+				else if (cnt == 1) begin
+					cnt <= 0;
+					state <= state + 1;
+				end
+				else begin
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			4: begin
+				DataFromSpi_tb <= 24'hF; //DATA1
+
+				if (cnt == 6) begin
+					cnt <= 0;
+					ValDataFromSpi_tb <= 1;
+					state <= state + 1;
+					countState <= countState + 1;
+				end
+				else begin
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			5: begin
+				ValDataFromSpi_tb <= 0;
+				if (countState == CNT_DATA_WORDS) begin
+					state <= state;
+				end
+				else if (cnt == 1) begin
+					cnt <= 0;
+					state <= 2;
+				end
+				else begin
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+		endcase
+	end
+end
+
+PacketAnalyzer1Mosi DUT (
+	.Clk_i					(clkMain_tb),	
+	.Rst_i					(rstMain_tb),	
+	
+	.DataFromSpi_i 			(DataFromSpi_tb),
+	.ValDataFromSpi_i 		(ValDataFromSpi_tb),
+	
+	.BusyMosi4_i			(busyMosi4_tb),
+
+	.FlagDirectLmx_o		(),
+	.FlagDirectDds_o		(),
+	.FlagDirectPot_o		(),
+	.FlagDirectDac_o		(),
+	.FlagDirectAtt_o		(),
+	.FlagDirectShReg_o		(),
+	.FlagDirectMax_o		(),
+	.FlagDirectGpio_o		(),
+	.FlagDirectTemp_o		(),
+
+	.Busy_o					()
+);
+
+
+endmodule

src/src/PacketAnalyzer1Mosi/PacketAnalyzer1MosiWave.do

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+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /PacketAnalyzer1MosiTb/DUT/Clk_i
+add wave -noupdate /PacketAnalyzer1MosiTb/DUT/Rst_i
+add wave -noupdate -radix binary /PacketAnalyzer1MosiTb/DUT/DataFromSpi_i
+add wave -noupdate /PacketAnalyzer1MosiTb/DUT/ValDataFromSpi_i
+add wave -noupdate /PacketAnalyzer1MosiTb/DUT/BusyMosi4_i
+add wave -noupdate /PacketAnalyzer1MosiTb/DUT/FlagDirectLmx_o
+add wave -noupdate /PacketAnalyzer1MosiTb/DUT/FlagDirectDds_o
+add wave -noupdate /PacketAnalyzer1MosiTb/DUT/FlagDirectPot_o
+add wave -noupdate /PacketAnalyzer1MosiTb/DUT/FlagDirectDac_o
+add wave -noupdate /PacketAnalyzer1MosiTb/DUT/FlagDirectAtt_o
+add wave -noupdate /PacketAnalyzer1MosiTb/DUT/FlagDirectShReg_o
+add wave -noupdate /PacketAnalyzer1MosiTb/DUT/FlagDirectMax_o
+add wave -noupdate /PacketAnalyzer1MosiTb/DUT/FlagDirectGpio_o
+add wave -noupdate /PacketAnalyzer1MosiTb/DUT/FlagDirectTemp_o
+add wave -noupdate /PacketAnalyzer1MosiTb/DUT/Busy_o
+add wave -noupdate /PacketAnalyzer1MosiTb/DUT/devId
+add wave -noupdate /PacketAnalyzer1MosiTb/DUT/cntData
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {175 ns} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 183
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ns} {3439 ns}