Добавлены обёртки для модулей Fifo, FifoCtrl и SpiM для каждого устройства. Fifo переключены в режим First Word Fallthrough

src/src/FifoCtrl/Fifo16x3/Fifo16x3.ipc

@@ -17,7 +17,7 @@ ECCSelected=false
 EmptyClear=1
 EmptySet=1
 EnReset=true
-FirstWordFallThrough=false
+FirstWordFallThrough=true
 FullClear=1
 FullSet=1
 LANG=0
@@ -28,7 +28,7 @@ ReadDataWidth=16
 ReadDepth=2
 ResetSynchronization=true
 SSRAM=false
-StandardFIFO=true
+StandardFIFO=false
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
 WriteDataWidth=16

src/src/FifoCtrl/Fifo16x3/Fifo16x3.v

@@ -1,7 +1,7 @@
 //
 //Written by GowinSynthesis
 //Tool Version "V1.9.9.02"
-//Wed Apr 24 12:55:54 2024
+//Thu Apr 25 16:04:59 2024
 
 //Source file index table:
 //file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
@@ -17,119 +17,129 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+t/bYNDjO0d+SB5/il7zBD/3fBQDGuJm2Z5KM7Q==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=5808)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6368)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module Fifo16x3 (
   Data,

src/src/FifoCtrl/Fifo16x3/Fifo16x3.vo

@@ -2,7 +2,7 @@
 //All rights reserved.
 //File Title: Post-PnR Simulation Model file
 //Tool Version: V1.9.9.02
-//Created Time: Wed Apr 24 12:55:54 2024
+//Created Time: Thu Apr 25 16:04:59 2024
 
 `timescale 100 ps/100 ps
 module Fifo16x3(
@@ -37,30 +37,30 @@ wire VCC;
 wire WrClk;
 wire WrEn;
 wire \fifo_inst/n20_5 ;
-wire \fifo_inst/n24_3 ;
-wire \fifo_inst/n167_3 ;
-wire \fifo_inst/n218_4 ;
+wire \fifo_inst/n26_4 ;
+wire \fifo_inst/n217_4 ;
 wire \fifo_inst/rempty_val ;
 wire \fifo_inst/wfull_val_7 ;
 wire \fifo_inst/wfull_val1 ;
 wire \fifo_inst/wfull_val1_0 ;
 wire \fifo_inst/Full_1 ;
 wire \fifo_inst/Equal.wbinnext_0_7 ;
-wire \fifo_inst/rbin_num_next_0_9 ;
-wire \fifo_inst/rempty_val1 ;
+wire \fifo_inst/rempty_val_8 ;
 wire \fifo_inst/wfull_val1_2 ;
 wire \fifo_inst/wfull_val1_3 ;
 wire \fifo_inst/Full_1_2 ;
 wire \fifo_inst/Full_2 ;
 wire \fifo_inst/n4_6 ;
 wire \fifo_inst/n9_6 ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [0:0] \fifo_inst/Equal.wgraynext ;
+wire [1:0] \fifo_inst/rbin_num_next ;
 wire [1:1] \fifo_inst/Equal.wbinnext ;
-wire [1:1] \fifo_inst/rbin_num_next ;
-wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [1:0] \fifo_inst/reset_r ;
 wire [1:0] \fifo_inst/reset_w ;
 wire [1:0] \fifo_inst/rbin_num ;
+wire [1:0] \fifo_inst/Equal.rq1_wptr ;
+wire [1:0] \fifo_inst/Equal.rq2_wptr ;
 wire [0:0] \fifo_inst/rptr ;
 wire [1:0] \fifo_inst/wptr ;
 wire [0:0] \fifo_inst/Equal.wbin ;
@@ -82,39 +82,41 @@ LUT4 \fifo_inst/n20_s1  (
 	.F(\fifo_inst/n20_5 )
 );
 defparam \fifo_inst/n20_s1 .INIT=16'h5300;
-LUT2 \fifo_inst/n24_s0  (
-	.I0(Empty),
-	.I1(RdEn),
-	.F(\fifo_inst/n24_3 )
+LUT3 \fifo_inst/n26_s1  (
+	.I0(RdEn),
+	.I1(Empty),
+	.I2(\fifo_inst/rempty_val ),
+	.F(\fifo_inst/n26_4 )
+);
+defparam \fifo_inst/n26_s1 .INIT=8'h0E;
+LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
+	.I0(\fifo_inst/rbin_num [0]),
+	.I1(\fifo_inst/rbin_num_next [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
 );
-defparam \fifo_inst/n24_s0 .INIT=4'h4;
+defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
 LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
-	.I0(\fifo_inst/n20_5 ),
-	.I1(\fifo_inst/Equal.wbin [0]),
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wgraynext [0])
 );
 defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
-LUT2 \fifo_inst/n167_s0  (
-	.I0(\fifo_inst/rempty_val ),
-	.I1(\fifo_inst/reset_r [1]),
-	.F(\fifo_inst/n167_3 )
-);
-defparam \fifo_inst/n167_s0 .INIT=4'hE;
-LUT2 \fifo_inst/n218_s1  (
+LUT2 \fifo_inst/n217_s1  (
 	.I0(\fifo_inst/reset_w [1]),
 	.I1(\fifo_inst/wfull_val_7 ),
-	.F(\fifo_inst/n218_4 )
+	.F(\fifo_inst/n217_4 )
 );
-defparam \fifo_inst/n218_s1 .INIT=4'h4;
+defparam \fifo_inst/n217_s1 .INIT=4'h4;
 LUT4 \fifo_inst/rempty_val_s3  (
-	.I0(\fifo_inst/wptr [0]),
-	.I1(\fifo_inst/rptr [0]),
-	.I2(\fifo_inst/wptr [1]),
-	.I3(\fifo_inst/rbin_num [1]),
+	.I0(\fifo_inst/Equal.rq2_wptr [1]),
+	.I1(\fifo_inst/rempty_val_8 ),
+	.I2(\fifo_inst/Equal.rq2_wptr [0]),
+	.I3(\fifo_inst/rbin_num_next [0]),
 	.F(\fifo_inst/rempty_val )
 );
-defparam \fifo_inst/rempty_val_s3 .INIT=16'h9009;
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
 LUT4 \fifo_inst/wfull_val_s3  (
 	.I0(\fifo_inst/wptr [0]),
 	.I1(\fifo_inst/wptr [1]),
@@ -131,8 +133,8 @@ LUT3 \fifo_inst/wfull_val1_s9  (
 );
 defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
 LUT3 \fifo_inst/wfull_val1_s10  (
-	.I0(\fifo_inst/wfull_val1_0 ),
-	.I1(\fifo_inst/wfull_val_7 ),
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/wfull_val1_0 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/wfull_val1_0 )
 );
@@ -145,48 +147,47 @@ LUT3 \fifo_inst/Full_d_s  (
 );
 defparam \fifo_inst/Full_d_s .INIT=8'hAC;
 LUT3 \fifo_inst/Full_s8  (
-	.I0(\fifo_inst/Full_1 ),
-	.I1(\fifo_inst/wfull_val_7 ),
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/Full_1 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/Full_1 )
 );
 defparam \fifo_inst/Full_s8 .INIT=8'h0E;
+LUT3 \fifo_inst/rbin_num_next_0_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next [0])
+);
+defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
+LUT3 \fifo_inst/rbin_num_next_1_s2  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
 LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
-	.I0(\fifo_inst/n20_5 ),
-	.I1(\fifo_inst/Equal.wbin [0]),
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
 	.F(\fifo_inst/Equal.wbinnext_0_7 )
 );
 defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
 LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
-	.I0(\fifo_inst/n20_5 ),
-	.I1(\fifo_inst/Equal.wbin [0]),
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wbinnext [1])
 );
 defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
-LUT4 \fifo_inst/rbin_num_next_1_s3  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.I3(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/rbin_num_next [1])
-);
-defparam \fifo_inst/rbin_num_next_1_s3 .INIT=16'hBF40;
-LUT3 \fifo_inst/rbin_num_next_0_s4  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rbin_num_next_0_9 )
-);
-defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
-LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.I3(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/Equal.rgraynext [0])
+LUT4 \fifo_inst/rempty_val_s4  (
+	.I0(\fifo_inst/Equal.rq2_wptr [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rempty_val_8 )
 );
-defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
+defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
 DFFP \fifo_inst/reset_r_0_s0  (
 	.D(GND),
 	.CLK(\fifo_inst/n4_6 ),
@@ -216,12 +217,40 @@ DFFC \fifo_inst/rbin_num_1_s0  (
 );
 defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/rbin_num_0_s0  (
-	.D(\fifo_inst/rbin_num_next_0_9 ),
+	.D(\fifo_inst/rbin_num_next [0]),
 	.CLK(RdClk),
 	.CLEAR(\fifo_inst/reset_r [1]),
 	.Q(\fifo_inst/rbin_num [0])
 );
 defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
+	.D(\fifo_inst/wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [1])
+);
+defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
+	.D(\fifo_inst/wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [0])
+);
+defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [1])
+);
+defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [0])
+);
+defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/rptr_0_s0  (
 	.D(\fifo_inst/Equal.rgraynext [0]),
 	.CLK(RdClk),
@@ -250,17 +279,10 @@ DFFC \fifo_inst/Equal.wbin_0_s0  (
 	.Q(\fifo_inst/Equal.wbin [0])
 );
 defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
-DFFP \fifo_inst/rempty_val1_s0  (
-	.D(\fifo_inst/rempty_val ),
-	.CLK(RdClk),
-	.PRESET(\fifo_inst/n167_3 ),
-	.Q(\fifo_inst/rempty_val1 )
-);
-defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
 DFFP \fifo_inst/Empty_s0  (
-	.D(\fifo_inst/rempty_val1 ),
+	.D(\fifo_inst/rempty_val ),
 	.CLK(RdClk),
-	.PRESET(\fifo_inst/n167_3 ),
+	.PRESET(\fifo_inst/reset_r [1]),
 	.Q(Empty)
 );
 defparam \fifo_inst/Empty_s0 .INIT=1'b1;
@@ -281,7 +303,7 @@ defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
 	.D(\fifo_inst/wfull_val_7 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n218_4 ),
+	.PRESET(\fifo_inst/n217_4 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -295,7 +317,7 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n218_4 ),
+	.PRESET(\fifo_inst/n217_4 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
@@ -304,14 +326,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
 	.CEA(\fifo_inst/n20_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n24_3 ),
+	.CEB(\fifo_inst/n26_4 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[15:0]}),
 	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, GND, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND}),
 	.DO({\fifo_inst/DO [31:16], Q[15:0]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;

src/src/FifoCtrl/Fifo16x3/Fifo16x3_tmp.v

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.9.02
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-
-//Created Time: Wed Apr 24 12:55:54 2024
+//Created Time: Thu Apr 25 16:04:59 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/FifoCtrl/Fifo16x3/temp/FIFOHS/Fifo16x3.vg

@@ -1,7 +1,7 @@
 //
 //Written by GowinSynthesis
 //Tool Version "V1.9.9.02"
-//Wed Apr 24 12:55:54 2024
+//Thu Apr 25 16:04:59 2024
 
 //Source file index table:
 //file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
@@ -17,119 +17,129 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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++9xK15Qi3TKg78a8SyeARfBIq/ZyaIeoIf0QdOas+rARU4dzyqiiiy7sm42o4pyAR9PegR9hQGE7
+t/bYNDjO0d+SB5/il7zBD/3fBQDGuJm2Z5KM7Q==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=5808)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6368)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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+IsmCBviST/NaLrbecssUM4rq97mLxpIwmAMLvgPpLBryi3SVk7UkqtY=
 `pragma protect end_protected
 module Fifo16x3 (
   Data,

src/src/FifoCtrl/Fifo16x3/temp/FIFOHS/Fifo16x3_syn_resource.html

@@ -31,7 +31,7 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 </tr>
 <tr>
 <td class="label">Fifo16x3 (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
-<td align = "center">16</td>
+<td align = "center">19</td>
 <td align = "center">-</td>
 <td align = "center">18</td>
 <td align = "center">-</td>

src/src/FifoCtrl/Fifo16x3/temp/FIFOHS/Fifo16x3_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="Fifo16x3" Register="16" Lut="18" Bsram="1" T_Register="16(16)" T_Lut="18(18)" T_Bsram="1(1)"/>
+<Module name="Fifo16x3" Register="19" Lut="18" Bsram="1" T_Register="19(19)" T_Lut="18(18)" T_Bsram="1(1)"/>

src/src/FifoCtrl/Fifo16x3/temp/FIFOHS/Fifo16x3_tmp.v

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.9.02
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-
-//Created Time: Wed Apr 24 12:55:54 2024
+//Created Time: Thu Apr 25 16:04:59 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/FifoCtrl/Fifo16x3/temp/FIFOHS/fifo_define.v

@@ -1,4 +1,5 @@
 `define module_name Fifo16x3
 `define EBR_BASED
+`define FWFT
 `define En_Reset
 `define Reset_Synchronization

src/src/FifoCtrl/FifoCtrl.v

@@ -133,26 +133,40 @@ always @(posedge WrClk_i) begin
     end
 end
 
-always @(*) begin
+always @(posedge RdClk_i) begin
     if (Rst_i) begin 
-        ReadEn_o = 1'b0;
+        ReadEn_o <= 1'b0;
     end
     else begin  
         if (!FifoEmpty_i && !BusySpiM_i) begin 
-            ReadEn_o = 1'b1;
+            ReadEn_o <= 1'b1;
         end
         else begin 
-            ReadEn_o = 1'b0;
+            ReadEn_o <= 1'b0;
         end
     end
 end
 
+// always @(posedge RdClk_i) begin 
+//     if (Rst_i) begin 
+//         ValRdData_o <= 1'b0;
+//     end
+//     else begin 
+//         if (ReadEn_o) begin 
+//             ValRdData_o <= 1'b1;
+//         end
+//         else begin 
+//             ValRdData_o <= 1'b0;
+//         end
+//     end
+// end
+
 always @(posedge RdClk_i) begin 
     if (Rst_i) begin 
         ValRdData_o <= 1'b0;
     end
-    else begin 
-        if (ReadEn_o) begin 
+    else begin
+        if (!FifoEmpty_i && !BusySpiM_i) begin 
             ValRdData_o <= 1'b1;
         end
         else begin 

src/src/FifoCtrl/FifoDDS/FifoDDS.ipc

@@ -17,7 +17,7 @@ ECCSelected=false
 EmptyClear=1
 EmptySet=1
 EnReset=true
-FirstWordFallThrough=false
+FirstWordFallThrough=true
 FullClear=1
 FullSet=1
 LANG=0
@@ -28,7 +28,7 @@ ReadDataWidth=64
 ReadDepth=2
 ResetSynchronization=true
 SSRAM=false
-StandardFIFO=true
+StandardFIFO=false
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
 WriteDataWidth=64

src/src/FifoCtrl/FifoDDS/FifoDDS.v

@@ -1,7 +1,7 @@
 //
 //Written by GowinSynthesis
 //Tool Version "V1.9.9.02"
-//Wed Apr 24 12:25:14 2024
+//Thu Apr 25 16:06:49 2024
 
 //Source file index table:
 //file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
@@ -17,131 +17,141 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+Xs0Rq7KS+nMjcFcl7E3CRA+0+XO4iCSxRkS+iA==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=6464)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7024)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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+LRGQicV+gHNsvlv4TECqtnqqZqgkRXeldlnyK/Y9mjESOJQ1OIe8MhcwT4b20Vl2P1py+F9jKfO/
+oKfKyYFnrYFv9/F+n8Qcek7r/otFn0Wj1qT5wf7usRgJTwkHXCyL8SbA1AGh1psjuMscmFxypv48
+jDe3NzcqnyPhKFq9QcyyGN0vGKx3+QYXKpuAvmJfhy9AGg1Fv2ejOyMnTAhL5AvK7xsA3Kr7K2vP
+r4tdrYskR2dAUpSIYGeUG1+sJHiMR2vr4nTUdZnza9OpxpP+SPkGhWUnU7F44NhRa6sPzyFlFTf9
+/2tZZq/+AAV0UOm+wiA/vAfKtm1nhy1HZytz++HDWndjyVS8P1eBVjeLz0nEPzoHNCo0z7wyoM6M
+5mSOYpSbOU9/rdCX8cYGkhH7yB9sKqtCxZCc/gwDBOz9BWyyCN/jlMNpNcKU8dJnd1UW+k30Dfe+
+YwohlEW9vyWGEyTsoSpsfuAhKYvtYOyCc+IUL/vfSrAQaNVubcbTT6lsC1THlrZ3ySsmvT1TFklm
+T9ZqWaCxLvwlLmayK5zWxgfqKwYgAZ9PmnF4Khi+U+jjbRmbs1MBhlmJo34J7KGLHwMWneuILuh2
+iLUPBdF8uBJEd7ciU2q2Ws21+sOosGY7QOmGw6nD1m1AoGfgK4g2f2llKh8yy3+eK5ZGBz00XGS9
+MfQjNng50F1VlTN/o+fg6tvHTSDWss05nBPe4MIR9VOBgPTXRv1knHYkmeAf5NXJY/CSbW+6sEYi
+PIR/gWGjKu5+95ZFq4NRzu0pGgcTD1TwA3XddAlM3yxlZZStapiGFXcG0h3YlFq0dUz0lCcBQtDs
+lbcixeFyH+/GSK+GSVCmMklEsbrCKhxV/miDQpjybm0tNCB2a1du2OAM/TNWVI4gHohAnvyWQKJe
+3v7KBb4D/R8IPr3HnmWScXZhWo/vspzpk3uF4gmEHxfWmIlq2uP3d4pgJLafwaitSZmd2Ha+jt/p
+L5gHqXEFjnBD7DRlTsMJGMHoFhU9erTrr9NenvQTx96NYcD6tQGhPse1Xhzm8fjsWocmm2zFNi/N
+yLUXcvMsVv4bPZxPFw==
 `pragma protect end_protected
 module FifoDDS (
   Data,

src/src/FifoCtrl/FifoDDS/FifoDDS.vo

@@ -2,7 +2,7 @@
 //All rights reserved.
 //File Title: Post-PnR Simulation Model file
 //Tool Version: V1.9.9.02
-//Created Time: Wed Apr 24 12:25:14 2024
+//Created Time: Thu Apr 25 16:06:49 2024
 
 `timescale 100 ps/100 ps
 module FifoDDS(
@@ -37,30 +37,30 @@ wire VCC;
 wire WrClk;
 wire WrEn;
 wire \fifo_inst/n20_5 ;
-wire \fifo_inst/n24_3 ;
-wire \fifo_inst/n359_3 ;
-wire \fifo_inst/n458_4 ;
+wire \fifo_inst/n26_4 ;
+wire \fifo_inst/n457_4 ;
 wire \fifo_inst/rempty_val ;
 wire \fifo_inst/wfull_val_7 ;
 wire \fifo_inst/wfull_val1 ;
 wire \fifo_inst/wfull_val1_0 ;
 wire \fifo_inst/Full_1 ;
 wire \fifo_inst/Equal.wbinnext_0_7 ;
-wire \fifo_inst/rbin_num_next_0_9 ;
-wire \fifo_inst/rempty_val1 ;
+wire \fifo_inst/rempty_val_8 ;
 wire \fifo_inst/wfull_val1_2 ;
 wire \fifo_inst/wfull_val1_3 ;
 wire \fifo_inst/Full_1_2 ;
 wire \fifo_inst/Full_2 ;
 wire \fifo_inst/n4_6 ;
 wire \fifo_inst/n9_6 ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [0:0] \fifo_inst/Equal.wgraynext ;
+wire [1:0] \fifo_inst/rbin_num_next ;
 wire [1:1] \fifo_inst/Equal.wbinnext ;
-wire [1:1] \fifo_inst/rbin_num_next ;
-wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [1:0] \fifo_inst/reset_r ;
 wire [1:0] \fifo_inst/reset_w ;
 wire [1:0] \fifo_inst/rbin_num ;
+wire [1:0] \fifo_inst/Equal.rq1_wptr ;
+wire [1:0] \fifo_inst/Equal.rq2_wptr ;
 wire [0:0] \fifo_inst/rptr ;
 wire [1:0] \fifo_inst/wptr ;
 wire [0:0] \fifo_inst/Equal.wbin ;
@@ -81,39 +81,41 @@ LUT4 \fifo_inst/n20_s1  (
 	.F(\fifo_inst/n20_5 )
 );
 defparam \fifo_inst/n20_s1 .INIT=16'h5300;
-LUT2 \fifo_inst/n24_s0  (
-	.I0(Empty),
-	.I1(RdEn),
-	.F(\fifo_inst/n24_3 )
+LUT3 \fifo_inst/n26_s1  (
+	.I0(RdEn),
+	.I1(Empty),
+	.I2(\fifo_inst/rempty_val ),
+	.F(\fifo_inst/n26_4 )
+);
+defparam \fifo_inst/n26_s1 .INIT=8'h0E;
+LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
+	.I0(\fifo_inst/rbin_num [0]),
+	.I1(\fifo_inst/rbin_num_next [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
 );
-defparam \fifo_inst/n24_s0 .INIT=4'h4;
+defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
 LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
-	.I0(\fifo_inst/n20_5 ),
-	.I1(\fifo_inst/Equal.wbin [0]),
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wgraynext [0])
 );
 defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
-LUT2 \fifo_inst/n359_s0  (
-	.I0(\fifo_inst/rempty_val ),
-	.I1(\fifo_inst/reset_r [1]),
-	.F(\fifo_inst/n359_3 )
-);
-defparam \fifo_inst/n359_s0 .INIT=4'hE;
-LUT2 \fifo_inst/n458_s1  (
+LUT2 \fifo_inst/n457_s1  (
 	.I0(\fifo_inst/reset_w [1]),
 	.I1(\fifo_inst/wfull_val_7 ),
-	.F(\fifo_inst/n458_4 )
+	.F(\fifo_inst/n457_4 )
 );
-defparam \fifo_inst/n458_s1 .INIT=4'h4;
+defparam \fifo_inst/n457_s1 .INIT=4'h4;
 LUT4 \fifo_inst/rempty_val_s3  (
-	.I0(\fifo_inst/wptr [0]),
-	.I1(\fifo_inst/rptr [0]),
-	.I2(\fifo_inst/wptr [1]),
-	.I3(\fifo_inst/rbin_num [1]),
+	.I0(\fifo_inst/Equal.rq2_wptr [1]),
+	.I1(\fifo_inst/rempty_val_8 ),
+	.I2(\fifo_inst/Equal.rq2_wptr [0]),
+	.I3(\fifo_inst/rbin_num_next [0]),
 	.F(\fifo_inst/rempty_val )
 );
-defparam \fifo_inst/rempty_val_s3 .INIT=16'h9009;
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
 LUT4 \fifo_inst/wfull_val_s3  (
 	.I0(\fifo_inst/wptr [0]),
 	.I1(\fifo_inst/wptr [1]),
@@ -130,8 +132,8 @@ LUT3 \fifo_inst/wfull_val1_s9  (
 );
 defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
 LUT3 \fifo_inst/wfull_val1_s10  (
-	.I0(\fifo_inst/wfull_val1_0 ),
-	.I1(\fifo_inst/wfull_val_7 ),
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/wfull_val1_0 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/wfull_val1_0 )
 );
@@ -144,48 +146,47 @@ LUT3 \fifo_inst/Full_d_s  (
 );
 defparam \fifo_inst/Full_d_s .INIT=8'hAC;
 LUT3 \fifo_inst/Full_s8  (
-	.I0(\fifo_inst/Full_1 ),
-	.I1(\fifo_inst/wfull_val_7 ),
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/Full_1 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/Full_1 )
 );
 defparam \fifo_inst/Full_s8 .INIT=8'h0E;
+LUT3 \fifo_inst/rbin_num_next_0_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next [0])
+);
+defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
+LUT3 \fifo_inst/rbin_num_next_1_s2  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
 LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
-	.I0(\fifo_inst/n20_5 ),
-	.I1(\fifo_inst/Equal.wbin [0]),
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
 	.F(\fifo_inst/Equal.wbinnext_0_7 )
 );
 defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
 LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
-	.I0(\fifo_inst/n20_5 ),
-	.I1(\fifo_inst/Equal.wbin [0]),
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wbinnext [1])
 );
 defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
-LUT4 \fifo_inst/rbin_num_next_1_s3  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.I3(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/rbin_num_next [1])
-);
-defparam \fifo_inst/rbin_num_next_1_s3 .INIT=16'hBF40;
-LUT3 \fifo_inst/rbin_num_next_0_s4  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rbin_num_next_0_9 )
-);
-defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
-LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.I3(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/Equal.rgraynext [0])
+LUT4 \fifo_inst/rempty_val_s4  (
+	.I0(\fifo_inst/Equal.rq2_wptr [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rempty_val_8 )
 );
-defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
+defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
 DFFP \fifo_inst/reset_r_0_s0  (
 	.D(GND),
 	.CLK(\fifo_inst/n4_6 ),
@@ -215,12 +216,40 @@ DFFC \fifo_inst/rbin_num_1_s0  (
 );
 defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/rbin_num_0_s0  (
-	.D(\fifo_inst/rbin_num_next_0_9 ),
+	.D(\fifo_inst/rbin_num_next [0]),
 	.CLK(RdClk),
 	.CLEAR(\fifo_inst/reset_r [1]),
 	.Q(\fifo_inst/rbin_num [0])
 );
 defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
+	.D(\fifo_inst/wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [1])
+);
+defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
+	.D(\fifo_inst/wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [0])
+);
+defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [1])
+);
+defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [0])
+);
+defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/rptr_0_s0  (
 	.D(\fifo_inst/Equal.rgraynext [0]),
 	.CLK(RdClk),
@@ -249,17 +278,10 @@ DFFC \fifo_inst/Equal.wbin_0_s0  (
 	.Q(\fifo_inst/Equal.wbin [0])
 );
 defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
-DFFP \fifo_inst/rempty_val1_s0  (
-	.D(\fifo_inst/rempty_val ),
-	.CLK(RdClk),
-	.PRESET(\fifo_inst/n359_3 ),
-	.Q(\fifo_inst/rempty_val1 )
-);
-defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
 DFFP \fifo_inst/Empty_s0  (
-	.D(\fifo_inst/rempty_val1 ),
+	.D(\fifo_inst/rempty_val ),
 	.CLK(RdClk),
-	.PRESET(\fifo_inst/n359_3 ),
+	.PRESET(\fifo_inst/reset_r [1]),
 	.Q(Empty)
 );
 defparam \fifo_inst/Empty_s0 .INIT=1'b1;
@@ -280,7 +302,7 @@ defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
 	.D(\fifo_inst/wfull_val_7 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n458_4 ),
+	.PRESET(\fifo_inst/n457_4 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -294,7 +316,7 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n458_4 ),
+	.PRESET(\fifo_inst/n457_4 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
@@ -303,14 +325,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
 	.CEA(\fifo_inst/n20_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n24_3 ),
+	.CEB(\fifo_inst/n26_4 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({Data[31:0]}),
 	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND, GND}),
 	.DO({Q[31:0]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
@@ -324,14 +346,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_1_s  (
 	.CEA(\fifo_inst/n20_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n24_3 ),
+	.CEB(\fifo_inst/n26_4 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({Data[63:32]}),
 	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND, GND}),
 	.DO({Q[63:32]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .READ_MODE=1'b0;

src/src/FifoCtrl/FifoDDS/FifoDDS_tmp.v

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.9.02
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-
-//Created Time: Wed Apr 24 12:25:14 2024
+//Created Time: Thu Apr 25 16:06:49 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/FifoCtrl/FifoDDS/temp/FIFOHS/FIFOHS.prj

@@ -10,7 +10,7 @@
     <OptionList>
         <Option type="disable_insert_pad" value="1"/>
         <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
-        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/fifo_hs/temp/FIFOHS"/>
+        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/FifoDDS/temp/FIFOHS"/>
         <Option type="output_file" value="FifoDDS.vg"/>
         <Option type="output_template" value="FifoDDS_tmp.v"/>
         <Option type="ram_balance" value="1"/>

src/src/FifoCtrl/FifoDDS/temp/FIFOHS/FifoDDS.log

@@ -39,7 +39,7 @@ WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_
 WARN  (AG0101) : The netlist is not one directed acyclic graph
 [80%] Tech-Mapping Phase 3 completed
 [90%] Tech-Mapping Phase 4 completed
-[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\fifo_hs\temp\FIFOHS\FifoDDS.vg" completed
-Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\fifo_hs\temp\FIFOHS\FifoDDS_tmp.v" completed
-[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\fifo_hs\temp\FIFOHS\FifoDDS_syn.rpt.html" completed
+[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoDDS\temp\FIFOHS\FifoDDS.vg" completed
+Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoDDS\temp\FIFOHS\FifoDDS_tmp.v" completed
+[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoDDS\temp\FIFOHS\FifoDDS_syn.rpt.html" completed
 GowinSynthesis finish

src/src/FifoCtrl/FifoDDS/temp/FIFOHS/FifoDDS.vg

@@ -1,7 +1,7 @@
 //
 //Written by GowinSynthesis
 //Tool Version "V1.9.9.02"
-//Wed Apr 24 12:25:14 2024
+//Thu Apr 25 16:06:49 2024
 
 //Source file index table:
 //file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
@@ -17,131 +17,141 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
-k1kSHEK6wLFQInHGt7VHC6fSnyD9mPxFLm3NjikHsWB3svUi80t+yPqX4bNxt4eZ/9G3QzVcAx5+
-c/hbq0FUbFlQvkhEKVeagGCWqvLtSu3ilV6woUFeFnzYQ9iXJmIv2A9DXzY4g8qcNQWaG7BTzMA4
-tkoaYcw3gv/wiVt51WY0hFDORuRkcL+PEQ/jxyXh7wG5S+/mCKIPOfKtJv2nSeDPXepflgq7vTuO
-e94b++3KKawa+mY7ITsnj7YPfh1r3h1FFyS02zu26krg14zR/VX+X4J1gHMSchub29vSXXyzG8sG
-3lcjaqbvI4T9REBx2R3WmlHRx2Hq0N3AFEWgOQ==
+bhm5ZxuHD5fe6lKy2Dq5AwHxacJ1cWMwBMX9H8GmdL4lnDV2AKUKXoXHJPX5qkh7Ng/EuDXlf3tq
+XgChMGXHxhGKlXwTDGbPZ7rg+R+CLwCXNxLjHDLHZj7jAwx16WNjn6S5gfS7ZWNO/UifNMSnMT3R
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+aNSO4thTEH7/k6gA0a1Hr9Kwu6d3XW6q2dZH78mYOaedKNxNSU95OsQ/GrR3fobX7P5Bxrf3upgd
+Xs0Rq7KS+nMjcFcl7E3CRA+0+XO4iCSxRkS+iA==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=6464)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7024)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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+yLUXcvMsVv4bPZxPFw==
 `pragma protect end_protected
 module FifoDDS (
   Data,

src/src/FifoCtrl/FifoDDS/temp/FIFOHS/FifoDDS_syn_resource.html

@@ -31,7 +31,7 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 </tr>
 <tr>
 <td class="label">FifoDDS (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
-<td align = "center">16</td>
+<td align = "center">19</td>
 <td align = "center">-</td>
 <td align = "center">18</td>
 <td align = "center">-</td>

src/src/FifoCtrl/FifoDDS/temp/FIFOHS/FifoDDS_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="FifoDDS" Register="16" Lut="18" Bsram="2" T_Register="16(16)" T_Lut="18(18)" T_Bsram="2(2)"/>
+<Module name="FifoDDS" Register="19" Lut="18" Bsram="2" T_Register="19(19)" T_Lut="18(18)" T_Bsram="2(2)"/>

src/src/FifoCtrl/FifoDDS/temp/FIFOHS/FifoDDS_tmp.v

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.9.02
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-
-//Created Time: Wed Apr 24 12:25:14 2024
+//Created Time: Thu Apr 25 16:06:49 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/FifoCtrl/FifoDDS/temp/FIFOHS/fifo_define.v

@@ -1,4 +1,5 @@
 `define module_name FifoDDS
 `define EBR_BASED
+`define FWFT
 `define En_Reset
 `define Reset_Synchronization

src/src/FifoCtrl/FifoLMX/FifoLMX.ipc

@@ -17,7 +17,7 @@ ECCSelected=false
 EmptyClear=1
 EmptySet=1
 EnReset=true
-FirstWordFallThrough=false
+FirstWordFallThrough=true
 FullClear=1
 FullSet=1
 LANG=0
@@ -28,7 +28,7 @@ ReadDataWidth=24
 ReadDepth=16
 ResetSynchronization=true
 SSRAM=false
-StandardFIFO=true
+StandardFIFO=false
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
 WriteDataWidth=24

src/src/FifoCtrl/FifoLMX/FifoLMX.v

@@ -1,7 +1,7 @@
 //
 //Written by GowinSynthesis
 //Tool Version "V1.9.9.02"
-//Wed Apr 24 12:23:21 2024
+//Thu Apr 25 16:07:21 2024
 
 //Source file index table:
 //file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
@@ -17,225 +17,246 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+Eeo9r6zKZBCzzoX/vEjCCVRH/vbTUoQQ9buY6g==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=11824)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=13040)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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+iquJKrJAOuQAmJm6Dbw/7b7Bf5o03PviM2gY4OBRgfCcMxEADJT1Tcslq6E=
 `pragma protect end_protected
 module FifoLMX (
   Data,

src/src/FifoCtrl/FifoLMX/FifoLMX.vo

@@ -2,7 +2,7 @@
 //All rights reserved.
 //File Title: Post-PnR Simulation Model file
 //Tool Version: V1.9.9.02
-//Created Time: Wed Apr 24 12:23:21 2024
+//Created Time: Thu Apr 25 16:07:21 2024
 
 `timescale 100 ps/100 ps
 module FifoLMX(
@@ -37,47 +37,46 @@ wire VCC;
 wire WrClk;
 wire WrEn;
 wire \fifo_inst/n23_5 ;
-wire \fifo_inst/n27_3 ;
+wire \fifo_inst/n29_4 ;
 wire \fifo_inst/wfull_val ;
-wire \fifo_inst/n277_3 ;
-wire \fifo_inst/n372_4 ;
+wire \fifo_inst/n371_4 ;
 wire \fifo_inst/wfull_val1 ;
 wire \fifo_inst/wfull_val1_0 ;
 wire \fifo_inst/Full_1 ;
 wire \fifo_inst/Equal.wbinnext_0_7 ;
-wire \fifo_inst/Equal.rgraynext_2_4 ;
+wire \fifo_inst/Equal.rgraynext_1_4 ;
 wire \fifo_inst/Equal.wgraynext_1_4 ;
 wire \fifo_inst/Equal.wgraynext_2_4 ;
 wire \fifo_inst/Equal.wgraynext_3_4 ;
 wire \fifo_inst/wfull_val_4 ;
 wire \fifo_inst/wfull_val_5 ;
-wire \fifo_inst/n372_5 ;
+wire \fifo_inst/n371_5 ;
 wire \fifo_inst/wfull_val1_16 ;
 wire \fifo_inst/Full_11 ;
-wire \fifo_inst/rbin_num_next_0_9 ;
 wire \fifo_inst/rempty_val ;
-wire \fifo_inst/rempty_val1 ;
 wire \fifo_inst/wfull_val1_2 ;
 wire \fifo_inst/wfull_val1_3 ;
 wire \fifo_inst/Full_1_2 ;
 wire \fifo_inst/Full_2 ;
-wire \fifo_inst/n128_1_SUM ;
-wire \fifo_inst/n128_3 ;
-wire \fifo_inst/n129_1_SUM ;
-wire \fifo_inst/n129_3 ;
 wire \fifo_inst/n130_1_SUM ;
 wire \fifo_inst/n130_3 ;
 wire \fifo_inst/n131_1_SUM ;
 wire \fifo_inst/n131_3 ;
+wire \fifo_inst/n132_1_SUM ;
+wire \fifo_inst/n132_3 ;
+wire \fifo_inst/n133_1_SUM ;
+wire \fifo_inst/n133_3 ;
 wire \fifo_inst/n4_6 ;
 wire \fifo_inst/n9_6 ;
 wire [3:0] \fifo_inst/Equal.rgraynext ;
 wire [3:0] \fifo_inst/Equal.wgraynext ;
-wire [4:1] \fifo_inst/rbin_num_next ;
+wire [4:0] \fifo_inst/rbin_num_next ;
 wire [4:1] \fifo_inst/Equal.wbinnext ;
 wire [1:0] \fifo_inst/reset_r ;
 wire [1:0] \fifo_inst/reset_w ;
 wire [4:0] \fifo_inst/rbin_num ;
+wire [4:0] \fifo_inst/Equal.rq1_wptr ;
+wire [4:0] \fifo_inst/Equal.rq2_wptr ;
 wire [3:0] \fifo_inst/rptr ;
 wire [4:0] \fifo_inst/wptr ;
 wire [3:0] \fifo_inst/Equal.wbin ;
@@ -99,29 +98,29 @@ LUT4 \fifo_inst/n23_s1  (
 	.F(\fifo_inst/n23_5 )
 );
 defparam \fifo_inst/n23_s1 .INIT=16'h5300;
-LUT2 \fifo_inst/n27_s0  (
-	.I0(Empty),
-	.I1(RdEn),
-	.F(\fifo_inst/n27_3 )
-);
-defparam \fifo_inst/n27_s0 .INIT=4'h4;
-LUT4 \fifo_inst/Equal.rgraynext_1_s0  (
-	.I0(\fifo_inst/n27_3 ),
-	.I1(\fifo_inst/rbin_num [0]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.I3(\fifo_inst/rbin_num [2]),
+LUT3 \fifo_inst/n29_s1  (
+	.I0(RdEn),
+	.I1(Empty),
+	.I2(\fifo_inst/rempty_val ),
+	.F(\fifo_inst/n29_4 )
+);
+defparam \fifo_inst/n29_s1 .INIT=8'h0E;
+LUT3 \fifo_inst/Equal.rgraynext_1_s0  (
+	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
+	.I1(\fifo_inst/rbin_num_next [1]),
+	.I2(\fifo_inst/rbin_num [2]),
 	.F(\fifo_inst/Equal.rgraynext [1])
 );
-defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=16'h07F8;
+defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=8'h1E;
 LUT3 \fifo_inst/Equal.rgraynext_2_s0  (
-	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
+	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
 	.I1(\fifo_inst/rbin_num [2]),
 	.I2(\fifo_inst/rbin_num [3]),
 	.F(\fifo_inst/Equal.rgraynext [2])
 );
 defparam \fifo_inst/Equal.rgraynext_2_s0 .INIT=8'h1E;
 LUT4 \fifo_inst/Equal.rgraynext_3_s0  (
-	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
+	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
 	.I1(\fifo_inst/rbin_num [2]),
 	.I2(\fifo_inst/rbin_num [3]),
 	.I3(\fifo_inst/rbin_num [4]),
@@ -167,19 +166,13 @@ LUT4 \fifo_inst/wfull_val_s0  (
 	.F(\fifo_inst/wfull_val )
 );
 defparam \fifo_inst/wfull_val_s0 .INIT=16'h6000;
-LUT2 \fifo_inst/n277_s0  (
-	.I0(\fifo_inst/rempty_val ),
-	.I1(\fifo_inst/reset_r [1]),
-	.F(\fifo_inst/n277_3 )
-);
-defparam \fifo_inst/n277_s0 .INIT=4'hE;
-LUT3 \fifo_inst/n372_s1  (
+LUT3 \fifo_inst/n371_s1  (
 	.I0(\fifo_inst/wfull_val_4 ),
 	.I1(\fifo_inst/wfull_val_5 ),
-	.I2(\fifo_inst/n372_5 ),
-	.F(\fifo_inst/n372_4 )
+	.I2(\fifo_inst/n371_5 ),
+	.F(\fifo_inst/n371_4 )
 );
-defparam \fifo_inst/n372_s1 .INIT=8'h80;
+defparam \fifo_inst/n371_s1 .INIT=8'h80;
 LUT3 \fifo_inst/wfull_val1_s9  (
 	.I0(\fifo_inst/wfull_val1_3 ),
 	.I1(\fifo_inst/wfull_val1_2 ),
@@ -189,7 +182,7 @@ LUT3 \fifo_inst/wfull_val1_s9  (
 defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
 LUT4 \fifo_inst/wfull_val1_s10  (
 	.I0(\fifo_inst/wfull_val_5 ),
-	.I1(\fifo_inst/n372_5 ),
+	.I1(\fifo_inst/n371_5 ),
 	.I2(\fifo_inst/wfull_val_4 ),
 	.I3(\fifo_inst/wfull_val1_16 ),
 	.F(\fifo_inst/wfull_val1_0 )
@@ -204,27 +197,42 @@ LUT3 \fifo_inst/Full_d_s  (
 defparam \fifo_inst/Full_d_s .INIT=8'hAC;
 LUT4 \fifo_inst/Full_s8  (
 	.I0(\fifo_inst/wfull_val_5 ),
-	.I1(\fifo_inst/n372_5 ),
+	.I1(\fifo_inst/n371_5 ),
 	.I2(\fifo_inst/wfull_val_4 ),
 	.I3(\fifo_inst/Full_11 ),
 	.F(\fifo_inst/Full_1 )
 );
 defparam \fifo_inst/Full_s8 .INIT=16'hFF80;
-LUT2 \fifo_inst/rbin_num_next_2_s3  (
-	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
+LUT3 \fifo_inst/rbin_num_next_0_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next [0])
+);
+defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
+LUT4 \fifo_inst/rbin_num_next_1_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s5 .INIT=16'hBF40;
+LUT2 \fifo_inst/rbin_num_next_2_s5  (
+	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
 	.I1(\fifo_inst/rbin_num [2]),
 	.F(\fifo_inst/rbin_num_next [2])
 );
-defparam \fifo_inst/rbin_num_next_2_s3 .INIT=4'h6;
-LUT3 \fifo_inst/rbin_num_next_3_s3  (
-	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
+defparam \fifo_inst/rbin_num_next_2_s5 .INIT=4'h6;
+LUT3 \fifo_inst/rbin_num_next_3_s5  (
+	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
 	.I1(\fifo_inst/rbin_num [2]),
 	.I2(\fifo_inst/rbin_num [3]),
 	.F(\fifo_inst/rbin_num_next [3])
 );
-defparam \fifo_inst/rbin_num_next_3_s3 .INIT=8'h78;
+defparam \fifo_inst/rbin_num_next_3_s5 .INIT=8'h78;
 LUT4 \fifo_inst/rbin_num_next_4_s2  (
-	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
+	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
 	.I1(\fifo_inst/rbin_num [2]),
 	.I2(\fifo_inst/rbin_num [3]),
 	.I3(\fifo_inst/rbin_num [4]),
@@ -259,14 +267,14 @@ LUT4 \fifo_inst/Equal.wbinnext_4_s2  (
 	.F(\fifo_inst/Equal.wbinnext [4])
 );
 defparam \fifo_inst/Equal.wbinnext_4_s2 .INIT=16'hBF40;
-LUT4 \fifo_inst/Equal.rgraynext_2_s1  (
+LUT4 \fifo_inst/Equal.rgraynext_1_s1  (
 	.I0(Empty),
 	.I1(RdEn),
 	.I2(\fifo_inst/rbin_num [0]),
 	.I3(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/Equal.rgraynext_2_4 )
+	.F(\fifo_inst/Equal.rgraynext_1_4 )
 );
-defparam \fifo_inst/Equal.rgraynext_2_s1 .INIT=16'h4000;
+defparam \fifo_inst/Equal.rgraynext_1_s1 .INIT=16'h4000;
 LUT2 \fifo_inst/Equal.wgraynext_1_s1  (
 	.I0(WrEn),
 	.I1(\fifo_inst/Equal.wbin [0]),
@@ -304,13 +312,13 @@ LUT4 \fifo_inst/wfull_val_s2  (
 	.F(\fifo_inst/wfull_val_5 )
 );
 defparam \fifo_inst/wfull_val_s2 .INIT=16'h0990;
-LUT3 \fifo_inst/n372_s2  (
+LUT3 \fifo_inst/n371_s2  (
 	.I0(\fifo_inst/reset_w [1]),
 	.I1(\fifo_inst/wptr [4]),
 	.I2(\fifo_inst/rbin_num [4]),
-	.F(\fifo_inst/n372_5 )
+	.F(\fifo_inst/n371_5 )
 );
-defparam \fifo_inst/n372_s2 .INIT=8'h14;
+defparam \fifo_inst/n371_s2 .INIT=8'h14;
 LUT2 \fifo_inst/wfull_val1_s11  (
 	.I0(\fifo_inst/reset_w [1]),
 	.I1(\fifo_inst/wfull_val1_0 ),
@@ -331,33 +339,18 @@ LUT4 \fifo_inst/Equal.wbinnext_1_s4  (
 	.F(\fifo_inst/Equal.wbinnext [1])
 );
 defparam \fifo_inst/Equal.wbinnext_1_s4 .INIT=16'hBF40;
-LUT4 \fifo_inst/rbin_num_next_1_s4  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.I3(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/rbin_num_next [1])
-);
-defparam \fifo_inst/rbin_num_next_1_s4 .INIT=16'hBF40;
-LUT3 \fifo_inst/rbin_num_next_0_s4  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rbin_num_next_0_9 )
-);
-defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
 LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
 	.I0(Empty),
 	.I1(RdEn),
 	.I2(\fifo_inst/rbin_num [0]),
-	.I3(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num_next [1]),
 	.F(\fifo_inst/Equal.rgraynext [0])
 );
-defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
+defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h4BB4;
 LUT3 \fifo_inst/rempty_val_s2  (
-	.I0(\fifo_inst/wptr [4]),
-	.I1(\fifo_inst/rbin_num [4]),
-	.I2(\fifo_inst/n131_3 ),
+	.I0(\fifo_inst/rbin_num_next [4]),
+	.I1(\fifo_inst/Equal.rq2_wptr [4]),
+	.I2(\fifo_inst/n133_3 ),
 	.F(\fifo_inst/rempty_val )
 );
 defparam \fifo_inst/rempty_val_s2 .INIT=8'h09;
@@ -411,12 +404,82 @@ DFFC \fifo_inst/rbin_num_1_s0  (
 );
 defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/rbin_num_0_s0  (
-	.D(\fifo_inst/rbin_num_next_0_9 ),
+	.D(\fifo_inst/rbin_num_next [0]),
 	.CLK(RdClk),
 	.CLEAR(\fifo_inst/reset_r [1]),
 	.Q(\fifo_inst/rbin_num [0])
 );
 defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_4_s0  (
+	.D(\fifo_inst/wptr [4]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [4])
+);
+defparam \fifo_inst/Equal.rq1_wptr_4_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_3_s0  (
+	.D(\fifo_inst/wptr [3]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [3])
+);
+defparam \fifo_inst/Equal.rq1_wptr_3_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_2_s0  (
+	.D(\fifo_inst/wptr [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [2])
+);
+defparam \fifo_inst/Equal.rq1_wptr_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
+	.D(\fifo_inst/wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [1])
+);
+defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
+	.D(\fifo_inst/wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [0])
+);
+defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_4_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [4]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [4])
+);
+defparam \fifo_inst/Equal.rq2_wptr_4_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_3_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [3]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [3])
+);
+defparam \fifo_inst/Equal.rq2_wptr_3_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_2_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [2])
+);
+defparam \fifo_inst/Equal.rq2_wptr_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [1])
+);
+defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [0])
+);
+defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/rptr_3_s0  (
 	.D(\fifo_inst/Equal.rgraynext [3]),
 	.CLK(RdClk),
@@ -508,17 +571,10 @@ DFFC \fifo_inst/Equal.wbin_0_s0  (
 	.Q(\fifo_inst/Equal.wbin [0])
 );
 defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
-DFFP \fifo_inst/rempty_val1_s0  (
-	.D(\fifo_inst/rempty_val ),
-	.CLK(RdClk),
-	.PRESET(\fifo_inst/n277_3 ),
-	.Q(\fifo_inst/rempty_val1 )
-);
-defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
 DFFP \fifo_inst/Empty_s0  (
-	.D(\fifo_inst/rempty_val1 ),
+	.D(\fifo_inst/rempty_val ),
 	.CLK(RdClk),
-	.PRESET(\fifo_inst/n277_3 ),
+	.PRESET(\fifo_inst/reset_r [1]),
 	.Q(Empty)
 );
 defparam \fifo_inst/Empty_s0 .INIT=1'b1;
@@ -539,7 +595,7 @@ defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
 	.D(\fifo_inst/wfull_val ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n372_4 ),
+	.PRESET(\fifo_inst/n371_4 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -553,7 +609,7 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n372_4 ),
+	.PRESET(\fifo_inst/n371_4 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
@@ -562,14 +618,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
 	.CEA(\fifo_inst/n23_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n27_3 ),
+	.CEB(\fifo_inst/n29_4 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({GND, GND, GND, GND, GND, GND, GND, GND, Data[23:0]}),
 	.ADA({GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [3:0], GND, VCC, VCC, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, \fifo_inst/rbin_num [3:0], GND, GND, GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [3:0], GND, GND, GND, GND, GND}),
 	.DO({\fifo_inst/DO [31:24], Q[23:0]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
@@ -578,42 +634,42 @@ defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=32;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
-ALU \fifo_inst/n128_s0  (
-	.I0(\fifo_inst/wptr [0]),
-	.I1(\fifo_inst/rptr [0]),
-	.I3(GND),
-	.CIN(GND),
-	.COUT(\fifo_inst/n128_3 ),
-	.SUM(\fifo_inst/n128_1_SUM )
-);
-defparam \fifo_inst/n128_s0 .ALU_MODE=3;
-ALU \fifo_inst/n129_s0  (
-	.I0(\fifo_inst/wptr [1]),
-	.I1(\fifo_inst/rptr [1]),
-	.I3(GND),
-	.CIN(\fifo_inst/n128_3 ),
-	.COUT(\fifo_inst/n129_3 ),
-	.SUM(\fifo_inst/n129_1_SUM )
-);
-defparam \fifo_inst/n129_s0 .ALU_MODE=3;
 ALU \fifo_inst/n130_s0  (
-	.I0(\fifo_inst/wptr [2]),
-	.I1(\fifo_inst/rptr [2]),
+	.I0(\fifo_inst/Equal.rgraynext [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [0]),
 	.I3(GND),
-	.CIN(\fifo_inst/n129_3 ),
+	.CIN(GND),
 	.COUT(\fifo_inst/n130_3 ),
 	.SUM(\fifo_inst/n130_1_SUM )
 );
 defparam \fifo_inst/n130_s0 .ALU_MODE=3;
 ALU \fifo_inst/n131_s0  (
-	.I0(\fifo_inst/wptr [3]),
-	.I1(\fifo_inst/rptr [3]),
+	.I0(\fifo_inst/Equal.rgraynext [1]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
 	.I3(GND),
 	.CIN(\fifo_inst/n130_3 ),
 	.COUT(\fifo_inst/n131_3 ),
 	.SUM(\fifo_inst/n131_1_SUM )
 );
 defparam \fifo_inst/n131_s0 .ALU_MODE=3;
+ALU \fifo_inst/n132_s0  (
+	.I0(\fifo_inst/Equal.rgraynext [2]),
+	.I1(\fifo_inst/Equal.rq2_wptr [2]),
+	.I3(GND),
+	.CIN(\fifo_inst/n131_3 ),
+	.COUT(\fifo_inst/n132_3 ),
+	.SUM(\fifo_inst/n132_1_SUM )
+);
+defparam \fifo_inst/n132_s0 .ALU_MODE=3;
+ALU \fifo_inst/n133_s0  (
+	.I0(\fifo_inst/Equal.rgraynext [3]),
+	.I1(\fifo_inst/Equal.rq2_wptr [3]),
+	.I3(GND),
+	.CIN(\fifo_inst/n132_3 ),
+	.COUT(\fifo_inst/n133_3 ),
+	.SUM(\fifo_inst/n133_1_SUM )
+);
+defparam \fifo_inst/n133_s0 .ALU_MODE=3;
 INV \fifo_inst/n4_s2  (
 	.I(RdClk),
 	.O(\fifo_inst/n4_6 )

src/src/FifoCtrl/FifoLMX/FifoLMX_tmp.v

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.9.02
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-
-//Created Time: Wed Apr 24 12:23:21 2024
+//Created Time: Thu Apr 25 16:07:21 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/FifoCtrl/FifoLMX/temp/FIFOHS/FIFOHS.prj

@@ -10,7 +10,7 @@
     <OptionList>
         <Option type="disable_insert_pad" value="1"/>
         <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
-        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/temp/FIFOHS"/>
+        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/FifoLMX/temp/FIFOHS"/>
         <Option type="output_file" value="FifoLMX.vg"/>
         <Option type="output_template" value="FifoLMX_tmp.v"/>
         <Option type="ram_balance" value="1"/>

src/src/FifoCtrl/FifoLMX/temp/FIFOHS/FifoLMX.log

@@ -39,7 +39,7 @@ WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_
 WARN  (AG0101) : The netlist is not one directed acyclic graph
 [80%] Tech-Mapping Phase 3 completed
 [90%] Tech-Mapping Phase 4 completed
-[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\temp\FIFOHS\FifoLMX.vg" completed
-Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\temp\FIFOHS\FifoLMX_tmp.v" completed
-[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\temp\FIFOHS\FifoLMX_syn.rpt.html" completed
+[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoLMX\temp\FIFOHS\FifoLMX.vg" completed
+Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoLMX\temp\FIFOHS\FifoLMX_tmp.v" completed
+[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoLMX\temp\FIFOHS\FifoLMX_syn.rpt.html" completed
 GowinSynthesis finish

src/src/FifoCtrl/FifoLMX/temp/FIFOHS/FifoLMX.vg

@@ -1,7 +1,7 @@
 //
 //Written by GowinSynthesis
 //Tool Version "V1.9.9.02"
-//Wed Apr 24 12:23:21 2024
+//Thu Apr 25 16:07:21 2024
 
 //Source file index table:
 //file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
@@ -17,225 +17,246 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+Eeo9r6zKZBCzzoX/vEjCCVRH/vbTUoQQ9buY6g==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=11824)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=13040)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module FifoLMX (
   Data,

src/src/FifoCtrl/FifoLMX/temp/FIFOHS/FifoLMX_syn_resource.html

@@ -31,9 +31,9 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 </tr>
 <tr>
 <td class="label">FifoLMX (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
-<td align = "center">28</td>
+<td align = "center">37</td>
 <td align = "center">4</td>
-<td align = "center">39</td>
+<td align = "center">38</td>
 <td align = "center">-</td>
 <td align = "center">1</td>
 <td align = "center">-</td>

src/src/FifoCtrl/FifoLMX/temp/FIFOHS/FifoLMX_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="FifoLMX" Register="28" Alu="4" Lut="39" Bsram="1" T_Register="28(28)" T_Alu="4(4)" T_Lut="39(39)" T_Bsram="1(1)"/>
+<Module name="FifoLMX" Register="37" Alu="4" Lut="38" Bsram="1" T_Register="37(37)" T_Alu="4(4)" T_Lut="38(38)" T_Bsram="1(1)"/>

src/src/FifoCtrl/FifoLMX/temp/FIFOHS/FifoLMX_tmp.v

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.9.02
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-
-//Created Time: Wed Apr 24 12:23:21 2024
+//Created Time: Thu Apr 25 16:07:21 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/FifoCtrl/FifoLMX/temp/FIFOHS/fifo_define.v

@@ -1,4 +1,5 @@
 `define module_name FifoLMX
 `define EBR_BASED
+`define FWFT
 `define En_Reset
 `define Reset_Synchronization

src/src/FifoCtrl/FifoMax2870/FifoMax2870.ipc

@@ -17,7 +17,7 @@ ECCSelected=false
 EmptyClear=1
 EmptySet=1
 EnReset=true
-FirstWordFallThrough=false
+FirstWordFallThrough=true
 FullClear=1
 FullSet=1
 LANG=0
@@ -28,7 +28,7 @@ ReadDataWidth=32
 ReadDepth=4
 ResetSynchronization=true
 SSRAM=false
-StandardFIFO=true
+StandardFIFO=false
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
 WriteDataWidth=32

src/src/FifoCtrl/FifoMax2870/FifoMax2870.v

@@ -1,7 +1,7 @@
 //
 //Written by GowinSynthesis
 //Tool Version "V1.9.9.02"
-//Wed Apr 24 12:27:38 2024
+//Thu Apr 25 16:07:36 2024
 
 //Source file index table:
 //file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
@@ -17,156 +17,164 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+XKL3+73PMXlMajN6EcsM4S1BTp7fXxaHLIWB1w==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=7888)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=8352)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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+UFKPIE60GOJM5l5TV8OVLPF04vqDqtxEqK9epn57aS6bVaFBG0fQyrwu2tA6EsE5HHvY2pipLp6y
+ixYXLHGSlymNpe6Aly+o3UT7u/auEiH3kAu9tr9kZhKkQ2L7JjUJJ8tr4pdRXAgctuln3las631r
+A5d51+D5gF6dQrgjF/mP7wqY9GFeJVtTssFz6e5KLcvvzMApZvLkrWgV06xeIFoUtCxisqQn4CsI
+zwTWXWSJXFCrmjlZKaYBf9aD6z2QiU0O5j0by9GvGG0NsgJskr6d1NS2oySbE5n/AeaWIWgcF4O5
+zq7E/hAL5DhI/yzHIYyuSyqU68Z/fAJnkQzdM8BakV5Yb85fcnk4p9KNz2qB45oIh3h7MJL6DzRt
+Tacxsq8NQNnXGnr35uUaeSZqrVrupt8Roo8Ty61Grm4kZwlm2sgMKgXAApelU5R326CkO7iMCf3z
+qVmXdmdwKDtJmtYhyMOxNRK8erlu4r6zEeDvEpx2IBIOGnT0ApDjYviZlP99fgMh3yJfI/had4rT
+mC1Z685Ml2+hMNFdxFjxEm8BVqAUNgfuaDj7Li5jZnGpqdGjUKfMwV4do/jufEf8Veu3WdAF65og
+swhI56mnllNG9wN34pjZ4RslCEtlkr4Gxz+LdX+cV/WpGQJnFBIabFIQZOawAZLpev8obH3dGkEh
+q+6txUhhMK+n8SpsxnUuMuBaihhSwlhxHZuNI21WZKs4+UHD4p4XKp5/JnwAVaF7JAHMPhRyu9Lj
+17vVYGLMvKAxiswx7F8Wf/sqe2bICrBHeOwr9txjW1zLKCnxVCLfivCAi3JjVKmfaJbPbdFYZc2T
+bPVpgkyuhCzoUp+3N37RJ/RWjqbeq6RDzOkIPZox
 `pragma protect end_protected
 module FifoMax2870 (
   Data,

src/src/FifoCtrl/FifoMax2870/FifoMax2870.vo

@@ -2,7 +2,7 @@
 //All rights reserved.
 //File Title: Post-PnR Simulation Model file
 //Tool Version: V1.9.9.02
-//Created Time: Wed Apr 24 12:27:39 2024
+//Created Time: Thu Apr 25 16:07:36 2024
 
 `timescale 100 ps/100 ps
 module FifoMax2870(
@@ -37,37 +37,35 @@ wire VCC;
 wire WrClk;
 wire WrEn;
 wire \fifo_inst/n21_5 ;
-wire \fifo_inst/n25_3 ;
-wire \fifo_inst/n257_3 ;
+wire \fifo_inst/n27_4 ;
 wire \fifo_inst/wfull_val1 ;
 wire \fifo_inst/wfull_val1_0 ;
 wire \fifo_inst/Full_1 ;
 wire \fifo_inst/Equal.wbinnext_0_7 ;
-wire \fifo_inst/Equal.wgraynext_1_4 ;
 wire \fifo_inst/wfull_val_4 ;
 wire \fifo_inst/wfull_val_5 ;
-wire \fifo_inst/n336_6 ;
+wire \fifo_inst/n335_6 ;
 wire \fifo_inst/wfull_val ;
-wire \fifo_inst/rbin_num_next_0_9 ;
 wire \fifo_inst/rempty_val ;
-wire \fifo_inst/rempty_val1 ;
 wire \fifo_inst/wfull_val1_2 ;
 wire \fifo_inst/wfull_val1_3 ;
 wire \fifo_inst/Full_1_2 ;
 wire \fifo_inst/Full_2 ;
-wire \fifo_inst/n156_1_SUM ;
-wire \fifo_inst/n156_3 ;
-wire \fifo_inst/n157_1_SUM ;
-wire \fifo_inst/n157_3 ;
+wire \fifo_inst/n158_1_SUM ;
+wire \fifo_inst/n158_3 ;
+wire \fifo_inst/n159_1_SUM ;
+wire \fifo_inst/n159_3 ;
 wire \fifo_inst/n4_6 ;
 wire \fifo_inst/n9_6 ;
 wire [1:0] \fifo_inst/Equal.rgraynext ;
 wire [1:0] \fifo_inst/Equal.wgraynext ;
-wire [2:1] \fifo_inst/rbin_num_next ;
+wire [2:0] \fifo_inst/rbin_num_next ;
 wire [2:1] \fifo_inst/Equal.wbinnext ;
 wire [1:0] \fifo_inst/reset_r ;
 wire [1:0] \fifo_inst/reset_w ;
 wire [2:0] \fifo_inst/rbin_num ;
+wire [2:0] \fifo_inst/Equal.rq1_wptr ;
+wire [2:0] \fifo_inst/Equal.rq2_wptr ;
 wire [1:0] \fifo_inst/rptr ;
 wire [2:0] \fifo_inst/wptr ;
 wire [1:0] \fifo_inst/Equal.wbin ;
@@ -88,20 +86,28 @@ LUT4 \fifo_inst/n21_s1  (
 	.F(\fifo_inst/n21_5 )
 );
 defparam \fifo_inst/n21_s1 .INIT=16'h5300;
-LUT2 \fifo_inst/n25_s0  (
-	.I0(Empty),
-	.I1(RdEn),
-	.F(\fifo_inst/n25_3 )
+LUT3 \fifo_inst/n27_s1  (
+	.I0(RdEn),
+	.I1(Empty),
+	.I2(\fifo_inst/rempty_val ),
+	.F(\fifo_inst/n27_4 )
+);
+defparam \fifo_inst/n27_s1 .INIT=8'h0E;
+LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
 );
-defparam \fifo_inst/n25_s0 .INIT=4'h4;
+defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
 LUT4 \fifo_inst/Equal.rgraynext_1_s0  (
-	.I0(\fifo_inst/n25_3 ),
+	.I0(\fifo_inst/rbin_num_next [0]),
 	.I1(\fifo_inst/rbin_num [0]),
 	.I2(\fifo_inst/rbin_num [1]),
 	.I3(\fifo_inst/rbin_num [2]),
 	.F(\fifo_inst/Equal.rgraynext [1])
 );
-defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=16'h07F8;
+defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=16'h0BF4;
 LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
 	.I0(\fifo_inst/n21_5 ),
 	.I1(\fifo_inst/Equal.wbin [0]),
@@ -110,19 +116,13 @@ LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
 );
 defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
 LUT4 \fifo_inst/Equal.wgraynext_1_s0  (
-	.I0(Full),
-	.I1(\fifo_inst/Equal.wgraynext_1_4 ),
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
 	.I2(\fifo_inst/Equal.wbin [1]),
 	.I3(\fifo_inst/wptr [2]),
 	.F(\fifo_inst/Equal.wgraynext [1])
 );
-defparam \fifo_inst/Equal.wgraynext_1_s0 .INIT=16'h0BF4;
-LUT2 \fifo_inst/n257_s0  (
-	.I0(\fifo_inst/rempty_val ),
-	.I1(\fifo_inst/reset_r [1]),
-	.F(\fifo_inst/n257_3 )
-);
-defparam \fifo_inst/n257_s0 .INIT=4'hE;
+defparam \fifo_inst/Equal.wgraynext_1_s0 .INIT=16'h07F8;
 LUT3 \fifo_inst/wfull_val1_s9  (
 	.I0(\fifo_inst/wfull_val1_3 ),
 	.I1(\fifo_inst/wfull_val1_2 ),
@@ -153,34 +153,49 @@ LUT4 \fifo_inst/Full_s8  (
 	.F(\fifo_inst/Full_1 )
 );
 defparam \fifo_inst/Full_s8 .INIT=16'h00F8;
+LUT3 \fifo_inst/rbin_num_next_0_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next [0])
+);
+defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
+LUT3 \fifo_inst/rbin_num_next_1_s5  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s5 .INIT=8'hB4;
 LUT4 \fifo_inst/rbin_num_next_2_s2  (
-	.I0(\fifo_inst/n25_3 ),
+	.I0(\fifo_inst/rbin_num_next [0]),
 	.I1(\fifo_inst/rbin_num [0]),
 	.I2(\fifo_inst/rbin_num [1]),
 	.I3(\fifo_inst/rbin_num [2]),
 	.F(\fifo_inst/rbin_num_next [2])
 );
-defparam \fifo_inst/rbin_num_next_2_s2 .INIT=16'h7F80;
+defparam \fifo_inst/rbin_num_next_2_s2 .INIT=16'hBF40;
 LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
 	.I0(\fifo_inst/n21_5 ),
 	.I1(\fifo_inst/Equal.wbin [0]),
 	.F(\fifo_inst/Equal.wbinnext_0_7 )
 );
 defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
+LUT3 \fifo_inst/Equal.wbinnext_1_s3  (
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.I2(\fifo_inst/Equal.wbin [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s3 .INIT=8'h78;
 LUT4 \fifo_inst/Equal.wbinnext_2_s2  (
-	.I0(Full),
-	.I1(\fifo_inst/Equal.wgraynext_1_4 ),
+	.I0(\fifo_inst/n21_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
 	.I2(\fifo_inst/Equal.wbin [1]),
 	.I3(\fifo_inst/wptr [2]),
 	.F(\fifo_inst/Equal.wbinnext [2])
 );
-defparam \fifo_inst/Equal.wbinnext_2_s2 .INIT=16'hBF40;
-LUT2 \fifo_inst/Equal.wgraynext_1_s1  (
-	.I0(WrEn),
-	.I1(\fifo_inst/Equal.wbin [0]),
-	.F(\fifo_inst/Equal.wgraynext_1_4 )
-);
-defparam \fifo_inst/Equal.wgraynext_1_s1 .INIT=4'h8;
+defparam \fifo_inst/Equal.wbinnext_2_s2 .INIT=16'h7F80;
 LUT2 \fifo_inst/wfull_val_s1  (
 	.I0(\fifo_inst/wptr [2]),
 	.I1(\fifo_inst/rbin_num [2]),
@@ -195,22 +210,14 @@ LUT4 \fifo_inst/wfull_val_s2  (
 	.F(\fifo_inst/wfull_val_5 )
 );
 defparam \fifo_inst/wfull_val_s2 .INIT=16'h0990;
-LUT4 \fifo_inst/Equal.wbinnext_1_s4  (
-	.I0(Full),
-	.I1(WrEn),
-	.I2(\fifo_inst/Equal.wbin [0]),
-	.I3(\fifo_inst/Equal.wbin [1]),
-	.F(\fifo_inst/Equal.wbinnext [1])
-);
-defparam \fifo_inst/Equal.wbinnext_1_s4 .INIT=16'hBF40;
-LUT4 \fifo_inst/n336_s2  (
+LUT4 \fifo_inst/n335_s2  (
 	.I0(\fifo_inst/wptr [2]),
 	.I1(\fifo_inst/rbin_num [2]),
 	.I2(\fifo_inst/reset_w [1]),
 	.I3(\fifo_inst/wfull_val_5 ),
-	.F(\fifo_inst/n336_6 )
+	.F(\fifo_inst/n335_6 )
 );
-defparam \fifo_inst/n336_s2 .INIT=16'h0600;
+defparam \fifo_inst/n335_s2 .INIT=16'h0600;
 LUT3 \fifo_inst/wfull_val_s3  (
 	.I0(\fifo_inst/wptr [2]),
 	.I1(\fifo_inst/rbin_num [2]),
@@ -218,33 +225,10 @@ LUT3 \fifo_inst/wfull_val_s3  (
 	.F(\fifo_inst/wfull_val )
 );
 defparam \fifo_inst/wfull_val_s3 .INIT=8'h60;
-LUT4 \fifo_inst/rbin_num_next_1_s4  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.I3(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/rbin_num_next [1])
-);
-defparam \fifo_inst/rbin_num_next_1_s4 .INIT=16'hBF40;
-LUT3 \fifo_inst/rbin_num_next_0_s4  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rbin_num_next_0_9 )
-);
-defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
-LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.I3(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/Equal.rgraynext [0])
-);
-defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
 LUT3 \fifo_inst/rempty_val_s2  (
-	.I0(\fifo_inst/wptr [2]),
-	.I1(\fifo_inst/rbin_num [2]),
-	.I2(\fifo_inst/n157_3 ),
+	.I0(\fifo_inst/rbin_num_next [2]),
+	.I1(\fifo_inst/Equal.rq2_wptr [2]),
+	.I2(\fifo_inst/n159_3 ),
 	.F(\fifo_inst/rempty_val )
 );
 defparam \fifo_inst/rempty_val_s2 .INIT=8'h09;
@@ -284,12 +268,54 @@ DFFC \fifo_inst/rbin_num_1_s0  (
 );
 defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/rbin_num_0_s0  (
-	.D(\fifo_inst/rbin_num_next_0_9 ),
+	.D(\fifo_inst/rbin_num_next [0]),
 	.CLK(RdClk),
 	.CLEAR(\fifo_inst/reset_r [1]),
 	.Q(\fifo_inst/rbin_num [0])
 );
 defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_2_s0  (
+	.D(\fifo_inst/wptr [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [2])
+);
+defparam \fifo_inst/Equal.rq1_wptr_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
+	.D(\fifo_inst/wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [1])
+);
+defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
+	.D(\fifo_inst/wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [0])
+);
+defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_2_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [2]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [2])
+);
+defparam \fifo_inst/Equal.rq2_wptr_2_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [1])
+);
+defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [0])
+);
+defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/rptr_1_s0  (
 	.D(\fifo_inst/Equal.rgraynext [1]),
 	.CLK(RdClk),
@@ -339,17 +365,10 @@ DFFC \fifo_inst/Equal.wbin_0_s0  (
 	.Q(\fifo_inst/Equal.wbin [0])
 );
 defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
-DFFP \fifo_inst/rempty_val1_s0  (
-	.D(\fifo_inst/rempty_val ),
-	.CLK(RdClk),
-	.PRESET(\fifo_inst/n257_3 ),
-	.Q(\fifo_inst/rempty_val1 )
-);
-defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
 DFFP \fifo_inst/Empty_s0  (
-	.D(\fifo_inst/rempty_val1 ),
+	.D(\fifo_inst/rempty_val ),
 	.CLK(RdClk),
-	.PRESET(\fifo_inst/n257_3 ),
+	.PRESET(\fifo_inst/reset_r [1]),
 	.Q(Empty)
 );
 defparam \fifo_inst/Empty_s0 .INIT=1'b1;
@@ -370,7 +389,7 @@ defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
 	.D(\fifo_inst/wfull_val ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n336_6 ),
+	.PRESET(\fifo_inst/n335_6 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -384,7 +403,7 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n336_6 ),
+	.PRESET(\fifo_inst/n335_6 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
@@ -393,14 +412,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
 	.CEA(\fifo_inst/n21_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n25_3 ),
+	.CEB(\fifo_inst/n27_4 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({Data[31:0]}),
 	.ADA({GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [1:0], GND, VCC, VCC, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [1:0], GND, GND, GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [1:0], GND, GND, GND, GND, GND}),
 	.DO({Q[31:0]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
@@ -409,24 +428,24 @@ defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=32;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
-ALU \fifo_inst/n156_s0  (
-	.I0(\fifo_inst/wptr [0]),
-	.I1(\fifo_inst/rptr [0]),
+ALU \fifo_inst/n158_s0  (
+	.I0(\fifo_inst/Equal.rgraynext [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [0]),
 	.I3(GND),
 	.CIN(GND),
-	.COUT(\fifo_inst/n156_3 ),
-	.SUM(\fifo_inst/n156_1_SUM )
+	.COUT(\fifo_inst/n158_3 ),
+	.SUM(\fifo_inst/n158_1_SUM )
 );
-defparam \fifo_inst/n156_s0 .ALU_MODE=3;
-ALU \fifo_inst/n157_s0  (
-	.I0(\fifo_inst/wptr [1]),
-	.I1(\fifo_inst/rptr [1]),
+defparam \fifo_inst/n158_s0 .ALU_MODE=3;
+ALU \fifo_inst/n159_s0  (
+	.I0(\fifo_inst/Equal.rgraynext [1]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
 	.I3(GND),
-	.CIN(\fifo_inst/n156_3 ),
-	.COUT(\fifo_inst/n157_3 ),
-	.SUM(\fifo_inst/n157_1_SUM )
+	.CIN(\fifo_inst/n158_3 ),
+	.COUT(\fifo_inst/n159_3 ),
+	.SUM(\fifo_inst/n159_1_SUM )
 );
-defparam \fifo_inst/n157_s0 .ALU_MODE=3;
+defparam \fifo_inst/n159_s0 .ALU_MODE=3;
 INV \fifo_inst/n4_s2  (
 	.I(RdClk),
 	.O(\fifo_inst/n4_6 )

src/src/FifoCtrl/FifoMax2870/FifoMax2870_tmp.v

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.9.02
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-
-//Created Time: Wed Apr 24 12:27:38 2024
+//Created Time: Thu Apr 25 16:07:36 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/FifoCtrl/FifoMax2870/temp/FIFOHS/FIFOHS.prj

@@ -10,7 +10,7 @@
     <OptionList>
         <Option type="disable_insert_pad" value="1"/>
         <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
-        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/FifoMax2870/fifo_hs/temp/FIFOHS"/>
+        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/FifoMax2870/temp/FIFOHS"/>
         <Option type="output_file" value="FifoMax2870.vg"/>
         <Option type="output_template" value="FifoMax2870_tmp.v"/>
         <Option type="ram_balance" value="1"/>

src/src/FifoCtrl/FifoMax2870/temp/FIFOHS/FifoMax2870.log

@@ -39,7 +39,7 @@ WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_
 WARN  (AG0101) : The netlist is not one directed acyclic graph
 [80%] Tech-Mapping Phase 3 completed
 [90%] Tech-Mapping Phase 4 completed
-[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\fifo_hs\temp\FIFOHS\FifoMax2870.vg" completed
-Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\fifo_hs\temp\FIFOHS\FifoMax2870_tmp.v" completed
-[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\fifo_hs\temp\FIFOHS\FifoMax2870_syn.rpt.html" completed
+[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\temp\FIFOHS\FifoMax2870.vg" completed
+Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\temp\FIFOHS\FifoMax2870_tmp.v" completed
+[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\temp\FIFOHS\FifoMax2870_syn.rpt.html" completed
 GowinSynthesis finish

src/src/FifoCtrl/FifoMax2870/temp/FIFOHS/FifoMax2870.vg

@@ -1,7 +1,7 @@
 //
 //Written by GowinSynthesis
 //Tool Version "V1.9.9.02"
-//Wed Apr 24 12:27:38 2024
+//Thu Apr 25 16:07:36 2024
 
 //Source file index table:
 //file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
@@ -17,156 +17,164 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+XKL3+73PMXlMajN6EcsM4S1BTp7fXxaHLIWB1w==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=7888)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=8352)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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+bPVpgkyuhCzoUp+3N37RJ/RWjqbeq6RDzOkIPZox
 `pragma protect end_protected
 module FifoMax2870 (
   Data,

src/src/FifoCtrl/FifoMax2870/temp/FIFOHS/FifoMax2870_syn_resource.html

@@ -31,9 +31,9 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 </tr>
 <tr>
 <td class="label">FifoMax2870 (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
-<td align = "center">20</td>
-<td align = "center">2</td>
 <td align = "center">25</td>
+<td align = "center">2</td>
+<td align = "center">23</td>
 <td align = "center">-</td>
 <td align = "center">1</td>
 <td align = "center">-</td>

src/src/FifoCtrl/FifoMax2870/temp/FIFOHS/FifoMax2870_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="FifoMax2870" Register="20" Alu="2" Lut="25" Bsram="1" T_Register="20(20)" T_Alu="2(2)" T_Lut="25(25)" T_Bsram="1(1)"/>
+<Module name="FifoMax2870" Register="25" Alu="2" Lut="23" Bsram="1" T_Register="25(25)" T_Alu="2(2)" T_Lut="23(23)" T_Bsram="1(1)"/>

src/src/FifoCtrl/FifoMax2870/temp/FIFOHS/FifoMax2870_tmp.v

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.9.02
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-
-//Created Time: Wed Apr 24 12:27:38 2024
+//Created Time: Thu Apr 25 16:07:36 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/FifoCtrl/FifoMax2870/temp/FIFOHS/fifo_define.v

@@ -1,4 +1,5 @@
 `define module_name FifoMax2870
 `define EBR_BASED
+`define FWFT
 `define En_Reset
 `define Reset_Synchronization

src/src/FifoCtrl/FifoShiftReg/FifoShiftReg.ipc

@@ -17,7 +17,7 @@ ECCSelected=false
 EmptyClear=1
 EmptySet=1
 EnReset=true
-FirstWordFallThrough=false
+FirstWordFallThrough=true
 FullClear=1
 FullSet=1
 LANG=0
@@ -28,7 +28,7 @@ ReadDataWidth=8
 ReadDepth=2
 ResetSynchronization=true
 SSRAM=false
-StandardFIFO=true
+StandardFIFO=false
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
 WriteDataWidth=8

src/src/FifoCtrl/FifoShiftReg/FifoShiftReg.v

@@ -1,7 +1,7 @@
 //
 //Written by GowinSynthesis
 //Tool Version "V1.9.9.02"
-//Wed Apr 24 14:54:26 2024
+//Thu Apr 25 16:08:18 2024
 
 //Source file index table:
 //file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
@@ -17,120 +17,130 @@
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-`pragma protect encoding=(enctype="base64", line_length=76, bytes=5840)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6400)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
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+G2ZWAkABzRO0nbHVGI43UDRb6SzvhnEru+lE/tvU6oAP7EwdDjkfur1FvVzQinyHbW1bJdN25KSy
+lVvFBPjdKZ9TddnW/owW7tjI7RqXma2O9rBjONn1GMnOitA8aLmflrzFf5ELUfDsISPAs8V01a4j
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+05DHlCbJy4qzQymkig07w4dgHwCYV0dp1EtIjJJBFVOehhCJvno0OjV5vzD2zU4jlxkdoN//hF9r
+FGZCAdJ0fUc1V7y2cGMLAK0G4GzaYKigvSEqaiZ/58kf17IIRkFFZ8LPqKRmT/xJrdY377uLgMjD
+JabZqQVtKkIgLr6EV1VaLFkKcl3/9g+mC0dMtTxsccUlo7UKRrO4J53MZEnkPyEgIJf4/0iK0n1O
+2y3GKpfF60FQ6p5ZXfr/F+AA5fcFXFgbEJkLM/pe5Pc+hZTlNaSxdR03LvjLPY7hUFf0J+XTvEWh
+xrdJIMYp9APmEX4i8/rVNHX9vlVBRVoKJOayeGXTgwgvXtWzQxkVRCGtNNxP903f6SQEQsuFRGcZ
+YvDuOrqGXFLdCLxq6m++/Pvi7PsCPA8gNz+KJyfe1KvvzsABV96JllYfuUrG/D3dSTyrex/pY18v
+BiNoQ2aG/QkeI90z5oXmi2VpDNZE9Opa0gnV+VJeetMo98YHsuqMk1WrhHnNTnVMKfycKu4N8EFt
+H3wDXAun6eATEv8//B+ptKjUt1H5zRZqYG5Pjvh98ihFw/uPM38dY6tiPM07kSUdpLIVcWmLPgI0
+yn/i0+q7KpP7gj9QeKMn0bkhFVmcbak07JFGtVMK6x4u0Nghfv0lOyxtirJE3BL7Hxd4QGLmEN3t
+NsOzN2EHJ/ArtlgwrN/37AlLZO+UhsvSMTbawUNsmpqtqeQk2LBiCzQvY6CAqz/zs+AqaVHM+EH4
+/DgZxLUhrk6fiW8R+NjOE29d8U9/xsmEO6KhJch4k73kCH93ZBzaaPqq+D3UwaHbuk2k/cqPyNve
+BrWHDjSsnheYikR4eooDlA==
 `pragma protect end_protected
 module FifoShiftReg (
   Data,

src/src/FifoCtrl/FifoShiftReg/FifoShiftReg.vo

@@ -2,7 +2,7 @@
 //All rights reserved.
 //File Title: Post-PnR Simulation Model file
 //Tool Version: V1.9.9.02
-//Created Time: Wed Apr 24 14:54:26 2024
+//Created Time: Thu Apr 25 16:08:18 2024
 
 `timescale 100 ps/100 ps
 module FifoShiftReg(
@@ -37,30 +37,30 @@ wire VCC;
 wire WrClk;
 wire WrEn;
 wire \fifo_inst/n20_5 ;
-wire \fifo_inst/n24_3 ;
-wire \fifo_inst/n135_3 ;
-wire \fifo_inst/n178_4 ;
+wire \fifo_inst/n26_4 ;
+wire \fifo_inst/n177_4 ;
 wire \fifo_inst/rempty_val ;
 wire \fifo_inst/wfull_val_7 ;
 wire \fifo_inst/wfull_val1 ;
 wire \fifo_inst/wfull_val1_0 ;
 wire \fifo_inst/Full_1 ;
 wire \fifo_inst/Equal.wbinnext_0_7 ;
-wire \fifo_inst/rbin_num_next_0_9 ;
-wire \fifo_inst/rempty_val1 ;
+wire \fifo_inst/rempty_val_8 ;
 wire \fifo_inst/wfull_val1_2 ;
 wire \fifo_inst/wfull_val1_3 ;
 wire \fifo_inst/Full_1_2 ;
 wire \fifo_inst/Full_2 ;
 wire \fifo_inst/n4_6 ;
 wire \fifo_inst/n9_6 ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [0:0] \fifo_inst/Equal.wgraynext ;
+wire [1:0] \fifo_inst/rbin_num_next ;
 wire [1:1] \fifo_inst/Equal.wbinnext ;
-wire [1:1] \fifo_inst/rbin_num_next ;
-wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [1:0] \fifo_inst/reset_r ;
 wire [1:0] \fifo_inst/reset_w ;
 wire [1:0] \fifo_inst/rbin_num ;
+wire [1:0] \fifo_inst/Equal.rq1_wptr ;
+wire [1:0] \fifo_inst/Equal.rq2_wptr ;
 wire [0:0] \fifo_inst/rptr ;
 wire [1:0] \fifo_inst/wptr ;
 wire [0:0] \fifo_inst/Equal.wbin ;
@@ -82,39 +82,41 @@ LUT4 \fifo_inst/n20_s1  (
 	.F(\fifo_inst/n20_5 )
 );
 defparam \fifo_inst/n20_s1 .INIT=16'h5300;
-LUT2 \fifo_inst/n24_s0  (
-	.I0(Empty),
-	.I1(RdEn),
-	.F(\fifo_inst/n24_3 )
+LUT3 \fifo_inst/n26_s1  (
+	.I0(RdEn),
+	.I1(Empty),
+	.I2(\fifo_inst/rempty_val ),
+	.F(\fifo_inst/n26_4 )
+);
+defparam \fifo_inst/n26_s1 .INIT=8'h0E;
+LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
+	.I0(\fifo_inst/rbin_num [0]),
+	.I1(\fifo_inst/rbin_num_next [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
 );
-defparam \fifo_inst/n24_s0 .INIT=4'h4;
+defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
 LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
-	.I0(\fifo_inst/n20_5 ),
-	.I1(\fifo_inst/Equal.wbin [0]),
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wgraynext [0])
 );
 defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
-LUT2 \fifo_inst/n135_s0  (
-	.I0(\fifo_inst/rempty_val ),
-	.I1(\fifo_inst/reset_r [1]),
-	.F(\fifo_inst/n135_3 )
-);
-defparam \fifo_inst/n135_s0 .INIT=4'hE;
-LUT2 \fifo_inst/n178_s1  (
+LUT2 \fifo_inst/n177_s1  (
 	.I0(\fifo_inst/reset_w [1]),
 	.I1(\fifo_inst/wfull_val_7 ),
-	.F(\fifo_inst/n178_4 )
+	.F(\fifo_inst/n177_4 )
 );
-defparam \fifo_inst/n178_s1 .INIT=4'h4;
+defparam \fifo_inst/n177_s1 .INIT=4'h4;
 LUT4 \fifo_inst/rempty_val_s3  (
-	.I0(\fifo_inst/wptr [0]),
-	.I1(\fifo_inst/rptr [0]),
-	.I2(\fifo_inst/wptr [1]),
-	.I3(\fifo_inst/rbin_num [1]),
+	.I0(\fifo_inst/Equal.rq2_wptr [1]),
+	.I1(\fifo_inst/rempty_val_8 ),
+	.I2(\fifo_inst/Equal.rq2_wptr [0]),
+	.I3(\fifo_inst/rbin_num_next [0]),
 	.F(\fifo_inst/rempty_val )
 );
-defparam \fifo_inst/rempty_val_s3 .INIT=16'h9009;
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
 LUT4 \fifo_inst/wfull_val_s3  (
 	.I0(\fifo_inst/wptr [0]),
 	.I1(\fifo_inst/wptr [1]),
@@ -131,8 +133,8 @@ LUT3 \fifo_inst/wfull_val1_s9  (
 );
 defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
 LUT3 \fifo_inst/wfull_val1_s10  (
-	.I0(\fifo_inst/wfull_val1_0 ),
-	.I1(\fifo_inst/wfull_val_7 ),
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/wfull_val1_0 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/wfull_val1_0 )
 );
@@ -145,48 +147,47 @@ LUT3 \fifo_inst/Full_d_s  (
 );
 defparam \fifo_inst/Full_d_s .INIT=8'hAC;
 LUT3 \fifo_inst/Full_s8  (
-	.I0(\fifo_inst/Full_1 ),
-	.I1(\fifo_inst/wfull_val_7 ),
+	.I0(\fifo_inst/wfull_val_7 ),
+	.I1(\fifo_inst/Full_1 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/Full_1 )
 );
 defparam \fifo_inst/Full_s8 .INIT=8'h0E;
+LUT3 \fifo_inst/rbin_num_next_0_s5  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next [0])
+);
+defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
+LUT3 \fifo_inst/rbin_num_next_1_s2  (
+	.I0(\fifo_inst/rbin_num_next [0]),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
 LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
-	.I0(\fifo_inst/n20_5 ),
-	.I1(\fifo_inst/Equal.wbin [0]),
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
 	.F(\fifo_inst/Equal.wbinnext_0_7 )
 );
 defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
 LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
-	.I0(\fifo_inst/n20_5 ),
-	.I1(\fifo_inst/Equal.wbin [0]),
+	.I0(\fifo_inst/Equal.wbin [0]),
+	.I1(\fifo_inst/n20_5 ),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wbinnext [1])
 );
 defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
-LUT4 \fifo_inst/rbin_num_next_1_s3  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.I3(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/rbin_num_next [1])
-);
-defparam \fifo_inst/rbin_num_next_1_s3 .INIT=16'hBF40;
-LUT3 \fifo_inst/rbin_num_next_0_s4  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rbin_num_next_0_9 )
-);
-defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
-LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.I3(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/Equal.rgraynext [0])
+LUT4 \fifo_inst/rempty_val_s4  (
+	.I0(\fifo_inst/Equal.rq2_wptr [0]),
+	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rempty_val_8 )
 );
-defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
+defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
 DFFP \fifo_inst/reset_r_0_s0  (
 	.D(GND),
 	.CLK(\fifo_inst/n4_6 ),
@@ -216,12 +217,40 @@ DFFC \fifo_inst/rbin_num_1_s0  (
 );
 defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/rbin_num_0_s0  (
-	.D(\fifo_inst/rbin_num_next_0_9 ),
+	.D(\fifo_inst/rbin_num_next [0]),
 	.CLK(RdClk),
 	.CLEAR(\fifo_inst/reset_r [1]),
 	.Q(\fifo_inst/rbin_num [0])
 );
 defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
+	.D(\fifo_inst/wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [1])
+);
+defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
+	.D(\fifo_inst/wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq1_wptr [0])
+);
+defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [1]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [1])
+);
+defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
+DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
+	.D(\fifo_inst/Equal.rq1_wptr [0]),
+	.CLK(RdClk),
+	.CLEAR(\fifo_inst/reset_r [1]),
+	.Q(\fifo_inst/Equal.rq2_wptr [0])
+);
+defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/rptr_0_s0  (
 	.D(\fifo_inst/Equal.rgraynext [0]),
 	.CLK(RdClk),
@@ -250,17 +279,10 @@ DFFC \fifo_inst/Equal.wbin_0_s0  (
 	.Q(\fifo_inst/Equal.wbin [0])
 );
 defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
-DFFP \fifo_inst/rempty_val1_s0  (
-	.D(\fifo_inst/rempty_val ),
-	.CLK(RdClk),
-	.PRESET(\fifo_inst/n135_3 ),
-	.Q(\fifo_inst/rempty_val1 )
-);
-defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
 DFFP \fifo_inst/Empty_s0  (
-	.D(\fifo_inst/rempty_val1 ),
+	.D(\fifo_inst/rempty_val ),
 	.CLK(RdClk),
-	.PRESET(\fifo_inst/n135_3 ),
+	.PRESET(\fifo_inst/reset_r [1]),
 	.Q(Empty)
 );
 defparam \fifo_inst/Empty_s0 .INIT=1'b1;
@@ -281,7 +303,7 @@ defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
 	.D(\fifo_inst/wfull_val_7 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n178_4 ),
+	.PRESET(\fifo_inst/n177_4 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -295,7 +317,7 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n178_4 ),
+	.PRESET(\fifo_inst/n177_4 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
@@ -304,14 +326,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
 	.CEA(\fifo_inst/n20_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n24_3 ),
+	.CEB(\fifo_inst/n26_4 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[7:0]}),
 	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, GND, GND}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND}),
 	.DO({\fifo_inst/DO [31:8], Q[7:0]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;

src/src/FifoCtrl/FifoShiftReg/FifoShiftReg_tmp.v

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.9.02
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-
-//Created Time: Wed Apr 24 14:54:26 2024
+//Created Time: Thu Apr 25 16:08:18 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/FifoCtrl/FifoShiftReg/temp/FIFOHS/FifoShiftReg.vg

@@ -1,7 +1,7 @@
 //
 //Written by GowinSynthesis
 //Tool Version "V1.9.9.02"
-//Wed Apr 24 14:54:26 2024
+//Thu Apr 25 16:08:18 2024
 
 //Source file index table:
 //file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
@@ -17,120 +17,130 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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-TCiBKnj8AtxX/hjF5wT9nW2SWG6/F2zIdPpJqw==
+rE66WtNKtc22HlKA/X4eJurtJEnvZemh7Zi9pohq7hHdYu15Y21d8CKvWJizh8HxY9I0OT+eTJYe
+eqAmDwscz3d6gWPx0ty1wAovCUkRxoMRBOBCmiJBj1FAq23KXlKei5tCXIQQG+7uAA9Mz6Jr+6hd
++siV1FTOW4hlWZSMlHvcc5M3QH2IpgONxuKpGtgigAjcxFHeL61jOKWUafSHFW6bf8j2J5rsbwqY
+ArJzg7FAyvR/3aNkWyNra/6lK47Ld15z5DXOp6Qw4yowJyzNpUIg7BGTwuT5hvVdE8HU5+LAGBLC
+8DM4h8FNMqFHubE/tetwFYOqKFxGclYw1Xqrhw==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=5840)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=6400)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
-VK77N4wiigXr59iGa59PiSfdb46m7TM16APHsHBXKaYBwY7Ynf8ffGt8SVvlnR7JOBnYE6ItsnoC
-6cfcqm5h6BrhTNCsPlyUirferLMWqFYYt2XY2A5a+IOom1Q1OeEQJ2gdyFb/KjjyzxcW0Qm3z2Ee
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+BrWHDjSsnheYikR4eooDlA==
 `pragma protect end_protected
 module FifoShiftReg (
   Data,

src/src/FifoCtrl/FifoShiftReg/temp/FIFOHS/FifoShiftReg_syn_resource.html

@@ -31,7 +31,7 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 </tr>
 <tr>
 <td class="label">FifoShiftReg (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
-<td align = "center">16</td>
+<td align = "center">19</td>
 <td align = "center">-</td>
 <td align = "center">18</td>
 <td align = "center">-</td>

src/src/FifoCtrl/FifoShiftReg/temp/FIFOHS/FifoShiftReg_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="FifoShiftReg" Register="16" Lut="18" Bsram="1" T_Register="16(16)" T_Lut="18(18)" T_Bsram="1(1)"/>
+<Module name="FifoShiftReg" Register="19" Lut="18" Bsram="1" T_Register="19(19)" T_Lut="18(18)" T_Bsram="1(1)"/>

src/src/FifoCtrl/FifoShiftReg/temp/FIFOHS/FifoShiftReg_tmp.v

@@ -4,7 +4,7 @@
 //Tool Version: V1.9.9.02
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-
-//Created Time: Wed Apr 24 14:54:26 2024
+//Created Time: Thu Apr 25 16:08:18 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/FifoCtrl/FifoShiftReg/temp/FIFOHS/fifo_define.v

@@ -1,4 +1,5 @@
 `define module_name FifoShiftReg
 `define EBR_BASED
+`define FWFT
 `define En_Reset
 `define Reset_Synchronization

src/src/FifoCtrl/Wrappers/AttenuatorWrapper.v

@@ -0,0 +1,95 @@
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     AttenuatorWrapper
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:    This module is a wrapper for the Fifo, Fifo Controller and SPI Master modules.
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module AttenuatorWrapper #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 1,
+    parameter OUT_WIDTH = 16,
+    parameter DATA_WIDTH = 16
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================    
+wire [OUT_WIDTH-1:0] dataFromAttFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromAttFifo;
+wire readEnAtt;
+wire writeEnAtt;
+wire valRdDataATT;
+wire busySpiMAtt;
+wire attFifoFull;
+wire attFifoEmpty;
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(16)
+) FifoCtrlAtt
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiMAtt),
+	.FifoFull_i		(attFifoFull),
+	.FifoEmpty_i	(attFifoEmpty),
+	.Data_o			(dataFromAttFifoCtrl),
+	.ReadEn_o		(readEnAtt),
+	.WriteEn_o		(writeEnAtt),
+	.ValRdData_o	(valRdDataATT)
+);
+
+Fifo16x3 FifoAtt_inst (
+	.Data	(dataFromAttFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnAtt),
+	.RdEn	(readEnAtt),
+	.Full	(attFifoFull),
+	.Empty	(attFifoEmpty),
+	.Q		(dataFromAttFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(16)
+)SpiMAtt(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataATT),
+	.SpiData_i	(dataFromAttFifo),
+	.Busy_o	    (busySpiMAtt),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule

src/src/FifoCtrl/Wrappers/DDSWrapper.v

@@ -0,0 +1,95 @@
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     DDSWrapper
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:    This module is a wrapper for the Fifo, Fifo Controller and SPI Master modules.
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module DDSWrapper #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 3,
+    parameter OUT_WIDTH = 64,
+    parameter DATA_WIDTH = 64
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================    
+wire [OUT_WIDTH-1:0] dataFromDdsFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromDdsFifo;
+wire readEnDds;
+wire writeEnDds;
+wire valRdDataDDS;
+wire busySpiMDds;
+wire ddsFifoFull;
+wire ddsFifoEmpty;
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(3),
+	.OUT_WIDTH		(64)
+) FifoCtrlDDS
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiMDds),
+	.FifoFull_i		(ddsFifoFull),
+	.FifoEmpty_i	(ddsFifoEmpty),
+	.Data_o			(dataFromDdsFifoCtrl),
+	.ReadEn_o		(readEnDds),
+	.WriteEn_o		(writeEnDds),
+	.ValRdData_o	(valRdDataDDS)
+);
+
+FifoDDS FifoDDS_inst (
+	.Data	(dataFromDdsFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnDds),
+	.RdEn	(readEnDds),
+	.Full	(ddsFifoFull),
+	.Empty	(ddsFifoEmpty),
+	.Q		(dataFromDdsFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(64)
+)SpiMDDS(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataDDS),
+	.SpiData_i	(dataFromDdsFifo),
+	.Busy_o	    (busySpiMDds),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule

src/src/FifoCtrl/Wrappers/DacWrapper.v

@@ -0,0 +1,95 @@
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     DDSWrapper
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:    This module is a wrapper for the Fifo, Fifo Controller and SPI Master modules.
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module DacWrapper #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 1,
+    parameter OUT_WIDTH = 16,
+    parameter DATA_WIDTH = 16
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================    
+wire [OUT_WIDTH-1:0] dataFromDacFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromDacFifo;
+wire readEnDac;
+wire writeEnDac;
+wire valRdDataDAC;
+wire busySpiMDac;
+wire dacFifoFull;
+wire dacFifoEmpty;
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(16)
+) FifoCtrlDac
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiMDac),
+	.FifoFull_i		(dacFifoFull),
+	.FifoEmpty_i	(dacFifoEmpty),
+	.Data_o			(dataFromDacFifoCtrl),
+	.ReadEn_o		(readEnDac),
+	.WriteEn_o		(writeEnDac),
+	.ValRdData_o	(valRdDataDAC)
+);
+
+Fifo16x3 FifoDAC_inst (
+	.Data	(dataFromDacFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnDac),
+	.RdEn	(readEnDac),
+	.Full	(dacFifoFull),
+	.Empty	(dacFifoEmpty),
+	.Q		(dataFromDacFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(16)
+)SpiMDac(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataDAC),
+	.SpiData_i	(dataFromDacFifo),
+	.Busy_o	    (busySpiMDac),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule

src/src/FifoCtrl/Wrappers/LmxWrapper.v

@@ -0,0 +1,95 @@
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     LmxWrapper
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:    This module is a wrapper for the LMX Fifo, LMX Fifo Controller and SPI Master modules.
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module LmxWrapper #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 1,
+    parameter OUT_WIDTH = 24,
+    parameter DATA_WIDTH = 24
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================    
+wire [OUT_WIDTH-1:0] dataFromLmxFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromLmxFifo;
+wire readEnLmx;
+wire writeEnLmx;
+wire valRdDataLMX;
+wire busySpiMLmx;
+wire lmxFifoFull;
+wire lmxFifoEmpty;
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(24)
+) FifoCtrlLmx
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiMLmx),
+	.FifoFull_i		(lmxFifoFull),
+	.FifoEmpty_i	(lmxFifoEmpty),
+	.Data_o			(dataFromLmxFifoCtrl),
+	.ReadEn_o		(readEnLmx),
+	.WriteEn_o		(writeEnLmx),
+	.ValRdData_o	(valRdDataLMX)
+);
+
+FifoLMX FifoLMX_inst (
+	.Data	(dataFromLmxFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnLmx),
+	.RdEn	(readEnLmx),
+	.Full	(lmxFifoFull),
+	.Empty	(lmxFifoEmpty),
+	.Q		(dataFromLmxFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(24)
+)SpiMLmx(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataLMX),
+	.SpiData_i	(dataFromLmxFifo),
+	.Busy_o	    (busySpiMLmx),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule

src/src/FifoCtrl/Wrappers/Max2870Wrapper.v

@@ -0,0 +1,95 @@
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     Max2870Wrapper
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:    This module is a wrapper for the Fifo, Fifo Controller and SPI Master modules.
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module Max2870Wrapper #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 2,
+    parameter OUT_WIDTH = 32,
+    parameter DATA_WIDTH = 32
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================    
+wire [OUT_WIDTH-1:0] dataFromMaxFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromMaxFifo;
+wire readEnMax;
+wire writeEnMax;
+wire valRdDataMAX;
+wire busySpiMMax;
+wire maxFifoFull;
+wire maxFifoEmpty;
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(2),
+	.OUT_WIDTH		(32)
+) FifoCtrlMax
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiMMax),
+	.FifoFull_i		(maxFifoFull),
+	.FifoEmpty_i	(maxFifoEmpty),
+	.Data_o			(dataFromMaxFifoCtrl),
+	.ReadEn_o		(readEnMax),
+	.WriteEn_o		(writeEnMax),
+	.ValRdData_o	(valRdDataMAX)
+);
+
+FifoMax2870 FifoMax2870_inst (
+	.Data	(dataFromMaxFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnMax),
+	.RdEn	(readEnMax),
+	.Full	(maxFifoFull),
+	.Empty	(maxFifoEmpty),
+	.Q		(dataFromMaxFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(32)
+)SpiMMax(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataMAX),
+	.SpiData_i	(dataFromMaxFifo),
+	.Busy_o	    (busySpiMMax),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule

src/src/FifoCtrl/Wrappers/PotWrapper.v

@@ -0,0 +1,95 @@
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     DDSWrapper
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:    This module is a wrapper for the Fifo, Fifo Controller and SPI Master modules.
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module PotWrapper #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 1,
+    parameter OUT_WIDTH = 16,
+    parameter DATA_WIDTH = 16
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================    
+wire [OUT_WIDTH-1:0] dataFromPotFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromPotFifo;
+wire readEnPot;
+wire writeEnPot;
+wire valRdDataPOT;
+wire busySpiMPot;
+wire potFifoFull;
+wire potFifoEmpty;
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(16)
+) FifoCtrlPot
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiMPot),
+	.FifoFull_i		(potFifoFull),
+	.FifoEmpty_i	(potFifoEmpty),
+	.Data_o			(dataFromPotFifoCtrl),
+	.ReadEn_o		(readEnPot),
+	.WriteEn_o		(writeEnPot),
+	.ValRdData_o	(valRdDataPOT)
+);
+
+Fifo16x3 FifoPot_inst (
+	.Data	(dataFromPotFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnPot),
+	.RdEn	(readEnPot),
+	.Full	(potFifoFull),
+	.Empty	(potFifoEmpty),
+	.Q		(dataFromPotFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(16)
+)SpiMPot(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataPOT),
+	.SpiData_i	(dataFromPotFifo),
+	.Busy_o	    (busySpiMPot),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule

src/src/FifoCtrl/Wrappers/ShifRegWrapper.v

@@ -0,0 +1,94 @@
+// Company:         TAIR
+// Engineer:        Chigrinskiy A.  
+// 
+// Create Date:     18/04/2024 
+// Design Name: 
+// Module Name:     ShiftRegWrapper
+// Project Name:    SB_TMSG44V1_FPGA
+// Target Devices:  Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:    This module is a wrapper for the Fifo, Fifo Controller and SPI Master modules.
+//
+// Dependencies:  
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module ShiftRegWrapper #(
+    parameter IN_WIDTH = 24,
+    parameter WR_NUM = 1,
+    parameter OUT_WIDTH = 8,
+    parameter DATA_WIDTH = 8
+)(
+    input WrClk_i,
+    input RdClk_i,
+    input Rst_i,
+    input [IN_WIDTH-1:0] Data_i,
+    input Val_i,
+
+    output Ss_o,
+    output Sck_o,
+    output Mosi_o
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================    
+wire [OUT_WIDTH-1:0] dataFromShRegFifoCtrl;
+wire [OUT_WIDTH-1:0] dataFromShRegFifo;
+wire readEnShReg;
+wire writeEnShReg;
+wire valRdDataShReg;
+wire busySpiMShReg;
+wire shRegFifoFull;
+wire shRegFifoEmpty;
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+FifoCtrl #(
+	.IN_WIDTH		(24),
+	.WR_NUM			(1),
+	.OUT_WIDTH		(8)
+) FifoCtrlShReg
+(
+	.WrClk_i		(WrClk_i),
+	.RdClk_i		(RdClk_i),
+	.Rst_i			(Rst_i),
+	.Data_i			(Data_i),
+	.Val_i			(Val_i),
+	.BusySpiM_i		(busySpiMShReg),
+	.FifoFull_i		(shRegFifoFull),
+	.FifoEmpty_i	(shRegFifoEmpty),
+	.Data_o			(dataFromShRegFifoCtrl),
+	.ReadEn_o		(readEnShReg),
+	.WriteEn_o		(writeEnShReg),
+	.ValRdData_o	(valRdDataShReg)
+);
+
+FifoShiftReg FifoShReg_inst (
+	.Data	(dataFromShRegFifoCtrl),
+	.WrClk	(WrClk_i),
+	.RdClk	(RdClk_i),
+	.Reset	(Rst_i),
+	.WrEn	(writeEnShReg),
+	.RdEn	(readEnShReg),
+	.Full	(shRegFifoFull),
+	.Empty	(shRegFifoEmpty),
+	.Q		(dataFromShRegFifo)
+);
+
+SpiM #(
+	.DATA_WIDTH	(8)
+)SpiMShReg(
+	.Clk_i		(RdClk_i),
+	.Rst_i		(Rst_i),
+	.Val_i		(valRdDataShReg),
+	.SpiData_i	(dataFromShRegFifo),
+	.Busy_o	    (busySpiMShReg),
+	.Ss_o		(Ss_o),
+	.Mosi_o		(Mosi_o),
+	.Sck_o		(Sck_o)
+);
+
+endmodule

src/src/Top/TopSbTmsg.v

@@ -196,4 +196,4 @@ GpioCtrl GpioCtrl
 );
 
 
-endmodule
+endmodule