Ресет для врапперов генерируется в модуле InitRst. Для отладки скорость работы выходных устройств ограничена 5 МГц. В модуле InterfaceArbiter wordsNum адаптирован под обновившийся протокол. Изменена логика генерации PllVtuneCtrl в режиме 1Mosi.

script/recreate.tcl

@@ -33,6 +33,7 @@ add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/Max28
 add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/ShifRegWrapper.v"
 add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/DacWrapper.v"
 add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/PotWrapper.v"
+add_file -type verilog "$::DSN_ROOT/SB_TMSG44V1_FPGA/src/src/InitRst/InitRst.v"
 
 
 

src/constr/SbTmsg.sdc

@@ -4,11 +4,11 @@
 //Tool Version: V1.9.9.02 
 //Created Time: 2024-05-02 15:55:01
 create_clock -name clk5 -period 200 -waveform {0 100} [get_nets {clk5}]
-create_clock -name clk50 -period 20 -waveform {0 10} [get_nets {clk50}]
-create_clock -name clk26dot25 -period 38.095 -waveform {0 19.047} [get_nets {clk26dot25}]
-create_clock -name clk20 -period 50 -waveform {0 25} [get_nets {clk20}]
+//create_clock -name clk50 -period 20 -waveform {0 10} [get_nets {clk50}]
+//create_clock -name clk26dot25 -period 38.095 -waveform {0 19.047} [get_nets {clk26dot25}]
+//create_clock -name clk20 -period 50 -waveform {0 25} [get_nets {clk20}]
 create_clock -name clk100 -period 10 -waveform {0 5} [get_nets {gclk100}]
-create_clock -name clk210 -period 4.762 -waveform {0 2.381} [get_nets {ClkGen/clk210Mhz}]
+//create_clock -name clk210 -period 4.762 -waveform {0 2.381} [get_nets {ClkGen/clk210Mhz}]
 create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
 create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
 //create_clock -name clk60 -period 16.667 -waveform {0 8.334} [get_nets {clk60}]

src/src/InitRst/InitRst.v

@@ -0,0 +1,104 @@
+module InitRst (
+    clk_i,
+    signal_o
+);
+
+//================================================================================
+//
+//  FUNCTIONS
+//
+//================================================================================
+
+    function integer bit_num;
+        input integer value;
+        begin
+            bit_num = 0;
+            while (value > 0) begin
+                value   = value >> 1;
+                bit_num = bit_num + 1;
+            end
+        end
+    endfunction
+
+//================================================================================
+//
+//  PARAMETER/LOCALPARAM
+//
+//================================================================================
+
+    parameter   DELAY_VALUE     = 12000;
+    localparam  DELAY_CNT_W     = bit_num(DELAY_VALUE);
+
+//================================================================================
+//
+//  PORTS
+//
+//================================================================================
+
+    input           clk_i;
+    output  reg     signal_o;
+
+//================================================================================
+//
+//  STATE MACHINE STATES
+//
+//================================================================================
+
+    localparam      SM_RST_S    = 1'b0;
+    localparam      SM_DONE_S   = 1'b1;
+
+//================================================================================
+//
+//  REG/WIRE
+//
+//================================================================================
+
+    reg                         curr_state  = SM_RST_S;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt   = {DELAY_CNT_W{1'b0}};
+    reg                         delay_flag  = 1'b0;
+
+    reg                         next_state;
+    reg     [DELAY_CNT_W-1:0]   delay_cnt_next	=	{DELAY_CNT_W{1'b0}};
+    reg                         signal_next;
+
+//================================================================================
+//
+//  CODING
+//
+//================================================================================
+
+initial begin
+    curr_state  = SM_RST_S;
+    delay_cnt   = {DELAY_CNT_W{1'b0}};
+    signal_o    = 1'b1;
+    delay_flag  = 1'b0;
+end
+
+always @(posedge clk_i) begin
+    curr_state  <= next_state;
+    delay_cnt   <= delay_cnt_next;
+    signal_o    <= signal_next;
+    delay_flag  <= delay_cnt > (DELAY_VALUE - 1);
+end
+
+always @(*) begin
+    next_state      = SM_RST_S;
+    delay_cnt_next  = delay_cnt;
+    signal_next     = 1'b1;
+    case(curr_state)
+        SM_RST_S    : begin
+            if (delay_flag) begin
+                next_state      = SM_DONE_S;
+            end else begin
+                next_state      = SM_RST_S;
+                delay_cnt_next  = delay_cnt + {{(DELAY_CNT_W-1){1'b0}}, 1'b1};
+            end
+        end
+        SM_DONE_S   : begin
+            signal_next = 1'b0;
+            next_state  = SM_DONE_S;
+        end
+    endcase
+end
+
+endmodule

src/src/InterfaceArbiter/InterfaceArbiter.v

@@ -172,7 +172,7 @@ module InterfaceArbiter
 				if (!spiMode) begin
 					wordsNum <= dataRegSSpi[17:1];
 				end else begin
-					wordsNum <= dataRegQSpi[22:19]+dataRegQSpi[18:17]+dataRegQSpi[16]+dataRegQSpi[15]+dataRegQSpi[14]+dataRegQSpi[13:12]+dataRegQSpi[11:9]+dataRegQSpi[8:7];
+					wordsNum <= dataRegQSpi[21:19]+dataRegQSpi[17:16]+dataRegQSpi[15:12]+dataRegQSpi[10:9]+dataRegQSpi[7:6]+dataRegQSpi[4]+dataRegQSpi[2]+dataRegQSpi[1];
 				end 
 			end
 		end else begin

src/src/Top/TopSbTmsg.v

@@ -182,7 +182,9 @@ module TopSbTmsg
 	wire [3:0] lmxWordNum;
 	wire [2:0] ddsWordNum;
 	wire valWordNum;
-	
+
+	//InitRst
+	wire initRst;
 
 	reg misoReg;
 
@@ -333,6 +335,11 @@ ClkGen ClkGen
 	.Clk60Mhz_o			(clk60)
 );
 
+InitRst InitRst (
+	.clk_i		(clk24),
+	.signal_o	(initRst)
+);
+
 InterfaceArbiter 
 #(	
 	.OUTWORDWIDTH	(WORDWIDTH),
@@ -412,8 +419,8 @@ LmxWrapper #(
 	.DATA_WIDTH			(24)
 ) LmxWrapper(
 	.WrClk_i			(gclk100),
-	.RdClk_i			(clk26dot25),
-	.Rst_i				(Rst_i),
+	.RdClk_i			(clk5),
+	.Rst_i				(initRst),
 	.Data_i				(spiData),
 	.Val_i				(valLmxDataToFifo),
 	.LmxWordNum_i		(lmxWordNum),
@@ -432,8 +439,8 @@ DDSWrapper #(
 	.DATA_WIDTH			(64)
 ) DDSWrapper(
 	.WrClk_i			(gclk100),
-	.RdClk_i			(clk50),
-	.Rst_i				(Rst_i),
+	.RdClk_i			(clk5),
+	.Rst_i				(initRst),
 	.DdsWordNum_i		(ddsWordNum),
 	.DdsWordNumVal_i	(valWordNum),
 	.DdsDirectFlag_i	(flagDirectDds),
@@ -453,7 +460,7 @@ PotWrapper #(
 ) PotWrapper(
 	.WrClk_i		(gclk100),
 	.RdClk_i		(clk5),
-	.Rst_i			(Rst_i),
+	.Rst_i			(initRst),
 	.Data_i			(spiData),
 	.Val_i			(valPotDataToFifo),
 	.Ss_o			(potCsSpiM),
@@ -468,8 +475,8 @@ DacWrapper #(
 	.DATA_WIDTH		(16)
 ) DacWrapper(
 	.WrClk_i		(gclk100),
-	.RdClk_i		(clk50),
-	.Rst_i			(Rst_i),
+	.RdClk_i		(clk5),
+	.Rst_i			(initRst),
 	.Data_i			(spiData),
 	.Val_i			(valDacDataToFifo),
 	.Ss_o			(dacCsSpiM),
@@ -484,8 +491,8 @@ AttenuatorWrapper #(
 	.DATA_WIDTH		(16)
 ) AttenuatorWrapper(
 	.WrClk_i		(gclk100),
-	.RdClk_i		(clk50),
-	.Rst_i			(Rst_i),
+	.RdClk_i		(clk5),
+	.Rst_i			(initRst),
 	.Data_i			(spiData),
 	.Val_i			(valAttDataToFifo),
 	.Ss_o			(attCsSpiM),
@@ -500,8 +507,8 @@ ShiftRegWrapper #(
 	.DATA_WIDTH		(8)
 ) ShiftRegWrapper(
 	.WrClk_i		(gclk100),
-	.RdClk_i		(clk26dot25),
-	.Rst_i			(Rst_i),
+	.RdClk_i		(clk5),
+	.Rst_i			(initRst),
 	.Data_i			(spiData),
 	.Val_i			(valShRegDataToFifo),
 	.Ss_o			(shRegCsSpiM),
@@ -516,8 +523,8 @@ Max2870Wrapper #(
 	.DATA_WIDTH		(32)
 ) Max2870Wrapper(
 	.WrClk_i		(gclk100),
-	.RdClk_i		(clk20),
-	.Rst_i			(Rst_i),
+	.RdClk_i		(clk5),
+	.Rst_i			(initRst),
 	.Data_i			(spiData),
 	.Val_i			(valMaxDataToFifo),
 	.Ss_o			(maxCsSpiM),
@@ -527,7 +534,7 @@ Max2870Wrapper #(
 
 TempRead TempRead (
 	.Clk24Mhz_i				(clk24),
-	.Rst_i					(Rst_i),
+	.Rst_i					(initRst),
 	.ClkSpi_i				(Sck_i),
 	.FlagDirectTempRead_i	(flagDirectTemp),
 	.I2cScl_o				(I2cScl_o),

src/src/Top/TopSbTmsgTb.sv

@@ -182,7 +182,7 @@ initial begin
       PulsePol_i = 0;
       // Reset the system
       #(CLK_PERIOD*10) Rst_i = 0;
-      #(300000-60) rstForFPGA = 1;
+      #(700000-60) rstForFPGA = 1;
       #(CLK_PERIOD*74) rstForFPGA = 0;
       #(165000) Start_i = 1; // Start SPI transaction
       wait (trCnt == 70) begin 

src/src/WrapFifoChain/DDSWrapper.v

@@ -58,6 +58,7 @@ reg ssR;
 reg ssReg;
 reg ddsDirectFlagR;
 reg [2:0] ddsWordNumReg;
+reg [2:0] ddsWordNumRegSync;
 //==========================================================================//
 //									CODING									//
 //==========================================================================//
@@ -99,6 +100,15 @@ always @(posedge WrClk_i) begin
 	end
 end
 
+always @(posedge RdClk_i) begin 
+	if (Rst_i) begin 
+		ddsWordNumRegSync <= 3'h0;
+	end
+	else begin 
+		ddsWordNumRegSync <= ddsWordNumReg;
+	end
+end
+
 always @(posedge RdClk_i) begin 
 	if (Rst_i) begin 
 		DdsSyncFpga_o <= 1'b0;
@@ -107,11 +117,11 @@ always @(posedge RdClk_i) begin
 		if (ddsDirectFlagR && !DdsDirectFlag_i) begin 
 				DdsSyncFpga_o <= 1'b1;
 		end 
-		else if ((!Ss_o && ssReg) && (ddsWordNumReg != 0)) begin 
+		else if ((!Ss_o && ssReg) && (ddsWordNumRegSync != 0)) begin 
 			DdsSyncFpga_o <= 1'b0;
 		end
 		else begin 
-			if (ddsWordNumReg == 3'h1 && (Ss_o && !ssReg)) begin 
+			if (ddsWordNumRegSync == 3'h1 && (Ss_o && !ssReg)) begin 
 				DdsSyncFpga_o <= 1'b1;
 			end
 			else begin 

src/src/WrapFifoChain/LmxWrapper.v

@@ -95,9 +95,9 @@ always @(posedge WrClk_i) begin
 				end
 			end
 		end
-		else begin 
-			PllVtuneCtrl_o <= ~LmxDirectFlag_i;
-		end
+		// else begin 
+		// 	PllVtuneCtrl_o <= ~LmxDirectFlag_i;
+		// end
 	end
 end