Исправил названия регистров

src/src/PacketAnalyzer4Mosi/PacketAnalyzer4Mosi.v

@@ -49,7 +49,7 @@ module PacketAnalyzer4Mosi (
 //==========================================
 // Registers
 //==========================================
-reg [22:0] DataSpiReg;
+reg [22:0] dataSpiReg;
 
 //==========================================
 // Wires
@@ -80,14 +80,14 @@ localparam [22:0] DECREMENT_GPIO 	= 23'h80;		//23'b000 0000 0000 0000 1000 0000
 //==========================================
 // Assignments
 //==========================================
-assign lmxOr 	= 	|DataSpiReg[22:19];
-assign ddsOr 	= 	|DataSpiReg[18:17];
-assign potOr 	= 	 DataSpiReg[16];
-assign dacOr 	= 	 DataSpiReg[15];
-assign attOr 	= 	 DataSpiReg[14];
-assign shRegOr 	= 	|DataSpiReg[13:12];
-assign maxOr 	= 	|DataSpiReg[11:9];
-assign gpioOr 	= 	|DataSpiReg[8:7];
+assign lmxOr 	= 	|dataSpiReg[22:19];
+assign ddsOr 	= 	|dataSpiReg[18:17];
+assign potOr 	= 	 dataSpiReg[16];
+assign dacOr 	= 	 dataSpiReg[15];
+assign attOr 	= 	 dataSpiReg[14];
+assign shRegOr 	= 	|dataSpiReg[13:12];
+assign maxOr 	= 	|dataSpiReg[11:9];
+assign gpioOr 	= 	|dataSpiReg[8:7];
 
 assign selector = {lmxOr, ddsOr, potOr, dacOr, attOr, shRegOr, maxOr, gpioOr};
 
@@ -98,7 +98,7 @@ always @(posedge Clk_i) begin
 	if (Rst_i) begin
 		Busy_o <= 1'b0;
 	end
-	else if (DataSpiReg != 0) begin
+	else if (dataSpiReg != 0) begin
 		Busy_o <= 1'b1;
 	end
 	else begin
@@ -108,7 +108,7 @@ end
 
 always @(posedge Clk_i) begin
 	if (Rst_i || BusyMosi1_i) begin
-		DataSpiReg <= 23'b0;
+		dataSpiReg <= 23'b0;
 		ValLmxDataToFifo_o <= 1'b0;
 		ValDdsDataToFifo_o <= 1'b0;
 		ValPotDataToFifo_o <= 1'b0;
@@ -119,41 +119,41 @@ always @(posedge Clk_i) begin
 		ValGpioDataToFifo_o <= 1'b0;
 	end
 	else if (ValDataFromSpi_i) begin
-		if ((DataSpiReg == 0) && (DataFromSpi_i[23] == 1'b1)) begin
-			DataSpiReg <= DataFromSpi_i[22:0];
+		if ((dataSpiReg == 0) && (DataFromSpi_i[23] == 1'b1)) begin
+			dataSpiReg <= DataFromSpi_i[22:0];
 		end
 		else begin
 			casez(selector)
 			8'b1???????: begin //LMX
-				DataSpiReg <= DataSpiReg - DECREMENT_LMX;
+				dataSpiReg <= dataSpiReg - DECREMENT_LMX;
 				ValLmxDataToFifo_o <= 1'b1;
 			end
 			8'b01??????: begin //DDS
-				DataSpiReg <= DataSpiReg - DECREMENT_DDS;
+				dataSpiReg <= dataSpiReg - DECREMENT_DDS;
 				ValDdsDataToFifo_o <= 1'b1;
 			end
 			8'b001?????: begin //POT
-				DataSpiReg <= DataSpiReg - DECREMENT_POT;
+				dataSpiReg <= dataSpiReg - DECREMENT_POT;
 				ValPotDataToFifo_o <= 1'b1;
 			end
 			8'b0001????: begin //DAC
-				DataSpiReg <= DataSpiReg - DECREMENT_DAC;
+				dataSpiReg <= dataSpiReg - DECREMENT_DAC;
 				ValDacDataToFifo_o <= 1'b1;
 			end
 			8'b00001???: begin //ATT
-				DataSpiReg <= DataSpiReg - DECREMENT_ATT;
+				dataSpiReg <= dataSpiReg - DECREMENT_ATT;
 				ValAttDataToFifo_o <= 1'b1;
 			end
 			8'b000001??: begin //ShReg
-				DataSpiReg <= DataSpiReg - DECREMENT_SH_REG;
+				dataSpiReg <= dataSpiReg - DECREMENT_SH_REG;
 				ValShRegDataToFifo_o <= 1'b1;
 			end
 			8'b0000001?: begin //MAX2870
-				DataSpiReg <= DataSpiReg - DECREMENT_MAX;
+				dataSpiReg <= dataSpiReg - DECREMENT_MAX;
 				ValMaxDataToFifo_o <= 1'b1;
 			end
 			8'b00000001: begin //GPIO
-				DataSpiReg <= DataSpiReg - DECREMENT_GPIO;
+				dataSpiReg <= dataSpiReg - DECREMENT_GPIO;
 				ValGpioDataToFifo_o <= 1'b1;
 			end
 			default: begin
@@ -169,35 +169,35 @@ always @(posedge Clk_i) begin
 		endcase
 //=========================DELETE AFTER HARDWARE TEST===========================
 			/*if (lmxOr) begin //LMX
-				DataSpiReg <= DataSpiReg - DECREMENT_LMX;
+				dataSpiReg <= dataSpiReg - DECREMENT_LMX;
 				ValLmxDataToFifo_o 		<= 1'b1;
 			end
 			else if (ddsOr) begin //DDS
-				DataSpiReg <= DataSpiReg - DECREMENT_DDS;
+				dataSpiReg <= dataSpiReg - DECREMENT_DDS;
 				ValDdsDataToFifo_o 		<= 1'b1;
 			end
 			else if (potOr) begin //POT
-				DataSpiReg <= DataSpiReg - DECREMENT_POT;
+				dataSpiReg <= dataSpiReg - DECREMENT_POT;
 				ValPotDataToFifo_o 		<= 1'b1;
 			end
 			else if (dacOr) begin //DAC
-				DataSpiReg <= DataSpiReg - DECREMENT_DAC;
+				dataSpiReg <= dataSpiReg - DECREMENT_DAC;
 				ValDacDataToFifo_o 		<= 1'b1;
 			end
 			else if (attOr) begin
-				DataSpiReg <= DataSpiReg - DECREMENT_ATT;
+				dataSpiReg <= dataSpiReg - DECREMENT_ATT;
 				ValAttDataToFifo_o 		<= 1'b1;
 			end
 			else if (shRegOr) begin
-				DataSpiReg <= DataSpiReg - DECREMENT_SH_REG;
+				dataSpiReg <= dataSpiReg - DECREMENT_SH_REG;
 				ValShRegDataToFifo_o 	<= 1'b1;
 			end
 			else if (maxOr) begin
-				DataSpiReg <= DataSpiReg - DECREMENT_MAX;
+				dataSpiReg <= dataSpiReg - DECREMENT_MAX;
 				ValMaxDataToFifo_o 		<= 1'b1;
 			end
 			else if (gpioOr) begin
-				DataSpiReg <= DataSpiReg - DECREMENT_GPIO;
+				dataSpiReg <= dataSpiReg - DECREMENT_GPIO;
 				ValGpioDataToFifo_o 	<= 1'b1;
 			end
 			else begin

src/src/PacketAnalyzer4Mosi/PacketAnalyzer4MosiTb.v

@@ -33,8 +33,8 @@ reg clkMain_tb;
 reg rstMain_tb;
 reg busyMosi1_tb;
 
-reg [23:0] DataFromSpi_tb;
-reg ValDataFromSpi_tb;
+reg [23:0] dataFromSpi_tb;
+reg valdataFromSpi_tb;
 
 always #10 clkMain_tb = ~clkMain_tb;
 
@@ -54,18 +54,18 @@ always @(posedge clkMain_tb) begin
 	if (rstMain_tb) begin
 		cnt <= 0;
 		state <= 0;
-		ValDataFromSpi_tb <= 0;	
-		DataFromSpi_tb <= 0;
+		valdataFromSpi_tb <= 0;	
+		dataFromSpi_tb <= 0;
 		countState <= 0;
 	end
 	else begin
 		case(state)
 			0: begin
-				DataFromSpi_tb <= CFG_REG;
+				dataFromSpi_tb <= CFG_REG;
 
 				if (cnt == 6) begin
 					cnt <= 0;
-					ValDataFromSpi_tb <= 1;
+					valdataFromSpi_tb <= 1;
 					state <= state + 1;
 				end
 				else begin
@@ -74,7 +74,7 @@ always @(posedge clkMain_tb) begin
 				end
 			end
 			1: begin
-				ValDataFromSpi_tb <= 0;
+				valdataFromSpi_tb <= 0;
 				if (cnt == 1) begin
 					cnt <= 0;
 					state <= state + 1;
@@ -85,11 +85,11 @@ always @(posedge clkMain_tb) begin
 				end
 			end
 			2: begin
-				DataFromSpi_tb <= 24'hA; //DATA0
+				dataFromSpi_tb <= 24'hA; //DATA0
 
 				if (cnt == 6) begin
 					cnt <= 0;
-					ValDataFromSpi_tb <= 1;
+					valdataFromSpi_tb <= 1;
 					state <= state + 1;
 					countState <= countState + 1;
 				end
@@ -99,7 +99,7 @@ always @(posedge clkMain_tb) begin
 				end
 			end
 			3: begin
-				ValDataFromSpi_tb <= 0;
+				valdataFromSpi_tb <= 0;
 				if (countState == CNT_DATA_WORDS) begin
 					state <= 5;
 				end
@@ -113,11 +113,11 @@ always @(posedge clkMain_tb) begin
 				end
 			end
 			4: begin
-				DataFromSpi_tb <= 24'hF; //DATA1
+				dataFromSpi_tb <= 24'hF; //DATA1
 
 				if (cnt == 6) begin
 					cnt <= 0;
-					ValDataFromSpi_tb <= 1;
+					valdataFromSpi_tb <= 1;
 					state <= state + 1;
 					countState <= countState + 1;
 				end
@@ -127,7 +127,7 @@ always @(posedge clkMain_tb) begin
 				end
 			end
 			5: begin
-				ValDataFromSpi_tb <= 0;
+				valdataFromSpi_tb <= 0;
 				if (countState == CNT_DATA_WORDS) begin
 					state <= state;
 				end
@@ -148,8 +148,8 @@ PacketAnalyzer4Mosi DUT (
 	.Clk_i					(clkMain_tb),	
 	.Rst_i					(rstMain_tb),	
 	
-	.DataFromSpi_i 			(DataFromSpi_tb),
-	.ValDataFromSpi_i 		(ValDataFromSpi_tb),
+	.DataFromSpi_i 			(dataFromSpi_tb),
+	.ValDataFromSpi_i 		(valdataFromSpi_tb),
 	
 	.BusyMosi1_i			(busyMosi1_tb),