Merge branch 'dev' into Anatoliy/feature_FifoCtrl

src/src/InterfaceArbiter/ExtQspiMEmul.v

@@ -32,8 +32,8 @@ module ExtQSpiMEmul
 	parameter [1:0] SHREG = 2'h1;
 	parameter [2:0] MAX2870 = 3'h1;
 	parameter [1:0] GPIO = 2'h1;
-	parameter [5:0] RESERVED = 6'h1;
-	parameter EOPBIT = 1'b1;
+	parameter [5:0] RESERVED = 6'h0;
+	parameter EOPBIT = 1'b0;
 	
 //================================================================================
 //  REG/WIRE
@@ -44,6 +44,8 @@ module ExtQSpiMEmul
 	reg	[6:0]	cmdCnt;
 	reg	[3:0]	pauseCnt;
 
+	
+	
 	wire	txStop	=	(cmdCnt	>=	LMX+DDS+POT+DAC+ATT+SHREG+MAX2870+GPIO+1);
 	
 	reg [23:0] headerCmd = {MODE,LMX,DDS,POT,DAC,ATT,SHREG,MAX2870,GPIO,RESERVED,EOPBIT};
@@ -52,6 +54,9 @@ module ExtQSpiMEmul
 	reg	[23:0]	dspSpiData;
 	
 	reg sckFlag;
+	
+	wire [22:0] testWidre = headerCmd[22:0];
+	
 //================================================================================
 //  ASSIGNMENTS
 

src/src/InterfaceArbiter/InterfaceArbiter.v

@@ -22,9 +22,9 @@
 
 module InterfaceArbiter 
 #(	
-	parameter OutWordWith = 24,
-	parameter SingleSpiWordWith = 24,
-	parameter QuadSpiWordWith = 6
+	parameter OUTWORDWIDTH = 24,
+	parameter SSPIWORDWIDTH = 24,
+	parameter QSPIWORDWIDTH = SSPIWORDWIDTH/4
 )
 (
 	input Rst_i,
@@ -40,7 +40,7 @@ module InterfaceArbiter
 	
 	
 	input DataVal_o,
-	input [OutWordWith-1:0] Data_o
+	input [OUTWORDWIDTH-1:0] Data_o
 );
 
 //================================================================================
@@ -49,15 +49,15 @@ module InterfaceArbiter
 	localparam [1:0] IDLE = 0;
 	localparam [1:0] DATARX = 1;
 	
-	reg [OutWordWith-1:0] dataRegSSpi;
-	reg [OutWordWith-1:0] dataRegQSpi;
+	reg [OUTWORDWIDTH-1:0] dataRegSSpi;
+	reg [OUTWORDWIDTH-1:0] dataRegQSpi;
 	
-	reg [OutWordWith-1:0] captRegSspi;
+	reg [OUTWORDWIDTH-1:0] captRegSspi;
 	
-	reg [QuadSpiWordWith-1:0] captReg0;
-	reg [QuadSpiWordWith-1:0] captReg1;
-	reg [QuadSpiWordWith-1:0] captReg2;
-	reg [QuadSpiWordWith-1:0] captReg3;
+	reg [QSPIWORDWIDTH-1:0] captReg0;
+	reg [QSPIWORDWIDTH-1:0] captReg1;
+	reg [QSPIWORDWIDTH-1:0] captReg2;
+	reg [QSPIWORDWIDTH-1:0] captReg3;
 	
 	reg ssReg;
 	reg ssRegR;
@@ -70,9 +70,9 @@ module InterfaceArbiter
 	
 	reg dataValReg;
 	
-	reg [OutWordWith/4-1:0] ssCnt;
-	reg [OutWordWith/4-1:0] wordsCnt;
-	wire [OutWordWith/4-1:0] ssCntRstThresh = (spiMode) ? QuadSpiWordWith-1:SingleSpiWordWith-1;
+	reg [OUTWORDWIDTH/4-1:0] ssCnt;
+	reg [OUTWORDWIDTH/4-1:0] wordsCnt;
+	wire [OUTWORDWIDTH/4-1:0] ssCntRstThresh = (spiMode) ? QSPIWORDWIDTH-1:SSPIWORDWIDTH-1;
 	
 	reg [16:0] wordsNum;
 	
@@ -93,12 +93,12 @@ module InterfaceArbiter
 	always @(posedge Sck_i) begin
 		if (!Rst_i) begin
 			if (!Ss_i) begin
-				captRegSspi <= {captRegSspi[OutWordWith-2:0], Mosi0_i};
+				captRegSspi <= {captRegSspi[OUTWORDWIDTH-2:0], Mosi0_i};
 				
-				captReg0 <= {captReg0[QuadSpiWordWith-2:0], Mosi0_i};
-				captReg1 <= {captReg1[QuadSpiWordWith-2:0], Mosi1_i};
-				captReg2 <= {captReg2[QuadSpiWordWith-2:0], Mosi2_i};
-				captReg3 <= {captReg3[QuadSpiWordWith-2:0], Mosi3_i};
+				captReg0 <= {captReg0[QSPIWORDWIDTH-2:0], Mosi0_i};
+				captReg1 <= {captReg1[QSPIWORDWIDTH-2:0], Mosi1_i};
+				captReg2 <= {captReg2[QSPIWORDWIDTH-2:0], Mosi2_i};
+				captReg3 <= {captReg3[QSPIWORDWIDTH-2:0], Mosi3_i};
 			end
 		end else begin
 			captRegSspi <= 0;
@@ -165,13 +165,11 @@ module InterfaceArbiter
 	always @(posedge Clk_i) begin
 		if (!Rst_i) begin
 			if (currState == IDLE) begin
-				// if (ssPos) begin
-					if (!spiMode) begin
-						wordsNum <= dataRegSSpi[17:1];
-					end else begin
-						wordsNum <= dataRegQSpi[22:19]+dataRegQSpi[18:17]+dataRegQSpi[16]+dataRegQSpi[15]+dataRegQSpi[14]+dataRegQSpi[13:12]+dataRegQSpi[11:9]+dataRegQSpi[8:7];
-					end 
-				// end
+				if (!spiMode) begin
+					wordsNum <= dataRegSSpi[17:1];
+				end else begin
+					wordsNum <= dataRegQSpi[22:19]+dataRegQSpi[18:17]+dataRegQSpi[16]+dataRegQSpi[15]+dataRegQSpi[14]+dataRegQSpi[13:12]+dataRegQSpi[11:9]+dataRegQSpi[8:7];
+				end 
 			end
 		end else begin
 			wordsNum <= 0;

src/src/PacketAnalyzer1Mosi/PacketAnalyzer1Mosi.v

@@ -82,15 +82,21 @@ always @(posedge Clk_i) begin
 		cntData <= 17'b0;
 	end 
 	else if (ValDataFromSpi_i) begin
-		if ((cntData == 0) && (DataFromSpi_i[23] == 0)) begin
-			cntData <= DataFromSpi_i[17:1];
-			devId 	<= DataFromSpi_i[22:18];
-		end
+		if (cntData == 0) begin 
+			if (DataFromSpi_i[23] == 0) begin
+				cntData <= DataFromSpi_i[17:1];
+				devId 	<= DataFromSpi_i[22:18];
+			end
+			else begin
+				cntData <= 5'b0;
+				devId 	<= 17'b0;
+			end
+		end	
 		else begin
 			cntData <= cntData - 1'b1;	
 		end
 	end
-	else if (cntData == 17'b0) begin
+	else if (cntData == 0) begin
 		devId <= 5'b0;
 	end
 end

src/src/Top/ExtQspiMEmul.v

@@ -0,0 +1,238 @@
+`timescale 1ns / 1ps
+
+module ExtQSpiMEmul 
+(
+	input Rst_i,
+	input Clk_i,
+	
+	input Start_i,
+	output TxDone_o,
+	
+	output Sck_o,
+	output reg Ss_o,
+	output reg Mosi0_o,
+	output reg Mosi1_o,
+	output reg Mosi2_o,
+	output reg Mosi3_o
+);
+
+//================================================================================
+//  PARAMETERS
+	localparam [1:0] IDLE = 0;
+	localparam [1:0] CMD = 1;
+	localparam [1:0] TX = 2;
+	localparam [1:0] PAUSE = 3;
+
+	parameter MODE = 1'h1;
+	parameter [3:0] LMX = 4'h1;
+	parameter [1:0] DDS = 2'h1;
+	parameter POT = 1'h1;
+	parameter DAC = 1'h1;
+	parameter ATT = 1'h1;
+	parameter [1:0] SHREG = 2'h1;
+	parameter [2:0] MAX2870 = 3'h1;
+	parameter [1:0] GPIO = 2'h1;
+	parameter [5:0] RESERVED = 6'h0;
+	parameter EOPBIT = 1'b0;
+	
+//================================================================================
+//  REG/WIRE
+	reg [1:0] currState;
+	reg [1:0] nextState;
+	
+	reg	[6:0]	txCnt;
+	reg	[6:0]	cmdCnt;
+	reg	[3:0]	pauseCnt;
+
+	
+	
+	wire	txStop	=	(cmdCnt	>=	LMX+DDS+POT+DAC+ATT+SHREG+MAX2870+GPIO+1);
+	
+	reg [23:0] headerCmd = {MODE,LMX,DDS,POT,DAC,ATT,SHREG,MAX2870,GPIO,RESERVED,EOPBIT};
+	reg [23:0] spiData;
+	
+	reg	[23:0]	dspSpiData;
+	
+	reg sckFlag;
+	
+	wire [22:0] testWidre = headerCmd[22:0];
+	
+//================================================================================
+//  ASSIGNMENTS
+
+assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b1;
+assign	TxDone_o	=	(txStop & (currState== CMD));
+
+//================================================================================
+//  CODING
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	CMD)	begin
+			if	(!txStop)	begin
+				cmdCnt	<=	cmdCnt+1;
+			end else begin
+				cmdCnt <= 0;
+			end
+		end
+	end	else	begin
+		cmdCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	TX)	begin
+			txCnt	<=	txCnt+1;
+		end	else	begin
+			txCnt	<=	0;
+		end
+	end	else	begin
+		txCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	PAUSE)	begin
+			pauseCnt	<=	pauseCnt+1;
+		end	else	begin
+			pauseCnt	<=	0;
+		end
+	end	else	begin
+		pauseCnt	<=	0;
+	end
+end
+	
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	CMD)	begin
+			spiData	<=	spiData+cmdCnt;
+		end
+	end	else	begin
+		spiData	<=	24'hab;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(currState	==	CMD)	begin
+		if	(cmdCnt	==	0)	begin
+			dspSpiData		<=	headerCmd;
+		end	else	begin
+			dspSpiData		<=	spiData;
+		end	
+	end	else	if	(currState	==	TX)	begin
+		dspSpiData	<=	dspSpiData<<1;
+	end if	(currState	==	IDLE)	begin
+		dspSpiData	<=	0;
+	end
+end
+
+always	@(posedge Clk_i)	begin
+	if	(currState	==	TX)	begin
+		if	(txCnt	>=	7'd0)	begin
+			Mosi0_o	<=	dspSpiData[23];
+			Mosi1_o	<=	dspSpiData[17];
+			Mosi2_o	<=	dspSpiData[11];
+			Mosi3_o	<=	dspSpiData[5];
+		end	else	begin
+			Mosi0_o	<=	1'b1;
+			Mosi1_o	<=	1'b1;
+			Mosi2_o	<=	1'b1;
+			Mosi3_o	<=	1'b1;
+		end
+	end	else	begin
+		Mosi0_o	<=	1'b1;
+		Mosi1_o	<=	1'b1;
+		Mosi2_o	<=	1'b1;
+		Mosi3_o	<=	1'b1;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(currState	==	TX)	begin
+		Ss_o	<=	1'b0;
+		sckFlag	<=	1'b1;
+	end	else	begin
+		Ss_o	<=	1'b1;
+		sckFlag	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(Rst_i)	begin
+		currState	<=	IDLE;
+	end	else	begin
+		currState	<=	nextState;
+	end
+end
+
+
+always	@(posedge	Clk_i)	begin
+	if	(Rst_i)	begin
+		currState	<=	IDLE;
+	end	else	begin
+		currState	<=	nextState;
+	end
+end
+
+
+always @(*) begin
+	nextState	=	IDLE;
+	case(currState)
+	IDLE	:	begin
+					if (Start_i)	begin
+						nextState = CMD;
+					end	else begin
+						nextState = IDLE;
+					end
+				end
+				
+	CMD	:		begin
+					if (!txStop)	begin
+						nextState = TX;
+					end	else begin
+						nextState = IDLE;
+					end
+				end
+
+	TX		:	begin
+					if (txCnt==6'd5) begin
+						nextState  = PAUSE;
+					end	else begin
+						nextState  = TX;
+					end
+				end
+        
+	PAUSE	:	begin
+					if (pauseCnt==4'd2) begin
+						nextState  = CMD;
+					end	else begin
+						nextState  = PAUSE;
+					end
+				end
+	endcase
+end
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/Top/ExtSpiMEmul.v

@@ -0,0 +1,205 @@
+`timescale 1ns / 1ps
+
+module ExtSpiMEmul 
+(
+	input Rst_i,
+	input Clk_i,
+	
+	input Start_i,
+	output TxDone_o,
+	
+	output Sck_o,
+	output reg Ss_o,
+	output reg Mosi_o
+	
+);
+
+//================================================================================
+//  PARAMETERS
+	localparam [1:0] IDLE = 0;
+	localparam [1:0] CMD = 1;
+	localparam [1:0] TX = 2;
+	localparam [1:0] PAUSE = 3;
+
+	parameter MODE = 1'h0;
+	parameter [4:0] DEVID = 5'h1;
+	parameter [16:0] WORDSNUM = 17'h3;
+	parameter EOPBIT = 1'b1;
+	
+//================================================================================
+//  REG/WIRE
+	reg [1:0] currState;
+	reg [1:0] nextState;
+	
+	reg	[6:0]	txCnt;
+	reg	[6:0]	cmdCnt;
+	reg	[3:0]	pauseCnt;
+
+	wire	txStop	=	(cmdCnt	>=	WORDSNUM+1);
+	
+	reg [23:0] headerCmd = {MODE,DEVID,WORDSNUM,EOPBIT};
+	reg [23:0] spiData;
+	
+	reg	[23:0]	dspSpiData;
+	
+	reg sckFlag;
+//================================================================================
+//  ASSIGNMENTS
+
+assign	Sck_o		=	(sckFlag)? ~Clk_i:1'b1;
+assign	TxDone_o	=	(txStop & (currState== CMD));
+
+//================================================================================
+//  CODING
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	CMD)	begin
+			if	(!txStop)	begin
+				cmdCnt	<=	cmdCnt+1;
+			end else begin
+				cmdCnt <= 0;
+			end
+		end
+	end	else	begin
+		cmdCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	TX)	begin
+			txCnt	<=	txCnt+1;
+		end	else	begin
+			txCnt	<=	0;
+		end
+	end	else	begin
+		txCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	PAUSE)	begin
+			pauseCnt	<=	pauseCnt+1;
+		end	else	begin
+			pauseCnt	<=	0;
+		end
+	end	else	begin
+		pauseCnt	<=	0;
+	end
+end
+	
+always	@(posedge	Clk_i)	begin
+	if	(!Rst_i)	begin
+		if	(currState	==	CMD)	begin
+			spiData	<=	spiData+cmdCnt;
+		end
+	end	else	begin
+		spiData	<=	24'hab;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(currState	==	CMD)	begin
+		if	(cmdCnt	==	0)	begin
+			dspSpiData		<=	headerCmd;
+		end	else	begin
+			dspSpiData		<=	spiData;
+		end	
+	end	else	if	(currState	==	TX)	begin
+		dspSpiData	<=	dspSpiData<<1;
+	end if	(currState	==	IDLE)	begin
+		dspSpiData	<=	0;
+	end
+end
+
+always	@(posedge Clk_i)	begin
+	if	(currState	==	TX)	begin
+		if	(txCnt	>=	7'd0)	begin
+			Mosi_o	<=	dspSpiData[23];
+		end	else	begin
+			Mosi_o	<=	1'b1;
+		end
+	end	else	begin
+		Mosi_o	<=	1'b1;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(currState	==	TX)	begin
+		Ss_o	<=	1'b0;
+		sckFlag	<=	1'b1;
+	end	else	begin
+		Ss_o	<=	1'b1;
+		sckFlag	<=	1'b0;
+	end
+end
+
+always	@(posedge	Clk_i)	begin
+	if	(Rst_i)	begin
+		currState	<=	IDLE;
+	end	else	begin
+		currState	<=	nextState;
+	end
+end
+
+always @(*) begin
+	nextState	=	IDLE;
+	case(currState)
+	IDLE	:	begin
+					if (Start_i)	begin
+						nextState = CMD;
+					end	else begin
+						nextState = IDLE;
+					end
+				end
+				
+	CMD	:		begin
+					if (!txStop)	begin
+						nextState = TX;
+					end	else begin
+						nextState = IDLE;
+					end
+				end
+
+	TX		:	begin
+					if (txCnt==6'd23) begin
+						nextState  = PAUSE;
+					end	else begin
+						nextState  = TX;
+					end
+				end
+        
+	PAUSE	:	begin
+					if (pauseCnt==4'd2) begin
+						nextState  = CMD;
+					end	else begin
+						nextState  = PAUSE;
+					end
+				end
+	endcase
+end
+
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

src/src/Top/TopSbTmsg.v

@@ -23,8 +23,9 @@
 
 module TopSbTmsg 
 #(
-    parameter DevNum = 8,
-    parameter WordWidth = 24
+    parameter DEVNUM = 8,
+    parameter WORDWIDTH = 24,
+    parameter SSPIWORDWIDTH = 24
 ) 
 (
 	input Clk_i,
@@ -45,9 +46,9 @@ module TopSbTmsg
 	output I2CSck_o,
 	inout I2CSda_io,
 	
-	output [DevNum-1:0] Ss_o,
-	output [DevNum-1:0] Sck_o,
-	output [DevNum-1:0] Mosi_o,
+	output [DEVNUM-1:0] Ss_o,
+	output [DEVNUM-1:0] Sck_o,
+	output [DEVNUM-1:0] Mosi_o,
 	
 	output [21:0] Gpio_o
 );
@@ -57,16 +58,43 @@ module TopSbTmsg
 
 
 //================================================================================
+//  REG/WIRE
 
-wire clk360;
-wire clk100;
-wire clk75;
-wire clk50;
-wire clk40;
-wire clk20;
-wire clk30;
-wire clk5;
+	wire clk360;
+	wire clk100;
+	wire clk75;
+	wire clk50;
+	wire clk40;
+	wire clk20;
+	wire clk30;
+	wire clk5;
 
+	wire spiDataVal;
+	wire [WORDWIDTH-1:0] spiData;
+	
+	wire busyMosi1;
+	wire busyMosi4;
+	
+	wire valLmxDataToFifo;		
+	wire valDdsDataToFifo;		
+	wire valPotDataToFifo;		
+	wire valDacDataToFifo;		
+	wire valAttDataToFifo;		
+	wire valShRegDataToFifo;	
+	wire valMaxDataToFifo;		
+	wire valGpioDataToFifo;	
+	
+	wire flagDirectLmx;	
+	wire flagDirectDds;	
+	wire flagDirectPot;	
+	wire flagDirectDac;	
+	wire flagDirectAtt;	
+	wire flagDirectShReg;	
+	wire flagDirectMax;	
+	wire flagDirectGpio;	
+	wire flagDirectTemp;	
+	
+	
 //================================================================================
 //  ASSIGNMENTS
 
@@ -77,6 +105,75 @@ wire clk5;
 //================================================================================
 //  CODING
 
+InterfaceArbiter 
+#(	
+	.OUTWORDWIDTH (WORDWIDTH),
+	.SSPIWORDWIDTH (SSPIWORDWIDTH)
+)
+SpiSlaveArbiter
+(
+	.Rst_i		(Rst_i),
+	// .Clk_i		(clk100),
+	.Clk_i		(Clk_i),
+	
+	.Sck_i		(Sck_i),
+	.Ss_i		(Ss_i),
+	
+	.Mosi0_i	(Mosi0_i),
+	.Mosi1_i	(Mosi1_io),
+	.Mosi2_i	(Mosi2_i),
+	.Mosi3_i	(Mosi3_i),
+	
+	
+	.DataVal_o	(spiDataVal),
+	.Data_o		(spiData)
+);
+
+PacketAnalyzer4Mosi PacketAnalyzer4Mosi
+(
+	// .Clk_i	(clk100),
+	.Clk_i	(Clk_i),
+	.Rst_i	(Rst_i),
+
+	.DataFromSpi_i		(spiData),
+	.ValDataFromSpi_i	(spiDataVal),
+
+	.BusyMosi1_i	(busyMosi1),
+
+	.ValLmxDataToFifo_o		(valLmxDataToFifo),
+	.ValDdsDataToFifo_o		(valDdsDataToFifo),
+	.ValPotDataToFifo_o		(valPotDataToFifo),
+	.ValDacDataToFifo_o		(valDacDataToFifo),
+	.ValAttDataToFifo_o		(valAttDataToFifo),
+	.ValShRegDataToFifo_o	(valShRegDataToFifo),
+	.ValMaxDataToFifo_o		(valMaxDataToFifo),
+	.ValGpioDataToFifo_o	(valGpioDataToFifo),
+
+	.Busy_o	(busyMosi4)
+);
 
+PacketAnalyzer1Mosi PacketAnalyzer1Mosi
+(
+	// .Clk_i	(clk100),
+	.Clk_i	(Clk_i),
+	.Rst_i	(Rst_i),
+
+	.DataFromSpi_i		(spiData),
+	.ValDataFromSpi_i	(spiDataVal),
+
+	.BusyMosi4_i	(busyMosi4),
+
+	.FlagDirectLmx_o	(flagDirectLmx),
+	.FlagDirectDds_o	(flagDirectDds),
+	.FlagDirectPot_o	(flagDirectPot),
+	.FlagDirectDac_o	(flagDirectDac),
+	.FlagDirectAtt_o	(flagDirectAtt),
+	.FlagDirectShReg_o	(flagDirectShReg),
+	.FlagDirectMax_o	(flagDirectMax),
+	.FlagDirectGpio_o	(flagDirectGpio),
+	.FlagDirectTemp_o	(flagDirectTemp),
+
+	.Busy_o	(busyMosi1)
+);
 
 endmodule

src/src/Top/TopSbTmsgTb.v

@@ -0,0 +1,275 @@
+`timescale 1ns / 1ps
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company: Tair
+// Engineer: Churbanov S.
+// 
+// Create Date:     
+// Design Name: 
+// Module Name:    InterfaceArbiter
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module TopSbTmsgTb();
+
+//================================================================================
+//  REG/WIRE
+	
+	parameter OUTWORDWIDTH = 24;
+	parameter SSPIWORDWIDTH = 24;
+	parameter QSPIWORDWIDTH = 6;
+	
+	localparam [1:0] IDLE = 0;
+	localparam [1:0] SINGLE = 1;
+	localparam [1:0] DELAY = 2;
+	localparam [1:0] QUAD = 3;
+	
+	reg spiMode = 1'b0; //0 - single 1- quad
+	
+	reg [31:0] tbCnt;
+	reg [31:0] delCnt;
+	reg stateCnt;
+	
+	reg Clk100;
+	reg Clk10;
+	
+	reg [1:0] currState;
+	reg [1:0] nextState;
+	
+	reg rst;
+	
+	wire txStart = (tbCnt == 100 | tbCnt == 3000);
+	wire txDoneS;
+	wire txDoneQ;
+	
+	
+	wire sckS;
+	wire sckQ;
+	wire ssS;
+	wire ssQ;
+	
+	wire ss;
+	wire sck;
+	
+	wire mosi0S;
+	wire mosi0Q;
+	wire mosi1Q;
+	wire mosi2Q;
+	wire mosi3Q;
+	
+	wire delDone = (delCnt == 500);
+//================================================================================
+//  ASSIGNMENTS
+	
+	assign sck = (currState==SINGLE) ? sckS:sckQ;
+	assign ss = (currState==SINGLE) ? ssS:ssQ;
+	assign mosi0 = (currState==SINGLE) ? mosi0S:mosi0Q;
+	assign mosi1 = (currState==SINGLE) ? 1'b1:mosi1Q;
+	assign mosi2 = (currState==SINGLE) ? 1'b1:mosi2Q;
+	assign mosi3 = (currState==SINGLE) ? 1'b1:mosi3Q;
+//================================================================================
+//clocks gen
+	always	#5 Clk100	=	~Clk100;	
+	always	#50 Clk10	=	~Clk10;	
+	
+	
+//================================================================================
+//  CODING
+
+initial begin
+	Clk100	=	1'b1;
+	Clk10	=	1'b1;
+	rst		=	1'b1;
+#100;
+	rst		=	1'b0;
+end	
+	
+always	@(negedge	Clk100)	begin
+	if	(!rst)		begin
+		tbCnt	<=	tbCnt+1;
+	end	else	begin
+		tbCnt	<=	0;
+	end
+end
+
+always	@(posedge	Clk100)	begin
+	if	(!rst)		begin
+		if (currState == DELAY) begin
+			delCnt	<=	delCnt+1;
+		end	else	begin
+			delCnt	<=	0;
+		end
+	end else	begin
+		delCnt	<=	0;
+	end
+end
+
+always	@(negedge	Clk10)	begin
+	if	(!rst)		begin
+		if (txDoneS|txDoneQ) begin
+			stateCnt	<=	stateCnt+1;
+		end	
+	end else begin
+		stateCnt <= 0;
+	end
+end
+
+always	@(posedge	Clk100)	begin
+	if	(!rst)		begin
+		case (stateCnt)
+			0:	begin
+					spiMode <= 1'b0;
+				end
+			1:	begin
+					spiMode <= 1'b1;
+				end
+			default:begin
+						spiMode <= 1'b0;
+					end
+		endcase
+	end else begin
+		spiMode <= 1'b0;
+	end
+end
+
+always	@(posedge	Clk100)	begin
+	if	(rst)	begin
+		currState	<=	IDLE;
+	end	else	begin
+		currState	<=	nextState;
+	end
+end
+
+
+always @(*) begin
+	nextState	=	IDLE;
+	case(currState)
+	IDLE	:	begin
+					if (txStart)	begin
+						case (spiMode)
+							1'b0:	begin
+											nextState = SINGLE;
+										end
+							1'b1:		begin
+											nextState = QUAD;
+										end
+						endcase
+					end	else begin
+						nextState = IDLE;
+					end
+				end
+				
+	SINGLE	:	begin
+					if (txDoneS)	begin
+						nextState = DELAY;
+					end	else begin
+						nextState = SINGLE;
+					end
+				end
+				
+	DELAY	:	begin
+					if (delDone)	begin
+						nextState = QUAD;
+					end	else begin
+						nextState = DELAY;
+					end
+				end
+				
+	QUAD		:	begin
+					if (txDoneQ) begin
+						nextState  = IDLE;
+					end	else begin
+						nextState  = QUAD;
+					end
+				end
+	endcase
+end
+
+ExtSpiMEmul SingleSpiSm
+(
+	.Rst_i		(rst),
+	.Clk_i		(Clk10),
+	
+	.Start_i	((currState==SINGLE)),
+	.TxDone_o	(txDoneS),
+	
+	.Sck_o		(sckS),
+	.Ss_o		(ssS),
+	.Mosi_o		(mosi0S)
+	
+);
+
+ExtQSpiMEmul QuadSpiSm
+(
+	.Rst_i		(rst),
+	.Clk_i		(Clk10),
+	
+	.Start_i	((currState==QUAD)),
+	.TxDone_o	(txDoneQ),
+	
+	.Sck_o		(sckQ),
+	.Ss_o		(ssQ),
+	.Mosi0_o	(mosi0Q),
+	.Mosi1_o	(mosi1Q),
+	.Mosi2_o	(mosi2Q),
+	.Mosi3_o	(mosi3Q)
+	
+);
+
+TopSbTmsg DUT
+(
+	.Clk_i	(Clk100),
+	.Rst_i	(rst),
+	
+	.Sck_i	(sck),
+	.Ss_i	(ss),
+	
+	.Mosi0_i	(mosi0),
+	.Mosi1_io	(mosi1),
+	.Mosi2_i	(mosi2),
+	.Mosi3_i	(mosi3),
+	
+	.Miso1_i		(),
+	.Miso2_i		(),
+	.MisoMax2870_i	(),
+	
+	.I2CSck_o	(),
+	.I2CSda_io	(),
+	
+	.Ss_o		(),
+	.Sck_o		(),
+	.Mosi_o		(),
+	
+	.Gpio_o		()
+);
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+