Добавлена логика генерации сигналов GPIO PllVtuneCtrl и DdsSyncFpga.

src/src/Top/TopSbTmsg.v

@@ -193,14 +193,12 @@ assign DdsX2Fpga_o 			= gpio1CtrlData[16];
 assign PllLoopCtrl_o 		= gpio1CtrlData[15];
 assign PllSync_o 			= gpio1CtrlData[14];
 assign PllSyncCtrl_o 		= gpio1CtrlData[13];
-assign PllVtuneCtrl_o 		= gpio1CtrlData[12];
 assign AmAlc1Fix_o 			= gpio1CtrlData[11];
 assign SwCap1_o 			= gpio1CtrlData[10];
 assign SwCap2_o 			= gpio1CtrlData[9];
 assign SwCap3_o 			= gpio1CtrlData[8];
 assign AmAlcSw_o 			= gpio1CtrlData[7];
 assign SwCap4_o 			= gpio1CtrlData[6];
-assign DdsSyncFpga_o 		= gpio1CtrlData[5];
 assign DdsResetFpga_o 		= gpio1CtrlData[4];
 assign DdsSyncCtrlFpga_o 	= gpio1CtrlData[3];
 assign CtrlAmSw3_o 			= gpio1CtrlData[2];
@@ -399,35 +397,41 @@ PacketAnalyzer1Mosi	PacketAnalyzer1Mosi
 );
 
 LmxWrapper #(
-	.IN_WIDTH		(24),
-	.WR_NUM			(1),
-	.OUT_WIDTH		(24),
-	.DATA_WIDTH		(24)
+	.IN_WIDTH			(24),
+	.WR_NUM				(1),
+	.OUT_WIDTH			(24),
+	.DATA_WIDTH			(24)
 ) LmxWrapper(
-	.WrClk_i		(gclk100),
-	.RdClk_i		(clk26dot25),
-	.Rst_i			(Rst_i),
-	.Data_i			(spiData),
-	.Val_i			(valLmxDataToFifo),
-	.Ss_o			(lmxCsSpiM),
-	.Sck_o			(lmxClkSpiM),
-	.Mosi_o			(lmxMosiSpiM)
+	.WrClk_i			(gclk100),
+	.RdClk_i			(clk26dot25),
+	.Rst_i				(Rst_i),
+	.Data_i				(spiData),
+	.Val_i				(valLmxDataToFifo),
+	.LmxWordNum_i		(),
+	.LmxWordNumVal_i	(),	
+	.PllVtuneCtrl_o		(PllVtuneCtrl_o),
+	.Ss_o				(lmxCsSpiM),
+	.Sck_o				(lmxClkSpiM),
+	.Mosi_o				(lmxMosiSpiM)
 );
 
 DDSWrapper #(
-	.IN_WIDTH		(24),
-	.WR_NUM			(3),
-	.OUT_WIDTH		(64),
-	.DATA_WIDTH		(64)
+	.IN_WIDTH			(24),
+	.WR_NUM				(3),
+	.OUT_WIDTH			(64),
+	.DATA_WIDTH			(64)
 ) DDSWrapper(
-	.WrClk_i		(gclk100),
-	.RdClk_i		(clk50),
-	.Rst_i			(Rst_i),
-	.Data_i			(spiData),
-	.Val_i			(valDdsDataToFifo),
-	.Ss_o			(ddsCsSpiM),
-	.Sck_o			(ddsClkSpiM),
-	.Mosi_o			(ddsMosiSpiM)
+	.WrClk_i			(gclk100),
+	.RdClk_i			(clk50),
+	.Rst_i				(Rst_i),
+	.DdsWordNum_i		(),
+	.DdsWordNumVal_i	()
+	.Data_i				(spiData),
+	.Val_i				(valDdsDataToFifo),
+	.DdsSyncCtrlFpga_o	(DdsSyncFpga_o),
+	.Ss_o				(ddsCsSpiM),
+	.Sck_o				(ddsClkSpiM),
+	.Mosi_o				(ddsMosiSpiM)
 );
 
 PotWrapper #(

src/src/WrapFifoChain/DDSWrapper.v

@@ -24,9 +24,13 @@ module DDSWrapper #(
     input WrClk_i,
     input RdClk_i,
     input Rst_i,
+	input [2:0] DdsWordNum_i,
+	input DdsWordNumVal_i,
     input [IN_WIDTH-1:0] Data_i,
     input Val_i,
 
+	output reg DdsSyncFpga_o,
+
     output Ss_o,
     output Sck_o,
     output Mosi_o
@@ -44,9 +48,53 @@ wire busySpiMDds;
 wire ddsFifoFull;
 wire ddsFifoEmpty;
 
+reg ssR;
+reg [2:0] ddsWordNumReg; 
+
 //==========================================================================//
 //									CODING									//
 //==========================================================================//
+always @(posedge WrClk_i) begin
+	if (Rst_i) begin 
+		ssR <= 1'b0;
+	end
+	else begin 
+		ssR <= Ss_o;
+	end
+end
+
+always @(posedge WrClk_i) begin
+	if (Rst_i) begin 
+		ddsWordNumReg <= 3'h0;
+	end
+	else begin 
+		if (DdsWordNumVal_i) begin 
+			ddsWordNumReg <= DdsWordNum_i;
+		end
+		else begin 
+			if (Ss_o && !ssR) begin 
+				ddsWordNumReg <= ddsWordNumReg-1;
+			end
+		end
+	end
+end
+
+always @(posedge WrClk_i) begin 
+	if (Rst_i) begin 
+		DdsSyncFpga_o <= 1'b0;
+	end
+	else begin 
+		if ((!Ss_o && ssR) && ddsWordNumReg != 0 ) begin 
+			DdsSyncFpga_o <= 1'b0;
+		end
+		else begin 
+			if (ddsWordNumReg == 3'h1 && (Ss_o && !ssR)) begin 
+				DdsSyncFpga_o <= 1'b1;
+			end
+		end
+	end
+end 
+
 FifoCtrl #(
 	.IN_WIDTH		(IN_WIDTH),
 	.WR_NUM			(WR_NUM),

src/src/WrapFifoChain/LmxWrapper.v

@@ -27,6 +27,11 @@ module LmxWrapper #(
     input [IN_WIDTH-1:0] Data_i,
     input Val_i,
 
+	input [3:0] LmxWordNum_i,
+	input LmxWordNumVal_i,
+
+	output reg PllVtuneCtrl_o,
+
     output Ss_o,
     output Sck_o,
     output Mosi_o
@@ -44,9 +49,50 @@ wire busySpiMLmx;
 wire lmxFifoFull;
 wire lmxFifoEmpty;
 
+reg ssR;
+reg [2:0] lmxWordNumReg; 
 //==========================================================================//
 //									CODING									//
 //==========================================================================//
+always @(posedge WrClk_i) begin
+	if (Rst_i) begin 
+		ssR <= 1'b0;
+	end
+	else begin 
+		ssR <= Ss_o;
+	end
+end
+
+always @(posedge WrClk_i) begin
+	if (Rst_i) begin 
+		lmxWordNumReg <= 3'h0;
+	end
+	else begin 
+		if (LmxWordNumVal_i) begin 
+			lmxWordNumReg <= LmxWordNum_i;
+		end
+		else begin 
+			if (Ss_o && !ssR) begin 
+				lmxWordNumReg <= LmxWordNum_i-1;
+			end
+		end
+	end
+end
+
+always @(posedge WrClk_i) begin 
+	if (Rst_i) begin 
+		PllVtuneCtrl_o <=1'b0;
+	end
+	else begin 
+		if (lmxWordNumReg != 0) begin 
+			PllVtuneCtrl_o <= 1'b0;
+		end
+		else begin 
+			PllVtuneCtrl_o <= 1'b1;
+		end
+	end
+end
+
 FifoCtrl #(
 	.IN_WIDTH		(IN_WIDTH),
 	.WR_NUM			(WR_NUM),