Увеличена длительность сигнала DdsSyncFpga.

src/constr/SbTmsg.sdc

@@ -1,8 +1,10 @@
 //Copyright (C)2014-2024 GOWIN Semiconductor Corporation.
 //All rights reserved.
 //File Title: Timing Constraints file
-//Tool Version: V1.9.9.02 
-//Created Time: 2024-05-02 15:55:01
+//Tool Version: V1.9.9.03 (64-bit) 
+//Created Time: 2024-05-24 17:15:18
+create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
+create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
 create_clock -name clk5 -period 200 -waveform {0 100} [get_nets {clk5}]
 //create_clock -name clk50 -period 20 -waveform {0 10} [get_nets {clk50}]
 //create_clock -name clk26dot25 -period 38.095 -waveform {0 19.047} [get_nets {clk26dot25}]
@@ -15,4 +17,5 @@ create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
 set_clock_groups -asynchronous -group [get_clocks {Clk_i}] -group [get_clocks {Sck_i}]
 set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Clk_i}] 
 set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Sck_i}] 
+set_false_path -from [get_clocks {Clk_i}] -to [get_clocks {Sck_i}] 
 report_timing -setup -from_clock [get_clocks {clk100}] -max_paths 1000 -max_common_paths 1

src/src/WrapFifoChain/DDSWrapper.v

@@ -59,6 +59,7 @@ reg ssReg;
 reg ddsDirectFlagR;
 reg [2:0] ddsWordNumReg;
 reg [2:0] ddsWordNumRegSync;
+reg [1:0] ddsSyncCnt;
 //==========================================================================//
 //									CODING									//
 //==========================================================================//
@@ -100,6 +101,20 @@ always @(posedge WrClk_i) begin
 	end
 end
 
+always @(posedge RdClk_i) begin 
+	if (Rst_i) begin 
+		ddsSyncCnt <= 2'b0;
+	end
+	else begin 
+		if (ddsSyncCnt == 0 && DdsSyncFpga_o) begin 
+			ddsSyncCnt <= 2'b1;
+		end
+		else begin 
+			ddsSyncCnt <= 2'b0;
+		end
+	end
+end
+
 always @(posedge RdClk_i) begin 
 	if (Rst_i) begin 
 		ddsWordNumRegSync <= 3'h0;
@@ -124,6 +139,9 @@ always @(posedge RdClk_i) begin
 			if (ddsWordNumRegSync == 3'h1 && (Ss_o && !ssReg)) begin 
 				DdsSyncFpga_o <= 1'b1;
 			end
+			else if (ddsSyncCnt == 0 && DdsSyncFpga_o) begin
+				DdsSyncFpga_o <= 1'b1;
+			end 
 			else begin 
 				DdsSyncFpga_o <= 1'b0;
 			end