Добавил модуль LoadOrder

src/src/LoadOrder/LoadOrder.v

@@ -0,0 +1,66 @@
+module LoadOrder (
+    input WrClk_i,
+    input RdClkLmx_i,
+    input RdClkDds_i,
+    input Rst_i,
+    input [23:0] Data_i,
+    input Val_i,
+    input [3:0] LmxWordNum_i,
+    input [2:0] DdsWordNum_i,
+
+	/* If Load order is 0 Dds is busy until Lmx is done */
+    output reg DdsBusy_o,
+    /* If Load order is 1 Lmx is busy until Dds is done */
+    output reg LmxBusy_o
+);
+//================================================================================
+//	                                REG/WIRE
+//================================================================================  
+reg loadOrder;
+//==========================================================================//
+//									ASSIGNMENTS								//
+//==========================================================================//
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+always @(posedge WrClk_i) begin
+	if (Rst_i) begin 
+		loadOrder <= 1'b0;
+	end
+	else begin 
+		if (Val_i) begin 
+			loadOrder <= Data_i[22];
+		end
+	end
+end
+
+always @(posedge WrClk_i) begin 
+    if (Rst_i) begin 
+        LmxBusy_o <= 1'b0;
+        DdsBusy_o <= 1'b0;
+    end
+    else begin 
+        if (loadOrder) begin 
+            if (LmxWordNum_i != 0 ) begin 
+                LmxBusy_o <= 1'b1;
+                DdsBusy_o <= 1'b0;
+            end
+            else begin 
+                LmxBusy_o <= 1'b0;
+                DdsBusy_o <= 1'b0;
+            end
+        end
+        else begin 
+            if (DdsWordNum_i != 0 ) begin 
+                LmxBusy_o <= 1'b0;
+                DdsBusy_o <= 1'b1;
+            end
+            else begin 
+                LmxBusy_o <= 1'b0;
+                DdsBusy_o <= 1'b0;
+            end
+        end
+    end
+end
+
+endmodule

src/src/PacketAnalyzer4Mosi/PacketAnalyzer4Mosi.v

@@ -46,6 +46,7 @@ module PacketAnalyzer4Mosi (
 	output reg ValShRegDataToFifo_o,
 	output reg ValMaxDataToFifo_o,
 	output reg ValGpioDataToFifo_o,
+	output reg ValLoadOrder_o,
 
 	output reg Busy_o
 );
@@ -60,6 +61,7 @@ reg [22:0] dataSpiReg;
 //==========================================
 wire lmxOr;
 wire ddsOr;
+wire loadOrderOr;
 wire potOr;
 wire dacOr;
 wire attOr;
@@ -67,19 +69,20 @@ wire shRegOr;
 wire maxOr;
 wire gpioOr;
 
-wire [7:0] selector;
+wire [8:0] selector;
 
 //==========================================
 // Parameters
 //==========================================
-localparam [22:0] DECREMENT_DDS 	= 23'h80000;		//23'b000 1000 0000 0000 0000 0000
-localparam [22:0] DECREMENT_GPIO 	= 23'h10000;		//23'b000 0001 0000 0000 0000 0000
-localparam [22:0] DECREMENT_LMX 	= 23'h1000;			//23'b000 0000 0001 0000 0000 0000
-localparam [22:0] DECREMENT_MAX 	= 23'h200;			//23'b000 0000 0000 0010 0000 0000
-localparam [22:0] DECREMENT_SH_REG 	= 23'h40;			//23'b000 0000 0000 0000 0100 0000
-localparam [22:0] DECREMENT_POT 	= 23'h8;			//23'b000 0000 0000 0000 0000 1000
-localparam [22:0] DECREMENT_DAC 	= 23'h4;			//23'b000 0000 0000 0000 0000 0100
-localparam [22:0] DECREMENT_ATT 	= 23'h2;			//23'b000 0000 0000 0000 0000 0010
+localparam [22:0] DECREMENT_LOAD_ORDER 	= 23'h400000;		//23'b100 0000 0000 0000 0000 0000
+localparam [22:0] DECREMENT_DDS 		= 23'h80000;		//23'b000 1000 0000 0000 0000 0000
+localparam [22:0] DECREMENT_GPIO 		= 23'h10000;		//23'b000 0001 0000 0000 0000 0000
+localparam [22:0] DECREMENT_LMX 		= 23'h1000;			//23'b000 0000 0001 0000 0000 0000
+localparam [22:0] DECREMENT_MAX 		= 23'h200;			//23'b000 0000 0000 0010 0000 0000
+localparam [22:0] DECREMENT_SH_REG 		= 23'h40;			//23'b000 0000 0000 0000 0100 0000
+localparam [22:0] DECREMENT_POT 		= 23'h8;			//23'b000 0000 0000 0000 0000 1000
+localparam [22:0] DECREMENT_DAC 		= 23'h4;			//23'b000 0000 0000 0000 0000 0100
+localparam [22:0] DECREMENT_ATT 		= 23'h2;			//23'b000 0000 0000 0000 0000 0010
 
 //==========================================
 // Assignments
@@ -92,8 +95,9 @@ assign attOr 	= 	 dataSpiReg[1];
 assign shRegOr 	= 	|dataSpiReg[7:6];
 assign maxOr 	= 	|dataSpiReg[10:9];
 assign gpioOr 	= 	|dataSpiReg[17:16];
+assign loadOrderOr = dataSpiReg[22];
 
-assign selector = {ddsOr, gpioOr, lmxOr, maxOr, shRegOr, potOr, dacOr, attOr};
+assign selector = {loadOrderOr,ddsOr, gpioOr, lmxOr, maxOr, shRegOr, potOr, dacOr, attOr};
 
 //==========================================================================//
 //									CODING									//
@@ -124,6 +128,7 @@ always @(posedge Clk_i) begin
 		LmxWordNum_o <= 0;
 		DdsWordNum_o <= 0;
 		ValWordNum_o <= 1'b0;
+		ValLoadOrder_o <= 1'b0;
 	end
 	else if (ValDataFromSpi_i) begin
 		if ((dataSpiReg == 0) && (DataFromSpi_i[23] == 1'b1)) begin
@@ -134,35 +139,39 @@ always @(posedge Clk_i) begin
 		end
 		else begin
 			casez(selector)
-			8'b1???????: begin //DDS
+			9'b1????????: begin //LoadOrder
+				dataSpiReg <= dataSpiReg - DECREMENT_LOAD_ORDER;
+				ValLoadOrder_o <= 1'b1;
+			end
+			9'b01???????: begin //DDS
 				dataSpiReg <= dataSpiReg - DECREMENT_DDS;
 				ValDdsDataToFifo_o <= 1'b1;
 			end
-			8'b01??????: begin //GPIO
+			9'b001??????: begin //GPIO
 				dataSpiReg <= dataSpiReg - DECREMENT_GPIO;
 				ValGpioDataToFifo_o <= 1'b1;
 			end
-			8'b001?????: begin //LMX
+			9'b0001?????: begin //LMX
 				dataSpiReg <= dataSpiReg - DECREMENT_LMX;
 				ValLmxDataToFifo_o <= 1'b1;
 			end
-			8'b0001????: begin //MAX
+			9'b00001????: begin //MAX
 				dataSpiReg <= dataSpiReg - DECREMENT_MAX;
 				ValMaxDataToFifo_o <= 1'b1;
 			end
-			8'b00001???: begin //ShReg
+			9'b000001???: begin //ShReg
 				dataSpiReg <= dataSpiReg - DECREMENT_SH_REG;
 				ValShRegDataToFifo_o <= 1'b1;
 			end
-			8'b000001??: begin //Pot
+			9'b0000001??: begin //Pot
 				dataSpiReg <= dataSpiReg - DECREMENT_POT;
 				ValPotDataToFifo_o <= 1'b1;
 			end
-			8'b0000001?: begin //DAC
+			9'b00000001?: begin //DAC
 				dataSpiReg <= dataSpiReg - DECREMENT_DAC;
 				ValDacDataToFifo_o <= 1'b1;
 			end
-			8'b00000001: begin //ATT
+			9'b000000001: begin //ATT
 				dataSpiReg <= dataSpiReg - DECREMENT_ATT;
 				ValAttDataToFifo_o <= 1'b1;
 			end
@@ -175,6 +184,7 @@ always @(posedge Clk_i) begin
 				ValShRegDataToFifo_o <= 1'b0;
 				ValMaxDataToFifo_o <= 1'b0;
 				ValGpioDataToFifo_o <= 1'b0;
+				ValLoadOrder_o <= 1'b0;
 			end
 		endcase
 //=========================DELETE AFTER HARDWARE TEST===========================
@@ -232,6 +242,7 @@ always @(posedge Clk_i) begin
 		ValShRegDataToFifo_o 	<= 1'b0;
 		ValMaxDataToFifo_o 		<= 1'b0;
 		ValGpioDataToFifo_o 	<= 1'b0;
+		ValLoadOrder_o 		<= 1'b0;
 		ValWordNum_o <= 1'b0;
 	end
 end

src/src/Top/TopSbTmsg.v

@@ -136,7 +136,8 @@ localparam [11:0] FIRMWARE_VER	= 12'h1;
 	wire valAttDataToFifo;		
 	wire valShRegDataToFifo;	
 	wire valMaxDataToFifo;		
-	wire valGpioDataToFifo;	
+	wire valGpioDataToFifo;
+	wire valLoadOrder;	
 	
 	wire flagDirectLmx;	
 	wire flagDirectDds;	
@@ -187,6 +188,7 @@ localparam [11:0] FIRMWARE_VER	= 12'h1;
 	wire [3:0] lmxWordNum;
 	wire [2:0] ddsWordNum;
 	wire [2:0] ddsWordNumReg;
+	wire [3:0] lmxWordNumReg;
 	wire valWordNum;
 
 	wire testTrig;
@@ -410,6 +412,7 @@ PacketAnalyzer4Mosi PacketAnalyzer4Mosi
 	.ValShRegDataToFifo_o	(valShRegDataToFifo),
 	.ValMaxDataToFifo_o		(valMaxDataToFifo),
 	.ValGpioDataToFifo_o	(valGpioDataToFifo),
+	.ValLoadOrder_o			(valLoadOrder),
 
 	.Busy_o					(busyMosi4)
 );
@@ -439,6 +442,21 @@ PacketAnalyzer1Mosi	PacketAnalyzer1Mosi
 	.Busy_o					(busyMosi1)
 );
 
+LoadOrder LoadOrder
+(
+	.WrClk_i		(clk60),
+	.RdClkLmx_i		(clk60),
+	.RdClkDds_i		(clk50),
+	.Rst_i			(Rst_i),
+	.Data_i			(spiData),
+	.Val_i			(valLoadOrder),
+	.LmxWordNum_i	(lmxWordNumReg),
+	.DdsWordNum_i	(ddsWordNumReg),
+
+	.DdsBusy_o		(ddsBusy),
+	.LmxBusy_o		(lmxBusy)
+);
+
 LmxWrapper #(
 	.IN_WIDTH			(24),
 	.WR_NUM				(1),
@@ -456,6 +474,7 @@ LmxWrapper #(
 	.DdsCs_i			(ddsCsSpiM),
 	.LmxDirectFlag_i	(flagDirectLmx),	
 	.PllVtuneCtrl_o		(PllVtuneCtrl_o),
+	.LmxWordNumReg_o	(lmxWordNumReg),
 	.Ss_o				(lmxCsSpiM),
 	.Sck_o				(lmxClkSpiM),
 	.Mosi_o				(lmxMosiSpiM)

src/src/WrapFifoChain/LmxWrapper.v

@@ -34,6 +34,7 @@ module LmxWrapper #(
 	input LmxWordNumVal_i,
 
 	output reg PllVtuneCtrl_o,
+	output [3:0] LmxWordNumReg_o,
 
     output Ss_o,
     output Sck_o,
@@ -66,6 +67,7 @@ reg [3:0] lmxWordNumRegR;
 //									ASSIGNMENTS								//
 //==========================================================================//
 assign lmxWordNumValSync = plsToggleSyncB^plsToggleSyncA;
+assign LmxWordNumReg_o = lmxWordNumReg;
 //==========================================================================//
 //									CODING									//
 //==========================================================================//