Синхронизация в InterfaceArbiter.

src/src/InterfaceArbiter/InterfaceArbiter.v

@@ -81,18 +81,72 @@ module InterfaceArbiter
 	reg [1:0] currState;
 	
 	reg rxDone;
+
+	wire plsToggleSyncSignal;
+	reg plsToggle;
+	reg plsToggleSyncA;
+	reg plsToggleSyncB;
+	reg plsToggleSyncC;
+	reg plsToggleSyncSignalR;
+
 //================================================================================
 //  ASSIGNMENTS
 	assign ssPos = ssRegR & !ssRegRR;
 
 	
-	assign DataVal_o = dataValReg;
+	assign DataVal_o = plsToggleSyncSignal;
 	assign Data_o = (spiMode)? dataRegQSpi:dataRegSSpi;
 
+	assign plsToggleSyncSignal = plsToggleSyncB^plsToggleSyncA;
+
 	//assign ssCntRstThresh = (spiMode) ? QSPIWORDWIDTH-1:SSPIWORDWIDTH-1;
 	
 //================================================================================
 //  CODING
+
+	always @(posedge Clk_i) begin 
+    	if (Rst_i) begin 
+    	    plsToggleSyncA <= 1'b0;
+    	    plsToggleSyncB <= 1'b0;
+    	end
+    	else begin 
+    	    plsToggleSyncA <= plsToggle;
+    	    plsToggleSyncB <= plsToggleSyncA;
+    	end
+	end
+
+	always @(posedge Clk_i) begin 
+	    if (Rst_i) begin 
+	        plsToggleSyncC <= 1'b0;
+	    end
+	    else begin
+	        plsToggleSyncC <= plsToggleSyncB;
+	    end
+	end
+	
+	always @(posedge Ss_i or posedge Rst_i) begin 
+		if (Rst_i) begin 
+			plsToggle <= 1'b0;
+		end
+		else begin 
+			if (Ss_i) begin 
+				plsToggle <= ~plsToggle;
+			end
+			else begin 
+				plsToggle <= plsToggle;
+			end
+		end
+	end
+
+	always @(posedge Clk_i) begin 
+		if (Rst_i) begin 
+			plsToggleSyncSignalR <= 1'b0;
+		end
+		else begin 
+			plsToggleSyncSignalR <= plsToggleSyncSignal;
+		end
+	end
+
 	always @(posedge Sck_i or posedge Rst_i) begin 
 		if (Rst_i) begin 
 			captRegSspi <= 0;
@@ -141,7 +195,7 @@ module InterfaceArbiter
 	always @(posedge Clk_i) begin
 		if (!Rst_i) begin
 			if (currState == DATARX) begin
-				if (ssPos) begin
+				if (plsToggleSyncSignal) begin
 					if (wordsCnt == wordsNum-1) begin
 						wordsCnt <= 0;
 						rxDone <= 1'b1;
@@ -208,7 +262,7 @@ module InterfaceArbiter
 	
 	always @(posedge Clk_i) begin
 		if (!Rst_i) begin
-			if (ssPos) begin
+			if (plsToggleSyncSignal) begin
 				dataRegSSpi <= captRegSspi;
 				dataRegQSpi <= {captReg0,captReg1,captReg2,captReg3};
 				dataValReg <= 1'b1;
@@ -234,7 +288,7 @@ module InterfaceArbiter
 		nextState = IDLE;
 		case(currState)
 		IDLE		:begin
-						if (ssPosR)	begin
+						if (plsToggleSyncSignalR)	begin
 							nextState = DATARX;
 						end	else begin
 							nextState = IDLE;

src/src/Top/TopSbTmsg.v

@@ -352,7 +352,7 @@ InterfaceArbiter
 SpiSlaveArbiter
 (
 	.Rst_i		(Rst_i),
-	.Clk_i		(gclk100),
+	.Clk_i		(clk60),
 	
 	.Sck_i		(Sck_i),
 	.Ss_i		(Ss_i),
@@ -367,14 +367,14 @@ SpiSlaveArbiter
 	.Data_o		(spiData)
 );
 
-Sync1bit SyncPulse(
-	.ClkFast_i	(gclk100),
-	.ClkSlow_i	(clk60),
-	.Signal_i	(spiDataVal),
-	.Ss_i		(Ss_i),
-	.Rst_i		(initRst),
-	.Signal_o	(spiDataValSync)	
-);
+// Sync1bit SyncPulse(
+// 	.ClkFast_i	(gclk100),
+// 	.ClkSlow_i	(clk60),
+// 	.Signal_i	(spiDataVal),
+// 	.Ss_i		(Ss_i),
+// 	.Rst_i		(initRst),
+// 	.Signal_o	(spiDataValSync)	
+// );
 
 PacketAnalyzer4Mosi PacketAnalyzer4Mosi
 (
@@ -382,7 +382,7 @@ PacketAnalyzer4Mosi PacketAnalyzer4Mosi
 	.Rst_i					(Rst_i),
 
 	.DataFromSpi_i			(spiData),
-	.ValDataFromSpi_i		(spiDataValSync),
+	.ValDataFromSpi_i		(spiDataVal),
 
 	.BusyMosi1_i			(busyMosi1),
 
@@ -408,7 +408,7 @@ PacketAnalyzer1Mosi	PacketAnalyzer1Mosi
 	.Rst_i					(Rst_i),
 	
 	.DataFromSpi_i			(spiData),
-	.ValDataFromSpi_i		(spiDataValSync),
+	.ValDataFromSpi_i		(spiDataVal),
 	
 	.BusyMosi4_i			(busyMosi4),
 	
@@ -560,7 +560,7 @@ Gpio1Ctrl Gpio1Ctrl
 (
 	.Clk_i					(clk60),
 	.ValGpioDataToFifo_i	(valGpioDataToFifo),
-	.ValDataFromSpi_i		(spiDataValSync),
+	.ValDataFromSpi_i		(spiDataVal),
 	.FlagDirectGpio1_i		(flagDirectGpio1),
 	.Data_i					(spiData),
 	.GpioReg_o				(gpio1CtrlData)

src/src/Top/TopSbTmsgTb.sv

@@ -193,7 +193,7 @@ initial begin
   end
 //***********************************************
 
-always_ff @(posedge Clk10) begin
+always_ff @(posedge Clk50) begin
     if (Rst_i) begin 
         trCnt <= 0;
     end
@@ -258,7 +258,7 @@ always_comb begin
     end
 end
 
-always_ff @(posedge Clk10) begin 
+always_ff @(posedge Clk50) begin 
     if (Rst_i) begin 
         randData<=0;
         randData32 <= 0;
@@ -336,7 +336,7 @@ always_comb begin
     GSR GSR(.GSRI(1'b1));
 
    ExtSpiMEmul ExtSpiMEmul_inst (
-        .Clk_i(Clk10), 
+        .Clk_i(Clk50), 
         .Rst_i(Rst_i || modeSel), 
         .Start_i(Start_i), 
         .ClockPhase_i(CPHA_i),
@@ -347,7 +347,7 @@ always_comb begin
         .Lag_i(LAG_i),
         .Lead_i(LEAD_i),
         .EndianSel_i(EndianSel_i),
-        .Stop_i(Stop_i),
+        .Stop_i(6'h2),
         .PulsePol_i(PulsePol_i),
         .Mosi0_o(mosi0R),
         .Sck_o(SckR),
@@ -356,7 +356,7 @@ always_comb begin
     );
 
     ExtQspiMEmul ExtQspiMEmul_inst (
-        .Clk_i(Clk10),
+        .Clk_i(Clk50),
         .Rst_i(Rst_i || !modeSel),
         .Start_i(Start_i),
         .ClockPhase_i(CPHA_i),
@@ -367,7 +367,7 @@ always_comb begin
         .Lag_i(LAG_i),
         .Lead_i(LEAD_i),
         .EndianSel_i(EndianSel_i),
-        .Stop_i(Stop_i),
+        .Stop_i(6'h2),
         .PulsePol_i(PulsePol_i),
         .Mosi0_o(mosi0Q),
         .Mosi1_o(Mosi1_o),