Merge branch 'Mikhail/feature_PacketAnalyzer4Mosi' of zaytsev.mikhail/SB_TMSG44V1_FPGA into dev

src/src/PacketAnalyzer4Mosi/PacketAnalyzer4Mosi.v

@@ -0,0 +1,228 @@
+////////////////////////////////////////////////////////////////////////////////////////////
+// Company:			TAIR
+// Engineer:		Zaytsev Mikhail
+// 
+// Create Date:		18/04/2024 
+// Design Name: 
+// Module Name:		PacketAnalyzer4Mosi 
+// Project Name:	SB_TMSG44V1_FPGA
+// Target Devices:	Board: SB_TMSG44v1. FPGA: GW1N-LV9PG256C6/I5
+// Tool versions:
+// Description:		The module analyzes the input data bus DataFromSpi_i[23:0] by the 
+//					validity signal ValDataFromSpi_i. When a configuration packet is 
+//					received, it is captured into the internal register. Further, each 
+//					incoming data packet decrements the internal configuration register 
+//					until the internal configuration register is zero, which means that 
+//					the module is ready to receive the next configuration packet. Each 
+//					decrement sets the data validity bit for the specific end device. 
+//					The module also has an output signal Busy_o, which signals that 
+//					the module is in the state of processing the data received in 
+//					4MOSI mode for writing to the FIFO.
+//
+// Dependencies:	
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+////////////////////////////////////////////////////////////////////////////////////////////
+module PacketAnalyzer4Mosi (
+	input Clk_i,
+	input Rst_i,
+
+	input [23:0] DataFromSpi_i,
+	input ValDataFromSpi_i,
+
+	input BusyMosi1_i,
+
+	output reg ValLmxDataToFifo_o,
+	output reg ValDdsDataToFifo_o,
+	output reg ValPotDataToFifo_o,
+	output reg ValDacDataToFifo_o,
+	output reg ValAttDataToFifo_o,
+	output reg ValShRegDataToFifo_o,
+	output reg ValMaxDataToFifo_o,
+	output reg ValGpioDataToFifo_o,
+
+	output reg Busy_o
+);
+
+//==========================================
+// Registers
+//==========================================
+reg [22:0] DataSpiReg;
+
+//==========================================
+// Wires
+//==========================================
+wire lmxOr;
+wire ddsOr;
+wire potOr;
+wire dacOr;
+wire attOr;
+wire shRegOr;
+wire maxOr;
+wire gpioOr;
+
+wire [7:0] selector;
+
+//==========================================
+// Parameters
+//==========================================
+localparam [22:0] DECREMENT_LMX 	= 23'h80000;	//23'b000 1000 0000 0000 0000 0000
+localparam [22:0] DECREMENT_DDS 	= 23'h20000;	//23'b000 0010 0000 0000 0000 0000
+localparam [22:0] DECREMENT_POT 	= 23'h10000;	//23'b000 0001 0000 0000 0000 0000
+localparam [22:0] DECREMENT_DAC 	= 23'h8000;		//23'b000 0000 1000 0000 0000 0000
+localparam [22:0] DECREMENT_ATT 	= 23'h4000;		//23'b000 0000 0100 0000 0000 0000
+localparam [22:0] DECREMENT_SH_REG 	= 23'h1000;		//23'b000 0000 0001 0000 0000 0000
+localparam [22:0] DECREMENT_MAX 	= 23'h200;		//23'b000 0000 0000 0010 0000 0000
+localparam [22:0] DECREMENT_GPIO 	= 23'h80;		//23'b000 0000 0000 0000 1000 0000
+
+//==========================================
+// Assignments
+//==========================================
+assign lmxOr 	= 	|DataSpiReg[22:19];
+assign ddsOr 	= 	|DataSpiReg[18:17];
+assign potOr 	= 	 DataSpiReg[16];
+assign dacOr 	= 	 DataSpiReg[15];
+assign attOr 	= 	 DataSpiReg[14];
+assign shRegOr 	= 	|DataSpiReg[13:12];
+assign maxOr 	= 	|DataSpiReg[11:9];
+assign gpioOr 	= 	|DataSpiReg[8:7];
+
+assign selector = {lmxOr, ddsOr, potOr, dacOr, attOr, shRegOr, maxOr, gpioOr};
+
+//==========================================================================//
+//									CODING									//
+//==========================================================================//
+always @(posedge Clk_i) begin
+	if (Rst_i) begin
+		Busy_o <= 1'b0;
+	end
+	else if (DataSpiReg != 0) begin
+		Busy_o <= 1'b1;
+	end
+	else begin
+		Busy_o <= 1'b0;
+	end
+end
+
+always @(posedge Clk_i) begin
+	if (Rst_i || BusyMosi1_i) begin
+		DataSpiReg <= 23'b0;
+		ValLmxDataToFifo_o <= 1'b0;
+		ValDdsDataToFifo_o <= 1'b0;
+		ValPotDataToFifo_o <= 1'b0;
+		ValDacDataToFifo_o <= 1'b0;
+		ValAttDataToFifo_o <= 1'b0;
+		ValShRegDataToFifo_o <= 1'b0;
+		ValMaxDataToFifo_o <= 1'b0;
+		ValGpioDataToFifo_o <= 1'b0;
+	end
+	else if (ValDataFromSpi_i) begin
+		if ((DataSpiReg == 0) && (DataFromSpi_i[23] == 1'b1)) begin
+			DataSpiReg <= DataFromSpi_i[22:0];
+		end
+		else begin
+			casez(selector)
+			8'b1???????: begin //LMX
+				DataSpiReg <= DataSpiReg - DECREMENT_LMX;
+				ValLmxDataToFifo_o <= 1'b1;
+			end
+			8'b01??????: begin //DDS
+				DataSpiReg <= DataSpiReg - DECREMENT_DDS;
+				ValDdsDataToFifo_o <= 1'b1;
+			end
+			8'b001?????: begin //POT
+				DataSpiReg <= DataSpiReg - DECREMENT_POT;
+				ValPotDataToFifo_o <= 1'b1;
+			end
+			8'b0001????: begin //DAC
+				DataSpiReg <= DataSpiReg - DECREMENT_DAC;
+				ValDacDataToFifo_o <= 1'b1;
+			end
+			8'b00001???: begin //ATT
+				DataSpiReg <= DataSpiReg - DECREMENT_ATT;
+				ValAttDataToFifo_o <= 1'b1;
+			end
+			8'b000001??: begin //ShReg
+				DataSpiReg <= DataSpiReg - DECREMENT_SH_REG;
+				ValShRegDataToFifo_o <= 1'b1;
+			end
+			8'b0000001?: begin //MAX2870
+				DataSpiReg <= DataSpiReg - DECREMENT_MAX;
+				ValMaxDataToFifo_o <= 1'b1;
+			end
+			8'b00000001: begin //GPIO
+				DataSpiReg <= DataSpiReg - DECREMENT_GPIO;
+				ValGpioDataToFifo_o <= 1'b1;
+			end
+			default: begin
+				ValLmxDataToFifo_o <= 1'b0;
+				ValDdsDataToFifo_o <= 1'b0;
+				ValPotDataToFifo_o <= 1'b0;
+				ValDacDataToFifo_o <= 1'b0;
+				ValAttDataToFifo_o <= 1'b0;
+				ValShRegDataToFifo_o <= 1'b0;
+				ValMaxDataToFifo_o <= 1'b0;
+				ValGpioDataToFifo_o <= 1'b0;
+			end
+		endcase
+//=========================DELETE AFTER HARDWARE TEST===========================
+			/*if (lmxOr) begin //LMX
+				DataSpiReg <= DataSpiReg - DECREMENT_LMX;
+				ValLmxDataToFifo_o 		<= 1'b1;
+			end
+			else if (ddsOr) begin //DDS
+				DataSpiReg <= DataSpiReg - DECREMENT_DDS;
+				ValDdsDataToFifo_o 		<= 1'b1;
+			end
+			else if (potOr) begin //POT
+				DataSpiReg <= DataSpiReg - DECREMENT_POT;
+				ValPotDataToFifo_o 		<= 1'b1;
+			end
+			else if (dacOr) begin //DAC
+				DataSpiReg <= DataSpiReg - DECREMENT_DAC;
+				ValDacDataToFifo_o 		<= 1'b1;
+			end
+			else if (attOr) begin
+				DataSpiReg <= DataSpiReg - DECREMENT_ATT;
+				ValAttDataToFifo_o 		<= 1'b1;
+			end
+			else if (shRegOr) begin
+				DataSpiReg <= DataSpiReg - DECREMENT_SH_REG;
+				ValShRegDataToFifo_o 	<= 1'b1;
+			end
+			else if (maxOr) begin
+				DataSpiReg <= DataSpiReg - DECREMENT_MAX;
+				ValMaxDataToFifo_o 		<= 1'b1;
+			end
+			else if (gpioOr) begin
+				DataSpiReg <= DataSpiReg - DECREMENT_GPIO;
+				ValGpioDataToFifo_o 	<= 1'b1;
+			end
+			else begin
+				ValLmxDataToFifo_o 		<= 1'b0;
+				ValDdsDataToFifo_o 		<= 1'b0;
+				ValPotDataToFifo_o 		<= 1'b0;
+				ValDacDataToFifo_o 		<= 1'b0;
+				ValAttDataToFifo_o 		<= 1'b0;
+				ValShRegDataToFifo_o 	<= 1'b0;
+				ValMaxDataToFifo_o 		<= 1'b0;
+				ValGpioDataToFifo_o 	<= 1'b0;
+			end*/
+//=========================DELETE AFTER HARDWARE TEST===========================
+		end
+	end
+	else begin
+		ValLmxDataToFifo_o 		<= 1'b0;
+		ValDdsDataToFifo_o 		<= 1'b0;
+		ValPotDataToFifo_o 		<= 1'b0;
+		ValDacDataToFifo_o 		<= 1'b0;
+		ValAttDataToFifo_o 		<= 1'b0;
+		ValShRegDataToFifo_o 	<= 1'b0;
+		ValMaxDataToFifo_o 		<= 1'b0;
+		ValGpioDataToFifo_o 	<= 1'b0;
+	end
+end
+
+endmodule

src/src/PacketAnalyzer4Mosi/PacketAnalyzer4MosiTb.v

@@ -0,0 +1,169 @@
+`timescale 1ns / 1ns
+
+module PacketAnalyzer4MosiTb (
+);
+
+//===============USER DEFINE===================
+localparam [3:0] CNT_LMX_DATA = 1;
+localparam [1:0] CNT_DDS_DATA = 1;
+localparam [0:0] CNT_POT_DATA = 1;
+localparam [0:0] CNT_DAC_DATA = 1;
+localparam [0:0] CNT_ATT_DATA = 1;
+localparam [1:0] CNT_SH_REG_DATA = 1;
+localparam [2:0] CNT_MAX_DATA = 3;
+localparam [1:0] CNT_GPIO_DATA = 1;
+//===============USER DEFINE_END===============
+
+localparam MODE_4MOSI = 1'b1;
+localparam MODE_1MOSI = 1'b0;
+
+//===============USER DEFINE===================
+localparam MODE_SELECT = MODE_4MOSI;
+//===============USER DEFINE_END===============
+
+localparam CFG_REG = 	{MODE_SELECT, CNT_LMX_DATA, CNT_DDS_DATA, 
+						CNT_POT_DATA, CNT_DAC_DATA, CNT_ATT_DATA,
+						CNT_SH_REG_DATA, CNT_MAX_DATA, CNT_GPIO_DATA, 7'b0};
+
+localparam CNT_DATA_WORDS = CNT_LMX_DATA + CNT_DDS_DATA + CNT_POT_DATA 
+							+ CNT_DAC_DATA + CNT_ATT_DATA + CNT_SH_REG_DATA 
+							+ CNT_MAX_DATA + CNT_GPIO_DATA;
+
+reg clkMain_tb;
+reg rstMain_tb;
+reg busyMosi1_tb;
+
+reg [23:0] DataFromSpi_tb;
+reg ValDataFromSpi_tb;
+
+always #10 clkMain_tb = ~clkMain_tb;
+
+initial begin
+	clkMain_tb = 0;
+	rstMain_tb = 1;
+	busyMosi1_tb = 0;
+	#100
+	rstMain_tb = 0;
+end
+
+reg	[7:0]	state; 
+reg	[63:0]	cnt;
+reg	[63:0]	countState;
+
+always @(posedge clkMain_tb) begin
+	if (rstMain_tb) begin
+		cnt <= 0;
+		state <= 0;
+		ValDataFromSpi_tb <= 0;	
+		DataFromSpi_tb <= 0;
+		countState <= 0;
+	end
+	else begin
+		case(state)
+			0: begin
+				DataFromSpi_tb <= CFG_REG;
+
+				if (cnt == 6) begin
+					cnt <= 0;
+					ValDataFromSpi_tb <= 1;
+					state <= state + 1;
+				end
+				else begin
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			1: begin
+				ValDataFromSpi_tb <= 0;
+				if (cnt == 1) begin
+					cnt <= 0;
+					state <= state + 1;
+				end
+				else begin
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			2: begin
+				DataFromSpi_tb <= 24'hA; //DATA0
+
+				if (cnt == 6) begin
+					cnt <= 0;
+					ValDataFromSpi_tb <= 1;
+					state <= state + 1;
+					countState <= countState + 1;
+				end
+				else begin
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			3: begin
+				ValDataFromSpi_tb <= 0;
+				if (countState == CNT_DATA_WORDS) begin
+					state <= 5;
+				end
+				else if (cnt == 1) begin
+					cnt <= 0;
+					state <= state + 1;
+				end
+				else begin
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			4: begin
+				DataFromSpi_tb <= 24'hF; //DATA1
+
+				if (cnt == 6) begin
+					cnt <= 0;
+					ValDataFromSpi_tb <= 1;
+					state <= state + 1;
+					countState <= countState + 1;
+				end
+				else begin
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+			5: begin
+				ValDataFromSpi_tb <= 0;
+				if (countState == CNT_DATA_WORDS) begin
+					state <= state;
+				end
+				else if (cnt == 1) begin
+					cnt <= 0;
+					state <= 2;
+				end
+				else begin
+					cnt <= cnt + 1;
+					state <= state;
+				end
+			end
+		endcase
+	end
+end
+
+PacketAnalyzer4Mosi DUT (
+	.Clk_i					(clkMain_tb),	
+	.Rst_i					(rstMain_tb),	
+	
+	.DataFromSpi_i 			(DataFromSpi_tb),
+	.ValDataFromSpi_i 		(ValDataFromSpi_tb),
+	
+	.BusyMosi1_i			(busyMosi1_tb),
+
+	.ValLmxDataToFifo_o		(),
+	.ValDdsDataToFifo_o		(),
+	.ValPotDataToFifo_o		(),
+	.ValDacDataToFifo_o		(),
+	.ValAttDataToFifo_o		(),
+	.ValShRegDataToFifo_o	(),
+	.ValMaxDataToFifo_o		(),
+	.ValGpioDataToFifo_o	(),
+
+	.Busy_o					()
+);
+
+
+endmodule

src/src/PacketAnalyzer4Mosi/PacketAnalyzer4MosiWave.do

@@ -0,0 +1,44 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/Clk_i
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/Rst_i
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/DataFromSpi_i
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/ValDataFromSpi_i
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/BusyMosi1_i
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/ValLmxDataToFifo_o
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/ValDdsDataToFifo_o
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/ValPotDataToFifo_o
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/ValDacDataToFifo_o
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/ValAttDataToFifo_o
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/ValShRegDataToFifo_o
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/ValMaxDataToFifo_o
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/ValGpioDataToFifo_o
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/Busy_o
+add wave -noupdate -radix binary /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/DataSpiReg
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/lmxOr
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/ddsOr
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/potOr
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/dacOr
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/attOr
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/shRegOr
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/maxOr
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/gpioOr
+add wave -noupdate /PacketAnalyzer4MosiTb/PacketAnalyzer4Mosi_inst/selector
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {270 ns} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 174
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ns} {3962 ns}