Добавил клок 70 МГц

src/constr/SbTmsg.sdc

@@ -1,15 +1,15 @@
-//Copyright (C)2014-2024 GOWIN Semiconductor Corporation.
+//Copyright (C)2014-2025 GOWIN Semiconductor Corporation.
 //All rights reserved.
 //File Title: Timing Constraints file
-//Tool Version: V1.9.9.03 (64-bit) 
-//Created Time: 2024-05-31 16:04:42
+//Tool Version: V1.9.11 (64-bit) 
+//Created Time: 2025-04-08 10:12:55
 create_clock -name clk5 -period 200 -waveform {0 100} [get_nets {clk5}]
-create_clock -name clk60 -period 16.667 -waveform {0 8.334} [get_nets {clk60}]
 create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
 create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
-//create_clock -name clk100 -period 10 -waveform {0 5} [get_nets {gclk100}]
+create_generated_clock -name clk210 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 4 -multiply_by 35 -duty_cycle 50 [get_nets {ClkGen/clk210Mhz}]
+create_generated_clock -name clk70 -source [get_nets {ClkGen/clk210Mhz}] -master_clock clk210 -divide_by 3 -multiply_by 1 -duty_cycle 50 [get_nets {ClkGen/GowinPllSecond210M/clk70}]
 set_clock_groups -asynchronous -group [get_clocks {Clk_i}] -group [get_clocks {Sck_i}]
 set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Clk_i}] 
 set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Sck_i}] 
-set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {clk60}] 
-set_false_path -from [get_clocks {clk60}] -to [get_clocks {Sck_i}] 
+set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {clk70}] 
+set_false_path -from [get_clocks {clk70}] -to [get_clocks {Sck_i}] 

src/src/ClkGen/ClkGen.v

@@ -37,6 +37,7 @@ module ClkGen (
 	output Clk5Mhz_o,
 	output Clk20Mhz_o,
 	output Clk50Mhz_o,
+	output Clk70Mhz_o,
 	output Clk26dot25Mhz_o,
 	output Clk60Mhz_o
 );
@@ -93,6 +94,7 @@ BUFG BUFG_24Mhz (
 GowinPllSecond GowinPllSecond210M (
 	.clkout		(clk210Mhz),
 	.lock		(lockSecondPll),
+	.clkoutd3	(Clk70Mhz_o),
 	.clkin		(Clk24Mhz_i)
 );
 

src/src/ClkGen/GowinPllSecond/GowinPllSecond.ipc

@@ -7,7 +7,7 @@ type=clock_rpll
 version=1.0
 
 [Config]
-CKLOUTD3=false
+CKLOUTD3=true
 CLKFB_SOURCE=0
 CLKIN_FREQ=24
 CLKOUTD=false
@@ -22,3 +22,4 @@ LOCK_EN=true
 MODE_GENERAL=true
 PLL_PWD=false
 RESET_PLL=false
+CLKOUTD3_SOURCE_CLKOUT=true

src/src/ClkGen/GowinPllSecond/GowinPllSecond.mod

@@ -7,7 +7,7 @@
 
 -mod_name GowinPllSecond
 -file_name GowinPllSecond
--path C:/Gowin/Projects_GOWIN/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinPllSecond/
+-path C:/Gowin/Projects/SB_TMSG44V1_FPGA/src/src/ClkGen/GowinPllSecond/
 -type PLL
 -rPll true
 -file_type vlg
@@ -29,4 +29,5 @@
 -clkoutp_bypass false
 -en_clkoutd false
 -clkoutd_bypass false
--en_clkoutd3 false
+-en_clkoutd3 true
+-clkoutd3_src CLKOUT

src/src/ClkGen/GowinPllSecond/GowinPllSecond.v

@@ -1,21 +1,21 @@
 //Copyright (C)2014-2024 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: IP file
-//Tool Version: V1.9.9.01 (64-bit)
+//Tool Version: V1.9.11 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
 //Device Version: C
-//Created Time: Tue Apr 23 17:39:37 2024
+//Created Time: Tue Apr  8 09:42:12 2025
 
-module GowinPllSecond (clkout, lock, clkin);
+module GowinPllSecond (clkout, lock, clkoutd3, clkin);
 
 output clkout;
 output lock;
+output clkoutd3;
 input clkin;
 
 wire clkoutp_o;
 wire clkoutd_o;
-wire clkoutd3_o;
 wire gw_gnd;
 
 assign gw_gnd = 1'b0;
@@ -25,7 +25,7 @@ rPLL rpll_inst (
     .LOCK(lock),
     .CLKOUTP(clkoutp_o),
     .CLKOUTD(clkoutd_o),
-    .CLKOUTD3(clkoutd3_o),
+    .CLKOUTD3(clkoutd3),
     .RESET(gw_gnd),
     .RESET_P(gw_gnd),
     .CLKIN(clkin),

src/src/ClkGen/GowinPllSecond/GowinPllSecond_tmp.v

@@ -1,19 +1,20 @@
 //Copyright (C)2014-2024 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.01 (64-bit)
+//Tool Version: V1.9.11 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
 //Device Version: C
-//Created Time: Tue Apr 23 17:39:37 2024
+//Created Time: Tue Apr  8 09:42:12 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
     GowinPllSecond your_instance_name(
-        .clkout(clkout_o), //output clkout
-        .lock(lock_o), //output lock
-        .clkin(clkin_i) //input clkin
+        .clkout(clkout), //output clkout
+        .lock(lock), //output lock
+        .clkoutd3(clkoutd3), //output clkoutd3
+        .clkin(clkin) //input clkin
     );
 
 //--------Copy end-------------------

src/src/Top/TopSbTmsg.v

@@ -128,6 +128,7 @@ localparam LED_TICK_RATE = 48000000;//0.5Hz 24MHz
 	wire clk50;
 	wire clk26dot25;
 	wire clk60;
+	wire clk70;
 
 	wire spiDataVal;
 	wire spiDataValSync;
@@ -380,6 +381,7 @@ ClkGen ClkGen
 	.Clk5Mhz_o			(clk5),
 	.Clk20Mhz_o			(clk20),
 	.Clk50Mhz_o			(clk50),
+	.Clk70Mhz_o			(clk70),
 	.Clk26dot25Mhz_o	(clk26dot25),
 	.Clk60Mhz_o			(clk60)
 );
@@ -397,7 +399,7 @@ InterfaceArbiter
 SpiSlaveArbiter
 (
 	.Rst_i		(Rst_i),
-	.Clk_i		(clk60),
+	.Clk_i		(clk70),
 	
 	.Sck_i		(Sck_i),
 	.Ss_i		(Ss_i),
@@ -412,18 +414,9 @@ SpiSlaveArbiter
 	.Data_o		(spiData)
 );
 
-// Sync1bit SyncPulse(
-// 	.ClkFast_i	(gclk100),
-// 	.ClkSlow_i	(clk60),
-// 	.Signal_i	(spiDataVal),
-// 	.Ss_i		(Ss_i),
-// 	.Rst_i		(initRst),
-// 	.Signal_o	(spiDataValSync)	
-// );
-
 PacketAnalyzer4Mosi PacketAnalyzer4Mosi
 (
-	.Clk_i					(clk60),
+	.Clk_i					(clk70),
 	.Rst_i					(Rst_i),
 
 	.DataFromSpi_i			(spiData),
@@ -449,7 +442,7 @@ PacketAnalyzer4Mosi PacketAnalyzer4Mosi
 
 PacketAnalyzer1Mosi	PacketAnalyzer1Mosi
 (
-	.Clk_i					(clk60),
+	.Clk_i					(clk70),
 	.Rst_i					(Rst_i),
 	
 	.DataFromSpi_i			(spiData),
@@ -478,8 +471,8 @@ LmxWrapper #(
 	.OUT_WIDTH			(24),
 	.DATA_WIDTH			(24)
 ) LmxWrapper(
-	.WrClk_i			(clk60),
-	.RdClk_i			(clk60),
+	.WrClk_i			(clk70),
+	.RdClk_i			(clk70),
 	.Rst_i				(initRst),
 	.Data_i				(spiData),
 	.Val_i				(valLmxDataToFifo),
@@ -500,7 +493,7 @@ DDSWrapper #(
 	.OUT_WIDTH			(80),
 	.DATA_WIDTH			(80)
 ) DDSWrapper(
-	.WrClk_i			(clk60),
+	.WrClk_i			(clk70),
 	.RdClk_i			(clk50),
 	.Rst_i				(initRst),
 	.DdsWordNum_i		(ddsWordNum),
@@ -521,7 +514,7 @@ PotWrapper #(
 	.OUT_WIDTH		(16),
 	.DATA_WIDTH		(16)
 ) PotWrapper(
-	.WrClk_i		(clk60),
+	.WrClk_i		(clk70),
 	.RdClk_i		(clk5),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
@@ -537,7 +530,7 @@ DacWrapper #(
 	.OUT_WIDTH		(16),
 	.DATA_WIDTH		(16)
 ) DacWrapper(
-	.WrClk_i		(clk60),
+	.WrClk_i		(clk70),
 	.RdClk_i		(clk50),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
@@ -553,7 +546,7 @@ AttenuatorWrapper #(
 	.OUT_WIDTH		(16),
 	.DATA_WIDTH		(16)
 ) AttenuatorWrapper(
-	.WrClk_i		(clk60),
+	.WrClk_i		(clk70),
 	.RdClk_i		(clk50),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
@@ -569,7 +562,7 @@ ShiftRegWrapper #(
 	.OUT_WIDTH		(8),
 	.DATA_WIDTH		(8)
 ) ShiftRegWrapper(
-	.WrClk_i		(clk60),
+	.WrClk_i		(clk70),
 	.RdClk_i		(clk26dot25),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
@@ -585,7 +578,7 @@ Max2870Wrapper #(
 	.OUT_WIDTH		(32),
 	.DATA_WIDTH		(32)
 ) Max2870Wrapper(
-	.WrClk_i		(clk60),
+	.WrClk_i		(clk70),
 	.RdClk_i		(clk20),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
@@ -607,7 +600,7 @@ TempRead TempRead (
 
 Gpio1Ctrl Gpio1Ctrl
 (
-	.Clk_i					(clk60),
+	.Clk_i					(clk70),
 	.ValGpioDataToFifo_i	(valGpioDataToFifo),
 	.ValDataFromSpi_i		(spiDataVal),
 	.FlagDirectGpio1_i		(flagDirectGpio1),
@@ -616,7 +609,7 @@ Gpio1Ctrl Gpio1Ctrl
 );
 
 Gpio2Read Gpio2Read (
-	.Clk_i				(clk60),
+	.Clk_i				(clk70),
 	.Rst_i				(initRst),
 	.ClkSpi_i			(Sck_i),
 	.LdMax_i			(MisoLdMax2870_i),

src/src/Top/TopSbTmsgTb.sv

@@ -1,4 +1,4 @@
-`timescale 1ns/1ns
+`timescale 1ns/1ps
 
 module TopSbTmsgTb(inout Mosi1_io);
    parameter CLK_PERIOD = 8.13; // Clock period in ns