Исправления в InterfaceArbiter. Понизили частоту до 50 МГц.

src/constr/SbTmsg.sdc

@@ -1,18 +1,14 @@
 //Copyright (C)2014-2024 GOWIN Semiconductor Corporation.
 //All rights reserved.
 //File Title: Timing Constraints file
-//Tool Version: V1.9.9.02 
-//Created Time: 2024-05-02 15:55:01
+//Tool Version: V1.9.9.03 (64-bit) 
+//Created Time: 2024-05-27 16:53:57
+create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
 create_clock -name clk5 -period 200 -waveform {0 100} [get_nets {clk5}]
+//create_clock -name clk100 -period 10 -waveform {0 5} [get_nets {gclk100}]
 //create_clock -name clk50 -period 20 -waveform {0 10} [get_nets {clk50}]
-//create_clock -name clk26dot25 -period 38.095 -waveform {0 19.047} [get_nets {clk26dot25}]
-//create_clock -name clk20 -period 50 -waveform {0 25} [get_nets {clk20}]
-create_clock -name clk100 -period 10 -waveform {0 5} [get_nets {gclk100}]
-//create_clock -name clk210 -period 4.762 -waveform {0 2.381} [get_nets {ClkGen/clk210Mhz}]
 create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
-create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
-//create_clock -name clk60 -period 16.667 -waveform {0 8.334} [get_nets {clk60}]
 set_clock_groups -asynchronous -group [get_clocks {Clk_i}] -group [get_clocks {Sck_i}]
 set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Clk_i}] 
 set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Sck_i}] 
-report_timing -setup -from_clock [get_clocks {clk100}] -max_paths 1000 -max_common_paths 1
+//report_timing -setup -from_clock [get_clocks {clk100}] -mod_ins {SpiSlaveArbiter}

src/src/InterfaceArbiter/InterfaceArbiter.v

@@ -80,13 +80,14 @@ module InterfaceArbiter
 	reg [1:0] currState;
 	
 	reg rxDone;
+	reg spiModeR;
 //================================================================================
 //  ASSIGNMENTS
 	assign ssPos = ssRegR & !ssRegRR;
 
 	
 	assign DataVal_o = dataValReg;
-	assign Data_o = (spiMode)? dataRegQSpi:dataRegSSpi;
+	assign Data_o = (spiModeR)? dataRegQSpi:dataRegSSpi;
 
 	//assign ssCntRstThresh = (spiMode) ? QSPIWORDWIDTH-1:SSPIWORDWIDTH-1;
 	
@@ -132,7 +133,7 @@ module InterfaceArbiter
 		if (!Rst_i) begin
 			if (currState == DATARX) begin
 				if (ssPos) begin
-					if (wordsCnt == wordsNum-1) begin
+					if (wordsCnt == wordsNum) begin
 						wordsCnt <= 0;
 						rxDone <= 1'b1;
 					end else begin
@@ -155,24 +156,35 @@ module InterfaceArbiter
 			spiMode <= 1'b0;
 		end
 		else begin
-			if (ssCnt == 1) begin 
-				if (captRegSspi[0]) begin 
-					spiMode <= 1'b1; 
-				end 
-				else begin 
-					spiMode <= 1'b0; 
+			if (currState == IDLE) begin 
+				if (ssCnt == 1) begin 
+					if (captRegSspi[0]) begin 
+						spiMode <= 1'b1; 
+					end 
+					else begin 
+						spiMode <= 1'b0; 
+					end
 				end
 			end
 		end
 	end
 
+	always @(posedge Clk_i) begin 
+		if (Rst_i) begin 
+			spiModeR <= 1'b0;
+		end
+		else begin 
+			spiModeR <= spiMode;
+		end
+	end
+
 	always @(posedge Clk_i) begin
 		if (!Rst_i) begin
 			if (currState == IDLE) begin
-				if (!spiMode) begin
-					wordsNum <= dataRegSSpi[17:1];
+				if (!spiModeR) begin
+					wordsNum <= dataRegSSpi[17:1] - 17'h1;
 				end else begin
-					wordsNum <= dataRegQSpi[21:19]+dataRegQSpi[17:16]+dataRegQSpi[15:12]+dataRegQSpi[10:9]+dataRegQSpi[7:6]+dataRegQSpi[4]+dataRegQSpi[2]+dataRegQSpi[1];
+					wordsNum <= (dataRegQSpi[21:19]+dataRegQSpi[17:16]+dataRegQSpi[15:12]+dataRegQSpi[10:9]+dataRegQSpi[7:6]+dataRegQSpi[4]+dataRegQSpi[2]+dataRegQSpi[1]) - 17'h1;
 				end 
 			end
 		end else begin

src/src/Top/TopSbTmsg.v

@@ -348,7 +348,7 @@ InterfaceArbiter
 SpiSlaveArbiter
 (
 	.Rst_i		(Rst_i),
-	.Clk_i		(gclk100),
+	.Clk_i		(clk50),
 	
 	.Sck_i		(Sck_i),
 	.Ss_i		(Ss_i),
@@ -364,7 +364,7 @@ SpiSlaveArbiter
 
 PacketAnalyzer4Mosi PacketAnalyzer4Mosi
 (
-	.Clk_i					(gclk100),
+	.Clk_i					(clk50),
 	.Rst_i					(Rst_i),
 
 	.DataFromSpi_i			(spiData),
@@ -390,7 +390,7 @@ PacketAnalyzer4Mosi PacketAnalyzer4Mosi
 
 PacketAnalyzer1Mosi	PacketAnalyzer1Mosi
 (
-	.Clk_i					(gclk100),
+	.Clk_i					(clk50),
 	.Rst_i					(Rst_i),
 	
 	.DataFromSpi_i			(spiData),
@@ -418,7 +418,7 @@ LmxWrapper #(
 	.OUT_WIDTH			(24),
 	.DATA_WIDTH			(24)
 ) LmxWrapper(
-	.WrClk_i			(gclk100),
+	.WrClk_i			(clk50),
 	.RdClk_i			(clk5),
 	.Rst_i				(initRst),
 	.Data_i				(spiData),
@@ -438,7 +438,7 @@ DDSWrapper #(
 	.OUT_WIDTH			(64),
 	.DATA_WIDTH			(64)
 ) DDSWrapper(
-	.WrClk_i			(gclk100),
+	.WrClk_i			(clk50),
 	.RdClk_i			(clk5),
 	.Rst_i				(initRst),
 	.DdsWordNum_i		(ddsWordNum),
@@ -458,7 +458,7 @@ PotWrapper #(
 	.OUT_WIDTH		(16),
 	.DATA_WIDTH		(16)
 ) PotWrapper(
-	.WrClk_i		(gclk100),
+	.WrClk_i		(clk50),
 	.RdClk_i		(clk5),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
@@ -474,7 +474,7 @@ DacWrapper #(
 	.OUT_WIDTH		(16),
 	.DATA_WIDTH		(16)
 ) DacWrapper(
-	.WrClk_i		(gclk100),
+	.WrClk_i		(clk50),
 	.RdClk_i		(clk5),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
@@ -490,7 +490,7 @@ AttenuatorWrapper #(
 	.OUT_WIDTH		(16),
 	.DATA_WIDTH		(16)
 ) AttenuatorWrapper(
-	.WrClk_i		(gclk100),
+	.WrClk_i		(clk50),
 	.RdClk_i		(clk5),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
@@ -506,7 +506,7 @@ ShiftRegWrapper #(
 	.OUT_WIDTH		(8),
 	.DATA_WIDTH		(8)
 ) ShiftRegWrapper(
-	.WrClk_i		(gclk100),
+	.WrClk_i		(clk50),
 	.RdClk_i		(clk5),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
@@ -522,7 +522,7 @@ Max2870Wrapper #(
 	.OUT_WIDTH		(32),
 	.DATA_WIDTH		(32)
 ) Max2870Wrapper(
-	.WrClk_i		(gclk100),
+	.WrClk_i		(clk50),
 	.RdClk_i		(clk5),
 	.Rst_i			(initRst),
 	.Data_i			(spiData),
@@ -544,7 +544,7 @@ TempRead TempRead (
 
 Gpio1Ctrl Gpio1Ctrl
 (
-	.Clk_i					(gclk100),
+	.Clk_i					(clk50),
 	.ValGpioDataToFifo_i	(valGpioDataToFifo),
 	.ValDataFromSpi_i		(spiDataVal),
 	.FlagDirectGpio1_i		(flagDirectGpio1),
@@ -553,7 +553,7 @@ Gpio1Ctrl Gpio1Ctrl
 );
 
 Gpio2Read Gpio2Read (
-	.Clk_i				(gclk100),
+	.Clk_i				(clk50),
 	.Rst_i				(Rst_i),
 	.ClkSpi_i			(Sck_i),
 	.LdMax_i			(MisoLdMax2870_i),

src/src/WrapFifoChain/LmxWrapper.v

@@ -52,6 +52,7 @@ wire lmxFifoEmpty;
 
 reg ssR;
 reg [3:0] lmxWordNumReg; 
+reg [3:0] lmxWordNumRegR;
 //==========================================================================//
 //									CODING									//
 //==========================================================================//
@@ -80,13 +81,22 @@ always @(posedge WrClk_i) begin
 	end
 end
 
+always @(posedge RdClk_i) begin 
+	if (Rst_i) begin 
+		lmxWordNumRegR <= 0;
+	end
+	else begin 
+		lmxWordNumRegR <= lmxWordNumReg;
+	end
+end
+
 always @(posedge WrClk_i) begin 
 	if (Rst_i) begin 
 		PllVtuneCtrl_o <=1'b0;
 	end
 	else begin
 		if (!LmxDirectFlag_i) begin  
-			if ((!Ss_o && ssR) && (lmxWordNumReg != 0) ) begin 
+			if ((!Ss_o && ssR) && (lmxWordNumRegR != 0) ) begin 
 				PllVtuneCtrl_o <= 1'b0;
 			end
 			else begin