Изменена ширина отгрузки данных для DDS - 80

src/src/FifoCtrl/FifoCtrl.v

@@ -75,7 +75,31 @@ always @(posedge WrClk_i) begin
     end
     else begin
         if (WR_NUM>1) begin
-            case (WR_NUM)  
+            case (WR_NUM)
+            4: begin 
+                case (wrCnt)  
+                    0 : begin 
+                        if (Val_i) begin 
+                            dataReg[(4*IN_WIDTH)-1:(3*IN_WIDTH)] <= Data_i;
+                        end
+                    end
+                    1 : begin 
+                        if (Val_i) begin 
+                            dataReg[(3*IN_WIDTH)-1:(2*IN_WIDTH)] <= Data_i;
+                        end
+                    end
+                    2:  begin
+                        if (Val_i) begin
+                            dataReg[(2*IN_WIDTH)-1:IN_WIDTH] <= Data_i;
+                        end
+                    end
+                    3: begin
+                        if (Val_i) begin 
+                        dataReg[IN_WIDTH-1:0] <= Data_i;
+                        end
+                    end
+                endcase
+            end
             3: begin
                 case (wrCnt)
                 0 : begin 

src/src/Top/TopSbTmsg.v

@@ -438,9 +438,9 @@ LmxWrapper #(
 
 DDSWrapper #(
 	.IN_WIDTH			(24),
-	.WR_NUM				(3),
-	.OUT_WIDTH			(64),
-	.DATA_WIDTH			(64)
+	.WR_NUM				(4),
+	.OUT_WIDTH			(80),
+	.DATA_WIDTH			(80)
 ) DDSWrapper(
 	.WrClk_i			(clk50),
 	.RdClk_i			(clk5),

src/src/Top/TopSbTmsgTb.sv

@@ -121,7 +121,7 @@ localparam [23:0] InitAttHeader         = {1'h0, DeviceIdAtt, AttWordInitNum, 1'
 localparam [23:0] InitShRegHeader       = {1'h0, DeviceIdShReg, ShRegWordInitNum, 1'h1};
 
 localparam [3:0]  LMXWordNum = 4'd14;
-localparam [2:0]  DDSWordNum = 3'd3;
+localparam [2:0]  DDSWordNum = 3'd4;
 localparam        POTWordNum = 2'd2;
 localparam        DACWordNum = 1'd1;
 localparam        ATTWordNum = 1'd1;
@@ -142,7 +142,7 @@ assign Mosi0_o = (modeSel) ? mosi0Q : mosi0R;
 assign Mosi1_io = (anyFlag) ? 1'bz : Mosi1_o;
 assign MisoLdLmx_i = 1'b1;
 
-assign emptyFlagTx = (trCnt > 95) ? 1'b1 : 1'b0;
+assign emptyFlagTx = (trCnt > 71) ? 1'b1 : 1'b0;
 assign QSPITotalWordNum = LMXWordNum + DDSWordNum + POTWordNum + DACWordNum + ATTWordNum + ShRegWordNum + MaxWordNum + GPIOWordNum; 
 
 //***********************************************
@@ -188,7 +188,7 @@ initial begin
       wait (trCnt == 70) begin 
             Start_i = 0;
         end
-        #(CLK_PERIOD*100) 
+        #(CLK_PERIOD*1000) 
         Start_i = 1; // Start SPI transaction
   end
 //***********************************************
@@ -317,7 +317,10 @@ always_comb begin
             else if (trCnt == 45) begin 
                 SPIdata = AllDevQSPIHeader;
             end
-            else if (trCnt == 71) begin 
+            else if (trCnt == 46) begin 
+                SPIdata = 7'h55;
+            end
+            else if (trCnt == 72) begin 
                 SPIdata = AllDevQSPIHeader;
             end
             else begin

src/src/WrapFifoChain/DDSWrapper.v

@@ -90,7 +90,7 @@ always @(posedge WrClk_i) begin
 	end
 	else begin 
 		if (DdsWordNumVal_i) begin 
-			ddsWordNumReg <= (DdsWordNum_i + (DdsWordNum_i>>1)+ (DdsWordNum_i>>2))>>2;
+			ddsWordNumReg <= DdsWordNum_i>>2;
 		end
 		else begin 
 			if (Ss_o && !ssR) begin 

src/src/WrapFifoChain/FifoDDS/FifoDDS.ipc

@@ -24,12 +24,12 @@ LANG=0
 OutputRegistersSelected=false
 REG=false
 ReadDataNum=false
-ReadDataWidth=64
+ReadDataWidth=80
 ReadDepth=2
 ResetSynchronization=true
 SSRAM=false
 StandardFIFO=false
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
-WriteDataWidth=64
+WriteDataWidth=80
 WriteDepth=2

src/src/WrapFifoChain/FifoDDS/FifoDDS.v

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:06:49 2024
+//Tool Version "V1.9.9.03 (64-bit)"
+//Tue May 28 15:49:41 2024
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,141 +17,156 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+krH8Dc9bcX5adde2FYFmhmRyz3sc5c38ia3cWA==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=7024)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7872)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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+1WYDV08RKy0MNY1jczT29y62XqMPzol/RmiHLRwP6bSXZB4JUicYxA2gkcRMkXoEhJKFXN6AvREV
+DwLKNhpSDIvM9fDrglt5PggARI37OhzWIboNEMb/eIY0BoLY17bH3z76eu87v9g88gGJlgzN42TH
+Ppm0BSlPUmcVYrg+o8Vze5b/Z4E+BO4BeE8zmcL7UE4/5E5qCA0YYZQwhfOABAkUZuvxnm2JkM7G
+LUKcX1Is
 `pragma protect end_protected
 module FifoDDS (
   Data,
@@ -165,13 +180,13 @@ module FifoDDS (
   Full
 )
 ;
-input [63:0] Data;
+input [79:0] Data;
 input Reset;
 input WrClk;
 input RdClk;
 input WrEn;
 input RdEn;
-output [63:0] Q;
+output [79:0] Q;
 output Empty;
 output Full;
 wire VCC;
@@ -182,10 +197,10 @@ wire GND;
     .WrClk(WrClk),
     .WrEn(WrEn),
     .RdEn(RdEn),
-    .Data(Data[63:0]),
+    .Data(Data[79:0]),
     .Empty(Empty),
     .Full(Full),
-    .Q(Q[63:0])
+    .Q(Q[79:0])
 );
   VCC VCC_cZ (
     .V(VCC)

src/src/WrapFifoChain/FifoDDS/FifoDDS.vo

@@ -1,8 +1,8 @@
 //Copyright (C)2014-2024 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Post-PnR Simulation Model file
-//Tool Version: V1.9.9.02
-//Created Time: Thu Apr 25 16:06:49 2024
+//Tool Version: V1.9.9.03 (64-bit)
+//Created Time: Tue May 28 15:49:41 2024
 
 `timescale 100 ps/100 ps
 module FifoDDS(
@@ -16,20 +16,20 @@ module FifoDDS(
 	Empty,
 	Full
 );
-input [63:0] Data;
+input [79:0] Data;
 input Reset;
 input WrClk;
 input RdClk;
 input WrEn;
 input RdEn;
-output [63:0] Q;
+output [79:0] Q;
 output Empty;
 output Full;
-wire [63:0] Data;
+wire [79:0] Data;
 wire Empty;
 wire Full;
 wire GND;
-wire [63:0] Q;
+wire [79:0] Q;
 wire RdClk;
 wire RdEn;
 wire Reset;
@@ -38,7 +38,7 @@ wire WrClk;
 wire WrEn;
 wire \fifo_inst/n20_5 ;
 wire \fifo_inst/n26_4 ;
-wire \fifo_inst/n457_4 ;
+wire \fifo_inst/n537_4 ;
 wire \fifo_inst/rempty_val ;
 wire \fifo_inst/wfull_val_7 ;
 wire \fifo_inst/wfull_val1 ;
@@ -64,6 +64,7 @@ wire [1:0] \fifo_inst/Equal.rq2_wptr ;
 wire [0:0] \fifo_inst/rptr ;
 wire [1:0] \fifo_inst/wptr ;
 wire [0:0] \fifo_inst/Equal.wbin ;
+wire [31:16] \fifo_inst/DO ;
 VCC VCC_cZ (
   .V(VCC)
 );
@@ -102,12 +103,12 @@ LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
 	.F(\fifo_inst/Equal.wgraynext [0])
 );
 defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
-LUT2 \fifo_inst/n457_s1  (
+LUT2 \fifo_inst/n537_s1  (
 	.I0(\fifo_inst/reset_w [1]),
 	.I1(\fifo_inst/wfull_val_7 ),
-	.F(\fifo_inst/n457_4 )
+	.F(\fifo_inst/n537_4 )
 );
-defparam \fifo_inst/n457_s1 .INIT=4'h4;
+defparam \fifo_inst/n537_s1 .INIT=4'h4;
 LUT4 \fifo_inst/rempty_val_s3  (
 	.I0(\fifo_inst/Equal.rq2_wptr [1]),
 	.I1(\fifo_inst/rempty_val_8 ),
@@ -302,7 +303,7 @@ defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
 	.D(\fifo_inst/wfull_val_7 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n457_4 ),
+	.PRESET(\fifo_inst/n537_4 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -316,7 +317,7 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n457_4 ),
+	.PRESET(\fifo_inst/n537_4 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
@@ -362,6 +363,27 @@ defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BIT_WIDTH_1=32;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .RESET_MODE="ASYNC";
 defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BLK_SEL_0=3'b000;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BLK_SEL_1=3'b000;
+SDPB \fifo_inst/Equal.mem_Equal.mem_0_2_s  (
+	.CLKA(WrClk),
+	.CEA(\fifo_inst/n20_5 ),
+	.RESETA(GND),
+	.CLKB(RdClk),
+	.CEB(\fifo_inst/n26_4 ),
+	.RESETB(\fifo_inst/reset_r [1]),
+	.OCE(GND),
+	.BLKSELA({GND, GND, GND}),
+	.BLKSELB({GND, GND, GND}),
+	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[79:64]}),
+	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND, GND}),
+	.DO({\fifo_inst/DO [31:16], Q[79:64]})
+);
+defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .READ_MODE=1'b0;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .BIT_WIDTH_0=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .BIT_WIDTH_1=32;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .RESET_MODE="ASYNC";
+defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .BLK_SEL_0=3'b000;
+defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .BLK_SEL_1=3'b000;
 INV \fifo_inst/n4_s2  (
 	.I(RdClk),
 	.O(\fifo_inst/n4_6 )

src/src/WrapFifoChain/FifoDDS/FifoDDS_tmp.v

@@ -1,24 +1,24 @@
 //Copyright (C)2014-2024 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.9.03 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:06:49 2024
+//Device: GW1N-9
+//Created Time: Tue May 28 15:49:41 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	FifoDDS your_instance_name(
-		.Data(Data_i), //input [63:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [63:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [79:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [79:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FIFOHS.prj

@@ -4,13 +4,13 @@
     <Version>beta</Version>
     <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
     <FileList>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
     </FileList>
     <OptionList>
         <Option type="disable_insert_pad" value="1"/>
-        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
-        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/FifoDDS/temp/FIFOHS"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Gowin/Projects/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoDDS/temp/FIFOHS"/>
         <Option type="output_file" value="FifoDDS.vg"/>
         <Option type="output_template" value="FifoDDS_tmp.v"/>
         <Option type="ram_balance" value="1"/>

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS.log

@@ -1,19 +1,19 @@
 GowinSynthesis start
 Running parser ...
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
-Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
-Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Compiling module 'FifoDDS'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
-Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoDDS'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 NOTE  (EX0101) : Current top module is "FifoDDS"
 [5%] Running netlist conversion ...
 Running device independent optimization ...
@@ -29,17 +29,17 @@ Running technical mapping ...
 [60%] Tech-Mapping Phase 0 completed
 [65%] Tech-Mapping Phase 1 completed
 [75%] Tech-Mapping Phase 2 completed
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
 [80%] Tech-Mapping Phase 3 completed
 [90%] Tech-Mapping Phase 4 completed
-[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoDDS\temp\FIFOHS\FifoDDS.vg" completed
-Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoDDS\temp\FIFOHS\FifoDDS_tmp.v" completed
-[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoDDS\temp\FIFOHS\FifoDDS_syn.rpt.html" completed
+[95%] Generate netlist file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoDDS\temp\FIFOHS\FifoDDS.vg" completed
+Generate template file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoDDS\temp\FIFOHS\FifoDDS_tmp.v" completed
+[100%] Generate report file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoDDS\temp\FIFOHS\FifoDDS_syn.rpt.html" completed
 GowinSynthesis finish

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS.vg

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:06:49 2024
+//Tool Version "V1.9.9.03 (64-bit)"
+//Tue May 28 15:49:41 2024
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,141 +17,156 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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-Xs0Rq7KS+nMjcFcl7E3CRA+0+XO4iCSxRkS+iA==
+HBNA+/9oSsy54/JlKoiN4gbbgk61v4S0vzu1SlxVV1FpSHLGFM3OwH9RYuOhFT+UXDcUiyGSTSim
+K+dcHv0CeFpV/YQWR5St8DdQGG+R45m6XWDErYGEafyEor0OduRaUiVP0XYqOL50oW/9d9x2NNiT
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+MJjDVvgoM3zUdhRo+JtyCKggxSnoc2ym6iCL/mV/5ly8CtyjxhgYzms2pS3M3jxp5ii+uQ3L2s40
+krH8Dc9bcX5adde2FYFmhmRyz3sc5c38ia3cWA==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=7024)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7872)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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+LUKcX1Is
 `pragma protect end_protected
 module FifoDDS (
   Data,
@@ -165,13 +180,13 @@ module FifoDDS (
   Full
 )
 ;
-input [63:0] Data;
+input [79:0] Data;
 input Reset;
 input WrClk;
 input RdClk;
 input WrEn;
 input RdEn;
-output [63:0] Q;
+output [79:0] Q;
 output Empty;
 output Full;
 wire VCC;
@@ -182,10 +197,10 @@ wire GND;
     .WrClk(WrClk),
     .WrEn(WrEn),
     .RdEn(RdEn),
-    .Data(Data[63:0]),
+    .Data(Data[79:0]),
     .Empty(Empty),
     .Full(Full),
-    .Q(Q[63:0])
+    .Q(Q[79:0])
 );
   VCC VCC_cZ (
     .V(VCC)

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS_syn_resource.html

@@ -30,12 +30,12 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 <th class="label">ROM16 NUMBER</th>
 </tr>
 <tr>
-<td class="label">FifoDDS (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td class="label">FifoDDS (C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
 <td align = "center">19</td>
 <td align = "center">-</td>
 <td align = "center">18</td>
 <td align = "center">-</td>
-<td align = "center">2</td>
+<td align = "center">3</td>
 <td align = "center">-</td>
 <td align = "center">-</td>
 </tr>

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="FifoDDS" Register="19" Lut="18" Bsram="2" T_Register="19(19)" T_Lut="18(18)" T_Bsram="2(2)"/>
+<Module name="FifoDDS" Register="19" Lut="18" Bsram="3" T_Register="19(19)" T_Lut="18(18)" T_Bsram="3(3)"/>

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS_tmp.v

@@ -1,24 +1,24 @@
 //Copyright (C)2014-2024 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.9.03 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:06:49 2024
+//Device: GW1N-9
+//Created Time: Tue May 28 15:49:41 2024
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	FifoDDS your_instance_name(
-		.Data(Data_i), //input [63:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [63:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [79:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [79:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/fifo_parameter.v

@@ -1,6 +1,6 @@
 parameter WDEPTH = 2;
 parameter ASIZE = 1;
-parameter WDSIZE = 64;
+parameter WDSIZE = 80;
 parameter RDEPTH = 2;
 parameter RASIZE = 1;
-parameter RDSIZE = 64;
+parameter RDSIZE = 80;

src/src/WrapFifoChain/LmxWrapper.v

@@ -99,15 +99,13 @@ always @(posedge WrClk_i) begin
 			if ((!Ss_o && ssR) && (lmxWordNumReg != 0) ) begin 
 				PllVtuneCtrl_o <= 1'b0;
 			end
-			else begin
-				if (lmxWordNumReg == 0) begin  
-					PllVtuneCtrl_o <= 1'b1;
-				end
+			else if (lmxWordNumReg == 0 ) begin
+				PllVtuneCtrl_o <= 1'b1;
 			end
 		end
-		// else begin 
-		// 	PllVtuneCtrl_o <= ~LmxDirectFlag_i;
-		// end
+		else begin 
+			PllVtuneCtrl_o <= 1'b1;
+		end
 	end
 end