.gitignore

@@ -0,0 +1,34 @@
+
+#Ignore thumbnails created by Windows
+Thumbs.db
+#Ignore files built by Visual Studio
+*.obj
+*.exe
+*.pdb
+*.user
+*.aps
+*.pch
+*.vspscc
+*_i.c
+*_p.c
+*.ncb
+*.suo
+*.tlb
+*.tlh
+*.bak
+*.cache
+*.ilk
+*.log
+[Bb]in
+[Dd]ebug*/
+*.lib
+*.sbr
+obj/
+[Rr]elease*/
+_ReSharper*/
+[Tt]est[Rr]esult*
+.vs/
+.idea/
+#Nuget packages folder
+packages/
+*.bin

MergingScript/BinsMerge.py

@@ -0,0 +1,310 @@
+import os
+import argparse
+import shutil
+
+GIT_HASH = "e3e4e86fdf3bb66747436c485453fd07"
+GIT_HASH_BIN = bytes.fromhex(GIT_HASH)
+INITIAL_DIR = os.path.dirname(os.path.abspath(__file__))
+
+APP_VER_ADDRESS = 0x6D000
+GOLDEN_APP_VER_ADDRESS = 0xDE000
+GOLDEN_ADDRESS = 0x0071000
+GOLDEN_APP_VERSION_SHIFTED = GOLDEN_APP_VER_ADDRESS-GOLDEN_ADDRESS
+
+
+def get_git_hash():
+    # Проверяем текущую директорию. Если не initial_dir, то переходим в нее
+    print(f"Текущая директория: {os.getcwd()}")
+    print(f"Исходная директория: {INITIAL_DIR}")
+    if os.getcwd() != INITIAL_DIR:
+        os.chdir(INITIAL_DIR)
+    # Переходим в директорию с git репозиторием
+    git_dir = find_git_repository()
+    if git_dir is None:
+        print("Не удалось найти git репозиторий.")
+        return None
+    os.chdir(git_dir)
+    # Получаем git hash --short
+    try:
+        git_hash = os.popen('git rev-parse --short HEAD').read().strip()
+    except Exception as e:
+        print(f"Ошибка при получении git hash: {e}")
+        git_hash = None
+    # Возвращаемся в исходную директорию
+    os.chdir(os.path.dirname(INITIAL_DIR))
+    return git_hash
+
+def get_git_tag():
+      # Проверяем текущую директорию. Если не initial_dir, то переходим в нее
+    if os.getcwd() != INITIAL_DIR:
+        os.chdir(INITIAL_DIR)
+    # Переходим в директорию с git репозиторием
+    git_dir = find_git_repository()
+    if git_dir is None:
+        print("Не удалось найти git репозиторий.")
+        return None
+    os.chdir(git_dir)
+    # Получаем git tag
+    try:
+        git_tag = os.popen('git describe --tags').read().strip()
+    except Exception as e:
+        print(f"Ошибка при получении git tag: {e}")
+        git_tag = None
+    # Возвращаемся в исходную директорию
+    os.chdir(os.path.dirname(INITIAL_DIR))
+    return git_tag
+
+def find_git_repository():
+    current_dir = INITIAL_DIR
+    
+    try:
+        # Выходим выше по дереву каталогов, пока не найдем .git
+        while True:
+            if os.path.isdir(os.path.join(current_dir, '.git')):
+                git_dir = os.path.abspath(os.path.join(current_dir, '.git'))
+                print(f"Найден git репозиторий: {git_dir}")
+                return git_dir
+                
+            parent_dir = os.path.dirname(current_dir)
+            if parent_dir == current_dir:  # Достигли корня файловой системы
+                print("Не удалось найти git репозиторий.")
+                return None
+                
+            current_dir = parent_dir
+            print(f"Проверяем директорию: {current_dir}")
+            
+    except Exception as e:
+        print(f"Ошибка при поиске git репозитория: {e}")
+        return None
+    finally:
+        # Возвращаемся в исходную директорию
+        os.chdir(INITIAL_DIR)
+
+def find_tag(tag_pattern):
+    # Проверяем текущую директорию. Если не initial_dir, то переходим в нее
+    if os.getcwd() != INITIAL_DIR:
+        os.chdir(INITIAL_DIR)
+    # Переходим в директорию с git репозиторием
+    git_dir = find_git_repository()
+    if git_dir is None:
+        print("Не удалось найти git репозиторий.")
+        return None
+    os.chdir(git_dir)
+    # Получаем все теги в git репозитории
+    all_tags = os.popen('git tag').read().strip().split('\n')
+    if not all_tags:
+        print("Не найдено ни одного тега в git репозитории.")
+        return None
+    # Фильтруем теги по заданному шаблону
+    matching_tags = [tag for tag in all_tags if tag_pattern in tag]
+    if not matching_tags:
+        print(f"Не найдено тегов, соответствующих шаблону: {tag_pattern}")
+        return None
+    # Получаем последний тег из списка совпадений
+    latest_tag = matching_tags[-1]
+    print(f"Найден тег: {latest_tag}")
+    # Возвращаемся в исходную директорию
+    os.chdir(os.path.dirname(INITIAL_DIR))
+    return latest_tag
+
+def merge_bins ():
+    #  Пути к файлам
+    os.chdir(INITIAL_DIR)
+    pwd = os.getcwd()
+    file_path_working = os.path.join(INITIAL_DIR, "SB_TMSG44V1_WORKING_FPGA.bin")
+    file_path_golden = os.path.join(INITIAL_DIR, "SB_TMSG44V1_GOLD_FPGA.bin")
+    file_path_output = os.path.join(INITIAL_DIR, "SB_TMSG44V1_TEST_MERGE_FPGA.bin")
+    #  Размеры файлов
+    file_size_working   = os.path.getsize(file_path_working)
+    file_size_golden    = os.path.getsize(file_path_golden)
+    #  Размер выходного файла - 8 Мбит
+    file_size_output    = 0x1000000  
+    # Записываем первый файл
+    with open(file_path_output,'wb') as outfile:
+        with open(file_path_working, 'rb') as f1:
+            shutil.copyfileobj(f1, outfile)
+        # Перемещаемся к адресу для второго файла
+        outfile.seek(GOLDEN_ADDRESS)
+        with open(file_path_golden, 'rb') as f2:
+            shutil.copyfileobj(f2, outfile)
+        # Перемещаемся к адресу для пользовательских данных
+        outfile.seek(APP_VER_ADDRESS)
+        current_git_tag=find_tag("_WORKING")
+        print(f"Текущий git tag: {current_git_tag}")
+        # Если полученный тег меньше 32 байт, то дополняем его до 32 байт
+        encoded_git_tag = current_git_tag.encode('utf-8')
+        if len(encoded_git_tag) < 32:
+            encoded_git_tag = encoded_git_tag.ljust(32, b'\x00')
+
+        # Записываем тег в файл
+        outfile.write(encoded_git_tag)
+        # Перемещаемся к адресу для GOLDEN данных
+        outfile.seek(GOLDEN_APP_VER_ADDRESS)
+        golden_tag = find_tag("_GOLDEN")
+        print(f"Текущий golden git tag: {golden_tag}")
+        # Если полученный тег меньше 32 байт, то дополняем его до 32 байт
+        encoded_golden_tag = golden_tag.encode('utf-8')
+        if len(encoded_golden_tag) < 32:
+            encoded_golden_tag = encoded_golden_tag.ljust(32, b'\x00')
+        outfile.write(encoded_golden_tag)
+    final_size = os.path.getsize(file_path_output)
+    # Проверка итогового размера
+    if final_size > file_size_output:
+        os.remove(file_path_output)  # Удаляем некорректный файл
+        raise ValueError(f"Итоговый размер файла ({final_size} байт) превысил максимально допустимый ({file_size_output} байт)")
+    print(f"Размер файла 1: {file_size_working} байт")
+    print(f"Размер файла 2: {file_size_golden} байт")
+    print(f"Итоговый размер: {final_size} байт")
+    return final_size
+
+def merge_working_only():
+    #  Пути к файлам
+    os.chdir(INITIAL_DIR)
+    pwd = os.getcwd()
+    file_path_working = os.path.join(INITIAL_DIR, "SB_TMSG44V1_WORKING_FPGA.bin")
+    file_path_output = os.path.join(INITIAL_DIR, "SB_TMSG44V1_WORKING_IMAGE_FPGA.bin")
+    #  Размеры файлов
+    file_size_working   = os.path.getsize(file_path_working)
+    #  Размер выходного файла - 8 Мбит
+    file_size_output    = 0x1000000  
+    # Записываем первый файл
+    with open(file_path_output,'wb') as outfile:
+        with open(file_path_working, 'rb') as f1:
+            shutil.copyfileobj(f1, outfile)
+        # Перемещаемся к адресу для пользовательских данных
+        outfile.seek(APP_VER_ADDRESS)
+        current_git_tag=find_tag("_WORKING")
+        print(f"Текущий git tag: {current_git_tag}")
+        # Если полученный тег меньше 32 байт, то дополняем его до 32 байт
+        encoded_git_tag = current_git_tag.encode('utf-8')
+        if len(encoded_git_tag) < 32:
+            encoded_git_tag = encoded_git_tag.ljust(32, b'\x00')
+
+        # Записываем тег в файл
+        outfile.write(encoded_git_tag)
+    final_size = os.path.getsize(file_path_output)
+    # Проверка итогового размера
+    if final_size > file_size_output:
+        os.remove(file_path_output)  # Удаляем некорректный файл
+        raise ValueError(f"Итоговый размер файла ({final_size} байт) превысил максимально допустимый ({file_size_output} байт)")
+    print(f"Размер файла: {file_size_working} байт")
+    print(f"Итоговый размер: {final_size} байт")
+    return final_size
+
+def merge_test_only():
+    #  Пути к файлам
+    os.chdir(INITIAL_DIR)
+    pwd = os.getcwd()
+    file_path_test = os.path.join(INITIAL_DIR, "SB_TMSG44V1_FPGA_TEST.bin")
+    file_path_output = os.path.join(INITIAL_DIR, "SB_TMSG44V1_TEST_FPGA.bin")
+    #  Размеры файлов
+    file_size_test   = os.path.getsize(file_path_test)
+    #  Размер выходного файла - 8 Мбит
+    file_size_output    = 0x1000000  
+    # Записываем первый файл
+    with open(file_path_output,'wb') as outfile:
+        with open(file_path_test, 'rb') as f1:
+            shutil.copyfileobj(f1, outfile)
+        # Перемещаемся к адресу для пользовательских данных
+        outfile.seek(APP_VER_ADDRESS)
+        test_tag = find_tag("_TEST")
+        print(f"Текущий test git tag: {test_tag}")
+        # Если полученный тег меньше 32 байт, то дополняем его до 32 байт
+        encoded_test_tag = test_tag.encode('utf-8')
+        if len(encoded_test_tag) < 32:
+            encoded_test_tag = encoded_test_tag.ljust(32, b'\x00')
+        # Записываем тег в файл
+        outfile.write(encoded_test_tag)
+    final_size = os.path.getsize(file_path_output)
+    # Проверка итогового размера
+    if final_size > file_size_output:
+        os.remove(file_path_output)  # Удаляем некорректный файл
+        raise ValueError(f"Итоговый размер файла ({final_size} байт) превысил максимально допустимый ({file_size_output} байт)")
+    print(f"Размер файла: {file_size_test} байт")
+    print(f"Итоговый размер: {final_size} байт")
+    return final_size
+
+
+def merge_golden_only():
+    #  Пути к файлам
+    os.chdir(INITIAL_DIR)
+    pwd = os.getcwd()
+    file_path_golden = os.path.join(INITIAL_DIR, "SB_TMSG44V1_GOLD_FPGA.bin")
+    file_path_output = os.path.join(INITIAL_DIR, "SB_TMSG44V1_TEST_GOLDEN_FPGA.bin")
+    #  Размеры файлов
+    file_size_golden   = os.path.getsize(file_path_golden)
+    #  Размер выходного файла - 8 Мбит
+    file_size_output    = 0x1000000  
+    # Записываем первый файл
+    with open(file_path_output,'wb') as outfile:
+        with open(file_path_golden, 'rb') as f2:
+            shutil.copyfileobj(f2, outfile)
+        # Перемещаемся к адресу для пользовательских данных
+        outfile.seek(GOLDEN_APP_VERSION_SHIFTED)
+        golden_tag = find_tag("_GOLDEN")
+        print(f"Текущий golden git tag: {golden_tag}")
+        # Если полученный тег меньше 32 байт, то дополняем его до 32 байт
+        encoded_golden_tag = golden_tag.encode('utf-8')
+        if len(encoded_golden_tag) < 32:
+            encoded_golden_tag = encoded_golden_tag.ljust(32, b'\x00')
+        outfile.write(encoded_golden_tag)
+    final_size = os.path.getsize(file_path_output)
+    # Проверка итогового размера
+    if final_size > file_size_output:
+        os.remove(file_path_output)  # Удаляем некорректный файл
+        raise ValueError(f"Итоговый размер файла ({final_size} байт) превысил максимально допустимый ({file_size_output} байт)")
+    print(f"Размер файла: {file_size_golden} байт")
+    print(f"Итоговый размер: {final_size} байт")
+    return final_size
+
+
+def main():
+
+    parser = argparse.ArgumentParser(description='Скрипт для объединения бинарных файлов прошивок')
+    parser.add_argument('--mode', choices=['merge', 'working', 'golden'], 
+                        help='Режим работы: merge - объединить Working и Golden, working - только Working и  Working версию, golden - только Golden и Golden версию',
+                        required=False)
+    
+    args = parser.parse_args()
+    
+    # Если режим не задан через аргумент, запрашиваем у пользователя
+    if args.mode is None:
+        print("Выберите режим работы:")
+        print("1. merge   - объединить Working и Golden прошивки")
+        print("2. working - объединить только Working прошивку с её версией")
+        print("3. golden  - объединить только Golden прошивку с её версией")
+        print("4. test    - объединить только Test прошивку с её версией")
+        
+        choice = ""
+        while choice not in ["1", "2", "3","4", "merge", "working", "golden","test"]:
+            choice = input("Введите номер (1-4) или название режима: ").strip().lower()
+            if choice == "1":
+                choice = "merge"
+            elif choice == "2":
+                choice = "working"
+            elif choice == "3":
+                choice = "golden"
+            elif choice == "4":
+                choice = "test"
+        
+        mode = choice
+    else:
+        mode = args.mode
+    
+    if mode == 'merge':
+        print("Объединение Working и Golden прошивок...")
+        merge_bins()
+    elif mode == 'working':
+        print("Объединение только Working прошивки с её версией...")
+        merge_working_only()
+    elif mode == 'golden':
+        print("Объединение только Golden прошивки с её версией...")
+        merge_golden_only()
+    elif mode == 'test':
+        print("Объединение только Test прошивки с её версией...")
+        merge_test_only()
+
+
+
+if __name__ == '__main__':
+    main()

src/constr/SbTmsg.cst

@@ -1,10 +1,10 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved. 
 //File Title: Physical Constraints file
-//Tool Version: V1.9.9.03 (64-bit)
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
-//Created Time: Wed 02 26 18:14:50 2025
+//Created Time: Wed 06 25 16:51:40 2025
 
 IO_LOC "FpgaLed_o" L16;
 IO_PORT "FpgaLed_o" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
@@ -126,4 +126,4 @@ IO_PORT "Sck_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
 IO_LOC "Rst_i" T9;
 IO_PORT "Rst_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
 IO_LOC "Clk_i" H11;
-IO_PORT "Clk_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
+IO_PORT "Clk_i" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;

src/constr/SbTmsg.sdc

@@ -1,15 +1,21 @@
-//Copyright (C)2014-2024 GOWIN Semiconductor Corporation.
+//Copyright (C)2014-2025 GOWIN Semiconductor Corporation.
 //All rights reserved.
 //File Title: Timing Constraints file
-//Tool Version: V1.9.9.03 (64-bit) 
-//Created Time: 2024-05-31 16:04:42
-create_clock -name clk5 -period 200 -waveform {0 100} [get_nets {clk5}]
-create_clock -name clk60 -period 16.667 -waveform {0 8.334} [get_nets {clk60}]
+//Tool Version: V1.9.11.02 (64-bit) 
+//Created Time: 2025-06-26 10:43:21
 create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
-create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
-//create_clock -name clk100 -period 10 -waveform {0 5} [get_nets {gclk100}]
-set_clock_groups -asynchronous -group [get_clocks {Clk_i}] -group [get_clocks {Sck_i}]
-set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Clk_i}] 
-set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Sck_i}] 
-set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {clk60}] 
-set_false_path -from [get_clocks {clk60}] -to [get_clocks {Sck_i}] 
+create_clock -name Sck_i -period 16.667 -waveform {0 8.334} [get_ports {Sck_i}]
+create_generated_clock -name clk50 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 12 -multiply_by 25 [get_nets {clk50}]
+create_generated_clock -name clk210 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 4 -multiply_by 35 [get_nets {ClkGen/clk210Mhz}]
+create_generated_clock -name clk5 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 120 -multiply_by 25 [get_nets {clk5}]
+create_generated_clock -name clk26dot25 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 32 -multiply_by 35 [get_nets {clk26dot25}]
+create_generated_clock -name clk20 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 30 -multiply_by 25 [get_nets {clk20}]
+create_generated_clock -name clk100 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 6 -multiply_by 25 [get_nets {ClkGen/clk100Mhz}]
+create_generated_clock -name clk60 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 14 -multiply_by 35 [get_nets {clk60}]
+create_generated_clock -name spiClkDds -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 12 -multiply_by 25 [get_nets {ClkAd9912Fpga_o_d}]
+set_clock_groups -asynchronous -group [get_clocks {Clk_i Sck_i}]
+set_false_path -from [get_regs {InitRst/signal_o_s1}] 
+report_timing -setup -max_paths 300 -max_common_paths 1
+report_timing -setup -from_clock [get_clocks {clk60}] -to_clock [get_clocks {clk60}] -max_paths 50 -max_common_paths 1
+report_timing -setup -from_clock [get_clocks {clk50}] -to_clock [get_clocks {clk50}] -max_paths 50 -max_common_paths 1
+report_timing -setup -from_clock [get_clocks {clk100}] -to_clock [get_clocks {clk100}] -max_paths 50 -max_common_paths 1

src/src/CDC/synchronizer.v

@@ -0,0 +1,175 @@
+//---------------------------------------------------
+//------------- BASIC SYNCHRONIZER ------------------
+//---------------------------------------------------
+module basicSynchronizer #
+(	parameter Length = 2)
+(	
+	input Rst_i,	
+	input Clk_i,
+	input D_i,
+	output D_o
+);
+
+	reg [Length-1 : 0] dReg;
+
+	always @ (posedge Rst_i or posedge Clk_i)
+		if (Rst_i)
+			dReg <= 0;
+		else
+			dReg <= {dReg[Length-2 : 0], D_i};
+	
+	assign D_o = dReg[Length - 1];
+	
+endmodule
+
+//---------------------------------------------------
+//--------- EDGE-DETECTING SYNCHRONIZER -------------
+//---------------------------------------------------
+
+module edgeDetectingSynchronizer #
+( 
+	parameter Length = 2,
+	parameter EdgeType = "rising"
+)
+(		
+	input Rst_i,	
+	input Clk_i,
+	input D_i,
+	output D_o
+);
+
+	wire basicSyncOut;
+	reg outReg;
+
+	basicSynchronizer # (.Length(Length)) 
+	basicSynch (
+		.Rst_i(Rst_i),
+		.Clk_i(Clk_i),
+		.D_i(D_i),
+		.D_o(basicSyncOut)
+	);
+		
+	always @ (posedge Rst_i or posedge Clk_i)
+		if (Rst_i)
+			outReg <= 0;
+		else
+			outReg <= basicSyncOut;
+			
+	generate 
+		if (EdgeType == "rising")
+			assign D_o = (basicSyncOut & (~outReg));
+		else
+			assign D_o = ((~basicSyncOut) & (outReg));
+	endgenerate
+	
+endmodule
+
+
+//--------------------------------------------------------------------------
+//------------- FAST-TO-SLOW FREQUENCY DOMAIN SYNCHRONIZER -----------------
+//--------------------------------------------------------------------------
+module fastToSlowSynch
+(		
+	input Rst_i,	
+	input Clk_i,
+	input D_i,
+	output D_o
+);
+
+	reg din_r, dout_r, rsti;
+	
+	wire rsts = (Rst_i || rsti);
+	
+	always @ (posedge rsts or posedge D_i)
+		if (rsts)
+			din_r <= 0;
+		else
+			din_r <= 1;
+			
+	always @ (posedge Rst_i or posedge Clk_i)
+		if (Rst_i)
+			begin
+				dout_r <= 0;
+				rsti <= 0;
+			end
+		else 
+			if (din_r)
+				begin
+					dout_r <= 1;
+					rsti <= 1;
+				end
+			else if (dout_r)
+				begin
+					dout_r <= 0;
+					rsti <= 0;
+				end
+
+	assign D_o = dout_r;	
+	
+endmodule
+
+//--------------------------------------------------------------------------
+//------------- FAST-TO-SLOW FREQUENCY DOMAIN SYNCHRONIZER -----------------
+//--------------------------------------------------------------------------
+module fastToSlowSynchPosPulseStretch #
+(
+	parameter StretchInClock = 2,
+	parameter SyncLength = 2
+)
+(		
+	input Rst_i,
+	input D_i,
+	output D_o,
+	input ClkIn_i,
+	input ClkOut_i
+);
+
+	reg dStretched;
+	generate 
+		if (StretchInClock > 2)
+			begin
+				reg [StretchInClock-2:0] dShReg;
+				always @ (posedge ClkIn_i or posedge Rst_i)
+					if (Rst_i)
+						begin
+							dShReg <= 0;
+							dStretched <= 0;
+						end
+					else
+						begin
+							dShReg <= {dShReg[StretchInClock-3:0], D_i};
+							dStretched <= (D_i || (dShReg != 0)) ? 1 : 0;
+						end
+			end
+		else if (StretchInClock == 2)
+			begin
+				reg dReg;
+				always @ (posedge ClkIn_i or posedge Rst_i)
+					if (Rst_i)
+						begin
+							dReg <= 0;
+							dStretched <= 0;
+						end
+					else
+						begin
+							dReg <= D_i;
+							dStretched <= dReg | D_i;
+						end
+			end
+	endgenerate
+	
+	edgeDetectingSynchronizer #
+	( 
+		.Length(SyncLength),
+		.EdgeType("rising")
+	)
+	edgeSyncInst
+	(		
+		.Rst_i(Rst_i),
+		.Clk_i(ClkOut_i),
+		.D_i(dStretched),
+		.D_o(D_o)
+	);	
+	
+endmodule
+

src/src/FifoCtrl/FifoCtrl.v

@@ -17,6 +17,7 @@
 //
 ////////////////////////////////////////////////////////////////////////////////////////////
 module FifoCtrl #(
+    parameter PARITY_CHECK = 0, // 1 - parity check enabled, 0 - disabled
     parameter IN_WIDTH = 24,
     parameter WR_NUM = 1,
     parameter OUT_WIDTH = 24
@@ -31,6 +32,7 @@ module FifoCtrl #(
     input FifoEmpty_i,
 
     output [OUT_WIDTH-1:0] Data_o,
+    output reg [9:0] ParityBits_o, // 10 bits for parity check
     output reg ReadEn_o,
     output reg  WriteEn_o,
     output reg ValRdData_o
@@ -46,7 +48,7 @@ localparam DATA_WIDTH = WR_NUM*IN_WIDTH;
 //================================================================================
 reg [DATA_WIDTH-1:0] dataReg;
 reg [1:0]  wrCnt;
-
+reg valRdData;
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
@@ -55,6 +57,22 @@ assign Data_o = dataReg[OUT_WIDTH-1:0];
 //================================================================================
 //	CODING
 //================================================================================
+generate
+    if (PARITY_CHECK) begin
+        always @(posedge WrClk_i) begin 
+               if (Rst_i) begin 
+                    ParityBits_o <= 0;
+               end
+               else begin 
+                   if (WriteEn_o) begin
+                       ParityBits_o <= dataReg[95:86];
+                   end
+               end
+        end
+    end
+endgenerate
+        
+
 always @(posedge WrClk_i) begin 
     if (Rst_i) begin 
         wrCnt <= 0;
@@ -165,7 +183,7 @@ always @(posedge RdClk_i) begin
         if (!FifoEmpty_i && !BusySpiM_i) begin 
             ReadEn_o <= 1'b1;
         end
-        else begin 
+        if (ReadEn_o) begin
             ReadEn_o <= 1'b0;
         end
     end
@@ -173,16 +191,20 @@ end
 
 always @(posedge RdClk_i) begin 
     if (Rst_i) begin 
-        ValRdData_o <= 1'b0;
+        valRdData <= 1'b0;
     end
     else begin
         if (!FifoEmpty_i && !BusySpiM_i) begin 
-            ValRdData_o <= 1'b1;
+            valRdData <= 1'b1;
         end
-        else begin 
-            ValRdData_o <= 1'b0;
+        if (valRdData) begin 
+            valRdData <= 1'b0;
         end
     end
 end
 
+always @(posedge RdClk_i) begin 
+    ValRdData_o <= valRdData;
+end
+
 endmodule

src/src/InterfaceArbiter/InterfaceArbiter.v

@@ -39,7 +39,7 @@ module InterfaceArbiter
 	input Mosi3_i,
 	
 	
-	output DataVal_o,
+	output reg DataVal_o,
 	output reg TestTrig_o,
 	output [OUTWORDWIDTH-1:0] Data_o
 );
@@ -77,6 +77,8 @@ module InterfaceArbiter
 	reg ssRegRR;
 	
 	reg spiMode;
+	reg spiModeSyncA;
+	reg spiModeSyncB;
 	
 	wire ssPos;
 	reg ssPosR;
@@ -101,13 +103,16 @@ module InterfaceArbiter
 	reg plsToggleSyncC;
 	reg plsToggleSyncSignalR;
 
+	reg ss_sync1, ss_sync2, ss_sync3;
+	reg ss_posedge_detect;
+
 //================================================================================
 //  ASSIGNMENTS
 	assign ssPos = ssRegR & !ssRegRR;
 
 	
-	assign DataVal_o = plsToggleSyncSignalR;
-	assign Data_o = (spiMode)? dataRegQSpi:dataRegSSpi;
+	// assign DataVal_o = plsToggleSyncSignalR;
+	assign Data_o = (spiModeSyncB)? dataRegQSpi:dataRegSSpi;
 
 	assign plsToggleSyncSignal = plsToggleSyncB^plsToggleSyncA;
 
@@ -116,6 +121,15 @@ module InterfaceArbiter
 //================================================================================
 //  CODING
 
+	always @(posedge Clk_i) begin 
+		if (Rst_i) begin 
+			DataVal_o <= 1'b0;
+		end
+		else begin 
+			DataVal_o <= plsToggleSyncSignalR;
+		end
+	end
+
 	always @(posedge Clk_i) begin 
     	if (Rst_i) begin 
     	    plsToggleSyncA <= 1'b0;
@@ -277,14 +291,25 @@ module InterfaceArbiter
 			end
 		end
 	end
+
+	always @(posedge Clk_i) begin 
+		if (Rst_i) begin 
+			spiModeSyncA <= 1'b0;
+			spiModeSyncB <= 1'b0;
+		end
+		else begin 
+			spiModeSyncA <= spiMode;
+			spiModeSyncB <= spiModeSyncA;
+		end
+	end
 	
 	always @(posedge Clk_i) begin
 		if (!Rst_i) begin
 			if (currState == IDLE) begin
-				if (!spiMode) begin
+				if (!spiModeSyncB) begin
 					wordsNum <= dataRegSSpi[17:1];
 				end else begin
-					wordsNum <= dataRegQSpi[21:19]+dataRegQSpi[17:16]+dataRegQSpi[15:12]+dataRegQSpi[10:9]+dataRegQSpi[7:6]+dataRegQSpi[4:3]+dataRegQSpi[2]+dataRegQSpi[1];
+					wordsNum <= dataRegQSpi[21:19]+dataRegQSpi[17:16]+dataRegQSpi[15:12]+dataRegQSpi[11:9]+dataRegQSpi[7:6]+dataRegQSpi[4:3]+dataRegQSpi[2]+dataRegQSpi[1];
 				end 
 			end
 		end else begin

src/src/PacketAnalyzer4Mosi/PacketAnalyzer4Mosi.v

@@ -90,7 +90,7 @@ assign potOr 	= 	|dataSpiReg[4:3];
 assign dacOr 	= 	 dataSpiReg[2];
 assign attOr 	= 	 dataSpiReg[1];
 assign shRegOr 	= 	|dataSpiReg[7:6];
-assign maxOr 	= 	|dataSpiReg[10:9];
+assign maxOr 	= 	|dataSpiReg[11:9];
 assign gpioOr 	= 	|dataSpiReg[17:16];
 
 assign selector = {ddsOr, gpioOr, lmxOr, maxOr, shRegOr, potOr, dacOr, attOr};

src/src/SPIm/SpiM.v

@@ -17,7 +17,9 @@
 //
 ////////////////////////////////////////////////////////////////////////////////////////////
 module SpiM #(
-    parameter DATA_WIDTH = 24
+    parameter DATA_WIDTH = 24,
+    parameter CS_DELAY = 3'h0,
+    parameter IS_LMX_DELAY = 0
 )(
     input Clk_i,
     input Rst_i,
@@ -51,61 +53,150 @@ endfunction
 //	REG/WIRE
 //================================================================================
 reg [log2(DATA_WIDTH)-1:0] ssCnt;
+reg [2:0] ssCntDelay;
 reg [DATA_WIDTH-1:0] mosiReg;
 reg	ssReg;
-
 //================================================================================
 //  ASSIGNMENTS
 //================================================================================
 assign Ss_o = ssReg;
-assign Mosi_o = (!ssReg) ? mosiReg[DATA_WIDTH-1] : 1'b0;
-assign Sck_o = (!ssReg) ? Clk_i : 1'b0;
+generate 
+    if (IS_LMX_DELAY) begin 
+        assign Sck_o = (!ssReg && ssCnt < DATA_WIDTH && (ssCntDelay == 0)) ? Clk_i : 1'b0;
+        assign Mosi_o = (!ssReg && ssCnt < DATA_WIDTH && (ssCntDelay == 0)) ? mosiReg[DATA_WIDTH-1] : 1'b0;
+    end
+    else begin 
+        assign Sck_o = (!ssReg) ? Clk_i : 1'b0;
+        assign Mosi_o = (!ssReg) ? mosiReg[DATA_WIDTH-1] : 1'b0;
+    end
+endgenerate
+
 assign Busy_o = !ssReg;
 
 //================================================================================
 //	CODING
 //================================================================================
-always @(negedge Clk_i) begin 
-    if (Rst_i) begin 
-        ssCnt <= 7'h0;
-    end
-    else begin
-        if (!ssReg) begin
-			ssCnt <= ssCnt+1;
-		end else begin
-			ssCnt <= 0;
-		end
-    end
-end
+generate
+    if (IS_LMX_DELAY) begin
+        always @(negedge Clk_i) begin 
+            if (Rst_i) begin 
+                ssCnt <= 7'h0;
+            end
+            else begin 
+                if (!ssReg ) begin 
+                    if (ssCntDelay == 3'h0) begin
+                        ssCnt <= ssCnt + 1;
+                    end
+                end
+                else begin
+                    ssCnt <= 0;
+                end
+            end
+        end
+		
+        always @(negedge Clk_i) begin 
+         	if (Rst_i) begin 
+            	ssCntDelay <= 3'h0;
+         	end
+         	else begin
+            	if (ssReg) begin
+					ssCntDelay <= CS_DELAY;
+				end
+				else begin
+					if (ssCntDelay != 3'h0) begin
+						ssCntDelay <= ssCntDelay - 1;
+					end
+				end
+         	end
+        end
 
-always @(negedge Clk_i) begin 
-    if (Rst_i) begin 
-        mosiReg <= 0;
+        always @(negedge Clk_i) begin 
+            if (Rst_i) begin 
+                mosiReg <= 0;
+            end
+            else begin 
+                if ((!ssReg) && (ssCntDelay == 3'h0)) begin 
+                    mosiReg <= mosiReg << 1;
+                end
+                else begin
+                    if (Val_i) begin
+                        mosiReg <= SpiData_i;
+                    end
+                end
+            end
+        end
     end
-    else begin 
-        if (!ssReg) begin 
-            mosiReg <= mosiReg << 1;
+    else begin
+        always @(negedge Clk_i) begin 
+            if (Rst_i) begin 
+                ssCnt <= 7'h0;
+            end
+            else begin 
+                if (!ssReg ) begin 
+                    ssCnt <= ssCnt + 1;
+                end
+                else begin
+                    ssCnt <= 0;
+                end
+            end
         end
-        else begin
-            if (Val_i) begin
-                mosiReg <= SpiData_i;
+		always @(negedge Clk_i) begin 
+			if (Rst_i) begin 
+				ssCntDelay <= 3'h0;
+			end
+			else begin
+				ssCntDelay <= 3'h0;
+			end
+		end
+        always @(negedge Clk_i) begin 
+            if (Rst_i) begin 
+                mosiReg <= 0;
+            end
+            else begin 
+                if (!ssReg) begin 
+                    mosiReg <= mosiReg << 1;
+                end
+                else begin
+                    if (Val_i) begin
+                        mosiReg <= SpiData_i;
+                    end
+                end
             end
         end
     end
-end
+endgenerate
 
-always @(negedge Clk_i) begin 
-    if (Rst_i) begin 
-        ssReg <= 1'b1;
+generate 
+    if (IS_LMX_DELAY) begin 
+        always @(negedge Clk_i) begin 
+            if (Rst_i) begin 
+                ssReg <= 1'b1;
+            end
+            else begin 
+                if (Val_i) begin
+                    ssReg <= 0;
+                end
+                if (ssCnt == DATA_WIDTH) begin
+                    ssReg <= 1;
+                end
+            end
+        end
     end
     else begin 
-        if (Val_i) begin
-			ssReg <= 0;
-		end
-		if (ssCnt == DATA_WIDTH-1) begin
-			ssReg <= 1;
-		end
+        always @(negedge Clk_i) begin 
+            if (Rst_i) begin 
+                ssReg <= 1'b1;
+            end
+            else begin 
+                if (Val_i) begin
+                    ssReg <= 0;
+                end
+                if (ssCnt == DATA_WIDTH - 1 ) begin
+                    ssReg <= 1;
+                end
+            end
+        end
     end
-end
+endgenerate
 
 endmodule

src/src/SpiS/SpiSlave.v

@@ -0,0 +1,120 @@
+module SpiSlave#(
+    parameter WIDTH = 80
+)(
+    input Clk_i,
+    input Rst_i,
+
+    input Sck_i,
+    input Ss_i,
+    input Mosi_i,
+
+    output reg [WIDTH-1:0] Data_o,
+    output reg Val_o
+);
+
+//================================================================================
+//	                                REG/WIRE
+//================================================================================
+reg [WIDTH-1:0] dataShiftReg;
+
+reg ssReg;
+reg ssPosedge;
+
+reg plsToggle;
+reg plsToggleSyncA;
+reg plsToggleSyncB;
+reg plsToggleSyncC;
+wire valPulseSync = plsToggleSyncB ^ plsToggleSyncA;
+
+//================================================================================
+//	                                CODE
+//================================================================================
+always @(posedge Clk_i) begin 
+    ssReg <= Ss_i;
+end
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        ssPosedge <= 1'b0;
+    end
+    else begin 
+        if (!ssReg && Ss_i) begin 
+            ssPosedge <= 1'b1;
+        end
+        else if (ssPosedge) begin 
+            ssPosedge <= 1'b0;
+        end
+    end
+end
+
+always @(posedge Clk_i) begin 
+	if (Rst_i) begin 
+	    plsToggleSyncA <= 1'b0;
+	    plsToggleSyncB <= 1'b0;
+	end
+	else begin 
+	    plsToggleSyncA <= plsToggle;
+	    plsToggleSyncB <= plsToggleSyncA;
+	end
+end
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        plsToggleSyncC <= 1'b0;
+    end
+    else begin
+        plsToggleSyncC <= plsToggleSyncB;
+    end
+end
+
+always @(posedge Ss_i or posedge Rst_i) begin 
+	if (Rst_i) begin 
+		plsToggle <= 1'b0;
+	end
+	else begin 
+		if (Ss_i) begin 
+			plsToggle <= ~plsToggle;
+		end
+		else begin 
+			plsToggle <= plsToggle;
+		end
+	end
+end
+
+always @(posedge Sck_i or posedge Rst_i) begin 
+    if (Rst_i) begin 
+        dataShiftReg <= {WIDTH{1'b0}};
+    end
+    else begin 
+        if (!Ss_i) begin 
+            dataShiftReg <= {dataShiftReg[WIDTH-2:0], Mosi_i};
+        end
+    end
+end
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        Val_o <= 1'b0;
+    end
+    else begin 
+        if (valPulseSync) begin 
+            Val_o <= 1'b1;
+        end
+        else begin
+            Val_o <= 1'b0;
+        end
+    end
+end
+
+always @(posedge Clk_i) begin 
+    if (Rst_i) begin 
+        Data_o <= 1'b0;
+    end
+    else begin 
+        if (valPulseSync) begin 
+            Data_o <= dataShiftReg;
+        end
+    end
+end
+
+
+endmodule

src/src/Top/ExtSpiMEmul.v

@@ -166,9 +166,6 @@ module ExtSpiMEmul (
         end
     end
     
-    
-    
-    
     always @(*) begin
         if (SelSt_i) begin 
             if (PulsePol_i) begin 

src/src/Top/TopSbTmsg.v

@@ -210,6 +210,13 @@ localparam LED_TICK_RATE = 48000000;//0.5Hz 24MHz
 	reg [31:0] ledCnt;
 	/* LedReg */
 	reg ledReg;
+	/* Result of test */
+	reg resultOfTest;
+
+	/* Spi Slave */
+	wire valFromSpiSlave;
+	wire [79:0] dataFromSpiSlave;
+	reg currentSample;
 
 //================================================================================
 //  ASSIGNMENTS
@@ -245,7 +252,9 @@ assign AnyFlag_o = anyFlag;//Debug-only
 
 assign servInfo	= {BOARD_VER, FIRMWARE_VER};
 
-assign FpgaLed_o = ledReg;
+// assign FpgaLed_o = resultOfTest;
+assign FpgaLed_o = ledReg; //Blink Led
+// assign FpgaLed_o = 1'b1; //Golden-Image
 
 //================================================================================
 //  CODING
@@ -371,6 +380,41 @@ always @(*) begin
 	end
 end
 
+SpiSlave #(
+	.WIDTH		(80)
+) SpiS_inst (
+	.Clk_i		(clk50),
+	.Rst_i		(initRst),
+	.Ss_i		(CsAd9912Fpga_o),
+	.Mosi_i		(MosiAd9912Fpga_o),
+	.Sck_i		(ClkAd9912Fpga_o),
+	.Val_o		(valFromSpiSlave),
+	.Data_o		(dataFromSpiSlave)
+);
+
+/* Spi Master Check */
+always @(posedge clk50) begin 
+	if (Rst_i) begin
+		resultOfTest <= 1'b0;
+		currentSample <= 1'b0;
+	end
+	else begin
+		if (valFromSpiSlave) begin 
+			if ((currentSample == 0) && dataFromSpiSlave == 80'hAAAAAAAAAAAAAAAAAAAA ) begin 
+				currentSample <= 1'b1;
+				resultOfTest <= 1'b0;
+			end
+			else if ((currentSample == 1) && dataFromSpiSlave == 80'h55555555555555555555 ) begin 
+				currentSample <= 1'b0;
+				resultOfTest <= 1'b0;
+			end
+			else begin 
+				resultOfTest <= 1'b1; // Ошибка, данные не совпадают
+			end  
+		end
+	end
+end
+
 ClkGen ClkGen
 (
 	.Clk24Mhz_i			(Clk_i),
@@ -503,6 +547,7 @@ DDSWrapper #(
 	.WrClk_i			(clk60),
 	.RdClk_i			(clk50),
 	.Rst_i				(initRst),
+	.RstExt_i			(Rst_i), //External reset for DDS
 	.DdsWordNum_i		(ddsWordNum),
 	.DdsWordNumVal_i	( valWordNum && (ddsWordNum != 0)),
 	.DdsDirectFlag_i	(flagDirectDds),

src/src/Top/TopSbTmsgTb.sv

@@ -1,4 +1,4 @@
-`timescale 1ns/1ns
+`timescale 1ns/1ps
 
 module TopSbTmsgTb(inout Mosi1_io);
    parameter CLK_PERIOD = 8.13; // Clock period in ns
@@ -131,7 +131,7 @@ localparam        POTWordNum = 2'd2;
 localparam        DACWordNum = 1'd1;
 localparam        ATTWordNum = 1'd1;
 localparam [1:0]  ShRegWordNum = 2'd1;
-localparam [1:0]  MaxWordNum =   2'd2;
+localparam [2:0]  MaxWordNum =   3'd2;
 localparam [1:0]  GPIOWordNum =  2'd1;
 
 localparam [23:0] Max2870Header         = {1'h1, 1'h0, 3'h0, 1'h0, 2'h0, 4'h0, 1'h0, MaxWordNum, 1'h0, 2'h0, 1'h0, 2'h0, 1'h0, 1'h0, 1'h1};
@@ -167,7 +167,7 @@ localparam [23:0] GPIO_REG = {DDS_SAW1_FPGA,GPIO_ADRF_V2,GPIO_ADRF_V1,REF_OFFSET
 //***********************************************
 
 // localparam [23:0] AllDevQSPIHeader = {1'h1, LMXWordNum, DDSWordNum, POTWordNum, DACWordNum,ATTWordNum, ShRegWordNum,MaxWordNum, GPIOWordNum, 7'h1};
-localparam [23:0] AllDevQSPIHeader = {1'h1, 1'h0,DDSWordNum,1'h0,GPIOWordNum, LMXWordNum,1'h0,MaxWordNum,1'h0,ShRegWordNum,1'h0,POTWordNum,DACWordNum,ATTWordNum,1'h1};
+localparam [23:0] AllDevQSPIHeader = {1'h1, 1'h0,DDSWordNum,1'h0,GPIOWordNum, LMXWordNum,MaxWordNum,1'h0,ShRegWordNum,1'h0,POTWordNum,DACWordNum,ATTWordNum,1'h1};
 
 //***********************************************
 //	           ASSIGNS
@@ -179,7 +179,7 @@ assign Mosi0_o = (modeSel) ? mosi0Q : mosi0R;
 assign Mosi1_io = (anyFlag) ? 1'bz : Mosi1_o;
 assign MisoLdLmx_i = 1'b1;
 
-assign emptyFlagTx = (trCnt > 74) ? 1'b1 : 1'b0;
+assign emptyFlagTx = (trCnt > 71) ? 1'b1 : 1'b0;
 assign QSPITotalWordNum = LMXWordNum + DDSWordNum + POTWordNum + DACWordNum + ATTWordNum + ShRegWordNum + MaxWordNum + GPIOWordNum; 
 
 assign currClk = (modeSel) ? Clk60 : Clk10;
@@ -397,7 +397,7 @@ always_comb begin
         .Lag_i(LAG_i),
         .Lead_i(LEAD_i),
         .EndianSel_i(EndianSel_i),
-        .Stop_i(6'h0),
+        .Stop_i(6'h3),
         .PulsePol_i(PulsePol_i),
         .Mosi0_o(mosi0R),
         .Sck_o(SckR),

src/src/WrapFifoChain/DDSWrapper.v

@@ -24,6 +24,7 @@ module DDSWrapper #(
     input WrClk_i,
     input RdClk_i,
     input Rst_i,
+	input RstExt_i,
 	input [2:0] DdsWordNum_i,
 	input DdsWordNumVal_i,
 	input DdsDirectFlag_i,
@@ -33,6 +34,8 @@ module DDSWrapper #(
 	output reg DdsSyncFpga_o,
 	output [2:0] DdsWordNumReg_o,
 
+	output reg ResultOfTest_o,
+
     output Ss_o,
     output Sck_o,
     output Mosi_o
@@ -57,16 +60,95 @@ wire ddsFifoEmpty;
 
 reg ssR;
 reg ssReg;
-reg ddsDirectFlagR;
+// reg ddsDirectFlagR;
+reg ddsDirectFlagSyncA;
+reg ddsDirectFlagSyncB;
+reg ddsDirectFlagSyncC;
 reg [2:0] ddsWordNumReg;
-reg [2:0] ddsWordNumRegSync;
+reg [2:0] ddsWordNumRegRdDomain;
+reg [2:0] ddsWordNumRegSyncA;
+reg [2:0] ddsWordNumRegSyncB;
+
+reg [2:0] ddsSyncCnt;
+
+/* WordNumVal Synchronization */
+wire ddsWordNumValSyncRdDomain;
+reg plsToggleWordNumVal;
+reg plsToggleWordNumValSyncA;
+reg plsToggleWordNumValSyncB;
+
+
+reg plsToggle;
+reg plsToggleSyncA;
+reg plsToggleSyncB;
+reg ssPosEdge;
+wire ssPosEdgeSync;
+wire [63:0] dataFromDdsFifoCut;
+reg [9:0] parityErrors;      // Ошибки чётности для каждого байта
+wire [9:0] byteParityBits;   // Вычисленные биты чётности
+wire [9:0] storedParityBits; // Сохранённые биты чётности
+
+// Промежуточные регистры для улучшения тайминга
+reg ssNegEdge;
+reg isLastWord;
+reg directFlagRisingEdge;
 //================================================================================
 //	                                ASSIGNMENTS
 //================================================================================ 
 assign DdsWordNumReg_o = ddsWordNumReg;
+assign ssPosEdgeSync = plsToggleSyncB^plsToggleSyncA;
+assign dataFromDdsFifoCut = dataFromDdsFifo[63:0];
+/* Parity check for each byte */
+assign byteParityBits[0] = ^dataFromDdsFifo[7:0];
+assign byteParityBits[1] = ^dataFromDdsFifo[15:8];
+assign byteParityBits[2] = ^dataFromDdsFifo[23:16];
+assign byteParityBits[3] = ^dataFromDdsFifo[31:24];
+assign byteParityBits[4] = ^dataFromDdsFifo[39:32];
+assign byteParityBits[5] = ^dataFromDdsFifo[47:40];
+assign byteParityBits[6] = ^dataFromDdsFifo[55:48];
+assign byteParityBits[7] = ^dataFromDdsFifo[63:56];
+assign byteParityBits[8] = ^dataFromDdsFifo[71:64];
+assign byteParityBits[9] = ^dataFromDdsFifo[79:72];
+
+/* ddsWordNumVal Synchronization */
+assign ddsWordNumValSyncRdDomain = plsToggleWordNumValSyncB^plsToggleWordNumValSyncA;
 //==========================================================================//
 //									CODING									//
 //==========================================================================//
+always @(posedge WrClk_i) begin 
+	if (Rst_i) begin 
+		plsToggleWordNumVal <= 1'b0;
+	end
+	else if (DdsWordNumVal_i) begin 
+		plsToggleWordNumVal <= ~plsToggleWordNumVal;
+	end
+	else begin 
+		plsToggleWordNumVal <= plsToggleWordNumVal;
+	end
+end
+always @(posedge RdClk_i) begin 
+	if (Rst_i) begin 
+		plsToggleWordNumValSyncA <= 1'b0;
+		plsToggleWordNumValSyncB <= 1'b0;
+	end
+	else begin 
+		plsToggleWordNumValSyncA <= plsToggleWordNumVal;
+		plsToggleWordNumValSyncB <= plsToggleWordNumValSyncA;
+	end
+end
+
+/* Check parity bits */
+always @(posedge RdClk_i) begin 
+	if (Rst_i) begin 
+		parityErrors <= 10'h0;
+	end
+	else begin 
+		if (readEnDds) begin
+			parityErrors <= (storedParityBits ^ byteParityBits);
+		end
+	end
+end 
+
 always @(posedge WrClk_i) begin
 	if (Rst_i) begin 
 		ssR <= 1'b0;
@@ -78,10 +160,14 @@ end
 
 always @(posedge RdClk_i) begin 
 	if (Rst_i) begin 
-		ddsDirectFlagR <= 1'b0;
+		ddsDirectFlagSyncA <= 1'b0;
+		ddsDirectFlagSyncB <= 1'b0;
+		ddsDirectFlagSyncC <= 1'b0;
 	end
 	else begin 
-		ddsDirectFlagR <= DdsDirectFlag_i;
+		ddsDirectFlagSyncA <= DdsDirectFlag_i;
+		ddsDirectFlagSyncB <= ddsDirectFlagSyncA;
+		ddsDirectFlagSyncC <= ddsDirectFlagSyncB;
 	end
 end
 
@@ -89,6 +175,60 @@ always @(posedge RdClk_i) begin
 	ssReg <= Ss_o;
 end
 
+always @(posedge RdClk_i) begin 
+	if (Rst_i) begin 
+		ssPosEdge <= 1'b0;
+	end
+	else begin 
+		ssPosEdge <= (Ss_o && !ssReg);
+	end
+end
+
+// Детекция спадающего фронта SS для улучшения тайминга
+always @(posedge RdClk_i) begin 
+	if (Rst_i) begin 
+		ssNegEdge <= 1'b0;
+	end
+	else begin 
+		ssNegEdge <= (!Ss_o && ssReg);
+	end
+end
+
+// Предварительное вычисление условий для улучшения тайминга
+always @(posedge RdClk_i) begin 
+	if (Rst_i) begin 
+		isLastWord <= 1'b0;
+		directFlagRisingEdge <= 1'b0;
+	end
+	else begin 
+		isLastWord <= (ddsWordNumRegSyncB == 3'h1);
+		directFlagRisingEdge <= (ddsDirectFlagSyncC && !ddsDirectFlagSyncB);
+	end
+end
+
+always @(posedge RdClk_i) begin 
+	if (Rst_i) begin 
+		plsToggle <= 1'b0;
+	end
+	else if (ssPosEdge) begin 
+		plsToggle <= ~plsToggle;
+	end
+	else begin 
+		plsToggle <= plsToggle;
+	end
+end
+
+always @(posedge WrClk_i) begin 
+	if (Rst_i) begin 
+		plsToggleSyncA <= 1'b0;
+		plsToggleSyncB <= 1'b0;
+	end
+	else begin 
+		plsToggleSyncA <= plsToggle;
+		plsToggleSyncB <= plsToggleSyncA;
+	end
+end
+
 always @(posedge WrClk_i) begin
 	if (Rst_i) begin 
 		ddsWordNumReg <= 3'h0;
@@ -98,7 +238,7 @@ always @(posedge WrClk_i) begin
 			ddsWordNumReg <= DdsWordNum_i>>2;
 		end
 		else begin 
-			if (Ss_o && !ssR) begin 
+			if (ssPosEdgeSync && (ddsWordNumReg > 0)) begin 
 				ddsWordNumReg <= ddsWordNumReg-1;
 			end
 		end
@@ -107,10 +247,12 @@ end
 
 always @(posedge RdClk_i) begin 
 	if (Rst_i) begin 
-		ddsWordNumRegSync <= 3'h0;
+		ddsWordNumRegSyncA <= 3'h0;
+		ddsWordNumRegSyncB <= 3'h0;
 	end
 	else begin 
-		ddsWordNumRegSync <= ddsWordNumReg;
+		ddsWordNumRegSyncA <= ddsWordNumReg;
+		ddsWordNumRegSyncB <= ddsWordNumRegSyncA;
 	end
 end
 
@@ -119,25 +261,23 @@ always @(posedge RdClk_i) begin
 		DdsSyncFpga_o <= 1'b0;
 	end
 	else begin
-		if (ddsDirectFlagR && !DdsDirectFlag_i) begin 
-				DdsSyncFpga_o <= 1'b1;
+		if (directFlagRisingEdge) begin 
+			DdsSyncFpga_o <= 1'b1;
 		end 
-		else if ((!Ss_o && ssReg) && (ddsWordNumRegSync != 0)) begin 
+		else if (ssNegEdge && (ddsWordNumRegSyncB != 0)) begin 
 			DdsSyncFpga_o <= 1'b0;
 		end
+		else if (isLastWord && ssPosEdge) begin 
+			DdsSyncFpga_o <= 1'b1;
+		end
 		else begin 
-			if (ddsWordNumRegSync == 3'h1 && (Ss_o && !ssReg)) begin 
-				DdsSyncFpga_o <= 1'b1;
-			end
-			else begin 
-				DdsSyncFpga_o <= 1'b0;
-			end
+			DdsSyncFpga_o <= DdsSyncFpga_o; // Удерживаем состояние
 		end
 	end
-end 
-
+end
 
 FifoCtrl #(
+	.PARITY_CHECK	(1),
 	.IN_WIDTH		(IN_WIDTH),
 	.WR_NUM			(WR_NUM),
 	.OUT_WIDTH		(OUT_WIDTH)
@@ -152,6 +292,7 @@ FifoCtrl #(
 	.FifoFull_i		(ddsFifoFull),
 	.FifoEmpty_i	(ddsFifoEmpty),
 	.Data_o			(dataFromDdsFifoCtrl),
+	.ParityBits_o	(storedParityBits),
 	.ReadEn_o		(readEnDds),
 	.WriteEn_o		(writeEnDds),
 	.ValRdData_o	(valRdDataDDS)

src/src/WrapFifoChain/Fifo16x3/Fifo16x3.ipc

@@ -17,7 +17,7 @@ ECCSelected=false
 EmptyClear=1
 EmptySet=1
 EnReset=true
-FirstWordFallThrough=true
+FirstWordFallThrough=false
 FullClear=1
 FullSet=1
 LANG=0
@@ -28,7 +28,7 @@ ReadDataWidth=16
 ReadDepth=2
 ResetSynchronization=true
 SSRAM=false
-StandardFIFO=false
+StandardFIFO=true
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
 WriteDataWidth=16

src/src/WrapFifoChain/Fifo16x3/Fifo16x3.v

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:04:59 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 11:09:42 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,129 +17,119 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+nrwY8z/Nec9IUKlRrVQ6JMH6jCXJWlZETP2N5w==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=6368)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=5808)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
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+8Y929ghVPldL4T/Trv6dbli9LlDaIUtq8jZMxgxh7aHUFXyb2fBagUdFb8e4vJzhjHI7c9izrwiZ
+C4lWyBXTiHia8tobNfy7dWV8S8nWtukIB+rcpSTuE0ipZQXmXuZNxwSvZa3LAj5Cpq3jDG3/DNZ3
+7yTzVOomWi6xN3ngvgndqS+dwk9x9T0DVHNRc8IDrh3Kjs9hzLEmLhIZvl3TYpiun2q5MfuXm8na
+TekEdh0l6AEsBxTqb3ASjsuiovB1xWU8hlpeyrpnMojn1HWVNIpYt4ZEWuq2qDGV2+dRhXHJetQb
+DBPG4Z3IbxCzi3HLB3mHvl7XE681BVKfqTfrgEqkpOBQclA7S29yOIAAAdN0Evnt5jnSoK4zG2iC
+qW670Kk+owYXAx8KCSQhW+1M5rSgUxuZigcNr9n7ZngiXYuEo90j8o6GnOVudOvFLYEAtmJ/zziY
+D1n0h8I0UuOLdKaUJ5VVE4i4B9voeoIZ2HlmIm42y5S1Bh3lgt4nAzBqvEZK+VDG2ySLFBfR8SE6
+RYEsmIq9RScXoEYLGY3etSzXrTR26lQ6aZnd5YzKhMMpbeLqwVvmMeoKgVTmOoZrvlyRjqq6VgZx
+6O/WVd2n4OZn50QrzXw8E5VTIxf9Z2A36Bb60CZGOwgTI3LvU/aF4waJtb7hGgvPye/czdXL7+tB
+gnxJGiy2IVYyK0+l9xQ8YUUxCCZFeqLBGbMJpNzlfVXcQVrvYKWhnmUA2yuMnOig3ylLYL2P1i1+
+pOQyrW3R2AWbxj+DvhhfjLx9DLdYLzUuMmk/wo1gJ2u57yydr4d2LKOykzxRCKOk8rTwxZXLA2Ha
+oagLmaAnKzA8GUG3ZAnE+w5KNLyQOyf0DTpl215Xyupc4TvhfcaXscM9XWLq/O/VdT+ShT9vVbuQ
+kKVmo8TijCsLP5sLJoWho7WDsTq4JTqi7gDUPWihwv73gjB/rcAI1HulBf29HNITMbn38B8z5frr
+i+A+6O/DT+VQc7XByM7CUm2P8mjtWvj3qlDa1EuNXfnVi+0U3I14ZjXsxJ+mBoojQu9T6KuQaSeH
+IltQcX3ytTiZkI/v/TmyfAndUsETXkBuUawNPJMIEAF6pZx5OxJ/aVHrzh/3vahEbX5t
 `pragma protect end_protected
 module Fifo16x3 (
   Data,

src/src/WrapFifoChain/Fifo16x3/Fifo16x3.vo

@@ -1,8 +1,8 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
-//File Title: Post-PnR Simulation Model file
-//Tool Version: V1.9.9.02
-//Created Time: Thu Apr 25 16:04:59 2024
+//File Title: Post-PnR Verilog Simulation Model file
+//Tool Version: V1.9.11.02 (64-bit)
+//Created Time: Thu Jun 26 11:09:43 2025
 
 `timescale 100 ps/100 ps
 module Fifo16x3(
@@ -37,30 +37,30 @@ wire VCC;
 wire WrClk;
 wire WrEn;
 wire \fifo_inst/n20_5 ;
-wire \fifo_inst/n26_4 ;
-wire \fifo_inst/n217_4 ;
+wire \fifo_inst/n24_3 ;
+wire \fifo_inst/n167_3 ;
+wire \fifo_inst/n218_4 ;
 wire \fifo_inst/rempty_val ;
 wire \fifo_inst/wfull_val_7 ;
 wire \fifo_inst/wfull_val1 ;
 wire \fifo_inst/wfull_val1_0 ;
 wire \fifo_inst/Full_1 ;
-wire \fifo_inst/Equal.wbinnext_0_7 ;
-wire \fifo_inst/rempty_val_8 ;
+wire \fifo_inst/Equal.wbinnext_0_8 ;
+wire \fifo_inst/rbin_num_next_0_10 ;
+wire \fifo_inst/rempty_val1 ;
 wire \fifo_inst/wfull_val1_2 ;
 wire \fifo_inst/wfull_val1_3 ;
 wire \fifo_inst/Full_1_2 ;
 wire \fifo_inst/Full_2 ;
 wire \fifo_inst/n4_6 ;
 wire \fifo_inst/n9_6 ;
-wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [0:0] \fifo_inst/Equal.wgraynext ;
-wire [1:0] \fifo_inst/rbin_num_next ;
 wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:1] \fifo_inst/rbin_num_next ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [1:0] \fifo_inst/reset_r ;
 wire [1:0] \fifo_inst/reset_w ;
 wire [1:0] \fifo_inst/rbin_num ;
-wire [1:0] \fifo_inst/Equal.rq1_wptr ;
-wire [1:0] \fifo_inst/Equal.rq2_wptr ;
 wire [0:0] \fifo_inst/rptr ;
 wire [1:0] \fifo_inst/wptr ;
 wire [0:0] \fifo_inst/Equal.wbin ;
@@ -82,41 +82,39 @@ LUT4 \fifo_inst/n20_s1  (
 	.F(\fifo_inst/n20_5 )
 );
 defparam \fifo_inst/n20_s1 .INIT=16'h5300;
-LUT3 \fifo_inst/n26_s1  (
-	.I0(RdEn),
-	.I1(Empty),
-	.I2(\fifo_inst/rempty_val ),
-	.F(\fifo_inst/n26_4 )
-);
-defparam \fifo_inst/n26_s1 .INIT=8'h0E;
-LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
-	.I0(\fifo_inst/rbin_num [0]),
-	.I1(\fifo_inst/rbin_num_next [0]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/Equal.rgraynext [0])
+LUT2 \fifo_inst/n24_s0  (
+	.I0(Empty),
+	.I1(RdEn),
+	.F(\fifo_inst/n24_3 )
 );
-defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+defparam \fifo_inst/n24_s0 .INIT=4'h4;
 LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wgraynext [0])
 );
 defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
-LUT2 \fifo_inst/n217_s1  (
+LUT2 \fifo_inst/n167_s0  (
+	.I0(\fifo_inst/rempty_val ),
+	.I1(\fifo_inst/reset_r [1]),
+	.F(\fifo_inst/n167_3 )
+);
+defparam \fifo_inst/n167_s0 .INIT=4'hE;
+LUT2 \fifo_inst/n218_s1  (
 	.I0(\fifo_inst/reset_w [1]),
 	.I1(\fifo_inst/wfull_val_7 ),
-	.F(\fifo_inst/n217_4 )
+	.F(\fifo_inst/n218_4 )
 );
-defparam \fifo_inst/n217_s1 .INIT=4'h4;
+defparam \fifo_inst/n218_s1 .INIT=4'h4;
 LUT4 \fifo_inst/rempty_val_s3  (
-	.I0(\fifo_inst/Equal.rq2_wptr [1]),
-	.I1(\fifo_inst/rempty_val_8 ),
-	.I2(\fifo_inst/Equal.rq2_wptr [0]),
-	.I3(\fifo_inst/rbin_num_next [0]),
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.I3(\fifo_inst/rbin_num [1]),
 	.F(\fifo_inst/rempty_val )
 );
-defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h9009;
 LUT4 \fifo_inst/wfull_val_s3  (
 	.I0(\fifo_inst/wptr [0]),
 	.I1(\fifo_inst/wptr [1]),
@@ -133,8 +131,8 @@ LUT3 \fifo_inst/wfull_val1_s9  (
 );
 defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
 LUT3 \fifo_inst/wfull_val1_s10  (
-	.I0(\fifo_inst/wfull_val_7 ),
-	.I1(\fifo_inst/wfull_val1_0 ),
+	.I0(\fifo_inst/wfull_val1_0 ),
+	.I1(\fifo_inst/wfull_val_7 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/wfull_val1_0 )
 );
@@ -147,47 +145,48 @@ LUT3 \fifo_inst/Full_d_s  (
 );
 defparam \fifo_inst/Full_d_s .INIT=8'hAC;
 LUT3 \fifo_inst/Full_s8  (
-	.I0(\fifo_inst/wfull_val_7 ),
-	.I1(\fifo_inst/Full_1 ),
+	.I0(\fifo_inst/Full_1 ),
+	.I1(\fifo_inst/wfull_val_7 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/Full_1 )
 );
 defparam \fifo_inst/Full_s8 .INIT=8'h0E;
-LUT3 \fifo_inst/rbin_num_next_0_s5  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rbin_num_next [0])
-);
-defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
-LUT3 \fifo_inst/rbin_num_next_1_s2  (
-	.I0(\fifo_inst/rbin_num_next [0]),
-	.I1(\fifo_inst/rbin_num [0]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/rbin_num_next [1])
-);
-defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
 LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
-	.F(\fifo_inst/Equal.wbinnext_0_7 )
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wbinnext_0_8 )
 );
 defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
 LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wbinnext [1])
 );
 defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
-LUT4 \fifo_inst/rempty_val_s4  (
-	.I0(\fifo_inst/Equal.rq2_wptr [0]),
-	.I1(\fifo_inst/Equal.rq2_wptr [1]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.I3(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rempty_val_8 )
+LUT4 \fifo_inst/rbin_num_next_1_s3  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s3 .INIT=16'hBF40;
+LUT3 \fifo_inst/rbin_num_next_0_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next_0_10 )
+);
+defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
+LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
 );
-defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
+defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
 DFFP \fifo_inst/reset_r_0_s0  (
 	.D(GND),
 	.CLK(\fifo_inst/n4_6 ),
@@ -217,40 +216,12 @@ DFFC \fifo_inst/rbin_num_1_s0  (
 );
 defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/rbin_num_0_s0  (
-	.D(\fifo_inst/rbin_num_next [0]),
+	.D(\fifo_inst/rbin_num_next_0_10 ),
 	.CLK(RdClk),
 	.CLEAR(\fifo_inst/reset_r [1]),
 	.Q(\fifo_inst/rbin_num [0])
 );
 defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
-	.D(\fifo_inst/wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [1])
-);
-defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
-	.D(\fifo_inst/wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [0])
-);
-defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [1])
-);
-defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [0])
-);
-defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/rptr_0_s0  (
 	.D(\fifo_inst/Equal.rgraynext [0]),
 	.CLK(RdClk),
@@ -273,16 +244,23 @@ DFFC \fifo_inst/wptr_0_s0  (
 );
 defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/Equal.wbin_0_s0  (
-	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.D(\fifo_inst/Equal.wbinnext_0_8 ),
 	.CLK(WrClk),
 	.CLEAR(\fifo_inst/reset_w [1]),
 	.Q(\fifo_inst/Equal.wbin [0])
 );
 defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
-DFFP \fifo_inst/Empty_s0  (
+DFFP \fifo_inst/rempty_val1_s0  (
 	.D(\fifo_inst/rempty_val ),
 	.CLK(RdClk),
-	.PRESET(\fifo_inst/reset_r [1]),
+	.PRESET(\fifo_inst/n167_3 ),
+	.Q(\fifo_inst/rempty_val1 )
+);
+defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val1 ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n167_3 ),
 	.Q(Empty)
 );
 defparam \fifo_inst/Empty_s0 .INIT=1'b1;
@@ -303,7 +281,7 @@ defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
 	.D(\fifo_inst/wfull_val_7 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n217_4 ),
+	.PRESET(\fifo_inst/n218_4 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -317,7 +295,7 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n217_4 ),
+	.PRESET(\fifo_inst/n218_4 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
@@ -326,14 +304,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
 	.CEA(\fifo_inst/n20_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n26_4 ),
+	.CEB(\fifo_inst/n24_3 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[15:0]}),
 	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, GND, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND, GND}),
 	.DO({\fifo_inst/DO [31:16], Q[15:0]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;

src/src/WrapFifoChain/Fifo16x3/Fifo16x3_tmp.v

@@ -1,24 +1,24 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:04:59 2024
+//Device: GW1N-9
+//Created Time: Thu Jun 26 11:09:42 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	Fifo16x3 your_instance_name(
-		.Data(Data_i), //input [15:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [15:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [15:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [15:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/FIFOHS.prj

@@ -4,17 +4,19 @@
     <Version>beta</Version>
     <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
     <FileList>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
     </FileList>
     <OptionList>
         <Option type="disable_insert_pad" value="1"/>
-        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
-        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/Fifo16x3/temp/FIFOHS"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Gowin/Projects/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS"/>
         <Option type="output_file" value="Fifo16x3.vg"/>
         <Option type="output_template" value="Fifo16x3_tmp.v"/>
         <Option type="ram_balance" value="1"/>
         <Option type="ram_rw_check" value="1"/>
+        <Option type="vcc" value="1.2"/>
+        <Option type="vccx" value="3.3"/>
         <Option type="verilog_language" value="sysv-2017"/>
     </OptionList>
 </Project>

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/Fifo16x3.log

@@ -1,19 +1,28 @@
 GowinSynthesis start
 Running parser ...
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
-Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
-Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Compiling module 'Fifo16x3'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
-Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'Reset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'RPReset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'Fifo16x3'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 NOTE  (EX0101) : Current top module is "Fifo16x3"
 [5%] Running netlist conversion ...
 Running device independent optimization ...
@@ -29,17 +38,17 @@ Running technical mapping ...
 [60%] Tech-Mapping Phase 0 completed
 [65%] Tech-Mapping Phase 1 completed
 [75%] Tech-Mapping Phase 2 completed
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
 [80%] Tech-Mapping Phase 3 completed
 [90%] Tech-Mapping Phase 4 completed
-[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\Fifo16x3\temp\FIFOHS\Fifo16x3.vg" completed
-Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\Fifo16x3\temp\FIFOHS\Fifo16x3_tmp.v" completed
-[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\Fifo16x3\temp\FIFOHS\Fifo16x3_syn.rpt.html" completed
+[95%] Generate netlist file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\Fifo16x3\temp\FIFOHS\Fifo16x3.vg" completed
+Generate template file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\Fifo16x3\temp\FIFOHS\Fifo16x3_tmp.v" completed
+[100%] Generate report file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\Fifo16x3\temp\FIFOHS\Fifo16x3_syn.rpt.html" completed
 GowinSynthesis finish

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/Fifo16x3.vg

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:04:59 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 11:09:42 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,129 +17,119 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+nrwY8z/Nec9IUKlRrVQ6JMH6jCXJWlZETP2N5w==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=6368)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=5808)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module Fifo16x3 (
   Data,

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/Fifo16x3_syn_resource.html

@@ -30,8 +30,8 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 <th class="label">ROM16 NUMBER</th>
 </tr>
 <tr>
-<td class="label">Fifo16x3 (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
-<td align = "center">19</td>
+<td class="label">Fifo16x3 (C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">16</td>
 <td align = "center">-</td>
 <td align = "center">18</td>
 <td align = "center">-</td>

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/Fifo16x3_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="Fifo16x3" Register="19" Lut="18" Bsram="1" T_Register="19(19)" T_Lut="18(18)" T_Bsram="1(1)"/>
+<Module name="Fifo16x3" Register="16" Lut="18" Bsram="1" T_Register="16(16)" T_Lut="18(18)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/Fifo16x3_tmp.v

@@ -1,24 +1,24 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:04:59 2024
+//Device: GW1N-9
+//Created Time: Thu Jun 26 11:09:42 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	Fifo16x3 your_instance_name(
-		.Data(Data_i), //input [15:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [15:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [15:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [15:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/fifo_define.v

@@ -1,5 +1,4 @@
 `define module_name Fifo16x3
 `define EBR_BASED
-`define FWFT
 `define En_Reset
 `define Reset_Synchronization

src/src/WrapFifoChain/FifoDDS/FifoDDS.ipc

@@ -17,7 +17,7 @@ ECCSelected=false
 EmptyClear=1
 EmptySet=1
 EnReset=true
-FirstWordFallThrough=true
+FirstWordFallThrough=false
 FullClear=1
 FullSet=1
 LANG=0
@@ -28,7 +28,7 @@ ReadDataWidth=80
 ReadDepth=2
 ResetSynchronization=true
 SSRAM=false
-StandardFIFO=false
+StandardFIFO=true
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
 WriteDataWidth=80

src/src/WrapFifoChain/FifoDDS/FifoDDS.v

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.03 (64-bit)"
-//Tue May 28 15:49:41 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 11:09:20 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,156 +17,146 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+sPn/fYjDgkHcdGVe++mN41kzGiD37X68lMYU8Q==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=7872)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7312)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module FifoDDS (
   Data,

src/src/WrapFifoChain/FifoDDS/FifoDDS.vo

@@ -1,8 +1,8 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
-//File Title: Post-PnR Simulation Model file
-//Tool Version: V1.9.9.03 (64-bit)
-//Created Time: Tue May 28 15:49:41 2024
+//File Title: Post-PnR Verilog Simulation Model file
+//Tool Version: V1.9.11.02 (64-bit)
+//Created Time: Thu Jun 26 11:09:20 2025
 
 `timescale 100 ps/100 ps
 module FifoDDS(
@@ -37,30 +37,30 @@ wire VCC;
 wire WrClk;
 wire WrEn;
 wire \fifo_inst/n20_5 ;
-wire \fifo_inst/n26_4 ;
-wire \fifo_inst/n537_4 ;
+wire \fifo_inst/n24_3 ;
+wire \fifo_inst/n423_3 ;
+wire \fifo_inst/n538_4 ;
 wire \fifo_inst/rempty_val ;
 wire \fifo_inst/wfull_val_7 ;
 wire \fifo_inst/wfull_val1 ;
 wire \fifo_inst/wfull_val1_0 ;
 wire \fifo_inst/Full_1 ;
-wire \fifo_inst/Equal.wbinnext_0_7 ;
-wire \fifo_inst/rempty_val_8 ;
+wire \fifo_inst/Equal.wbinnext_0_8 ;
+wire \fifo_inst/rbin_num_next_0_10 ;
+wire \fifo_inst/rempty_val1 ;
 wire \fifo_inst/wfull_val1_2 ;
 wire \fifo_inst/wfull_val1_3 ;
 wire \fifo_inst/Full_1_2 ;
 wire \fifo_inst/Full_2 ;
 wire \fifo_inst/n4_6 ;
 wire \fifo_inst/n9_6 ;
-wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [0:0] \fifo_inst/Equal.wgraynext ;
-wire [1:0] \fifo_inst/rbin_num_next ;
 wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:1] \fifo_inst/rbin_num_next ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [1:0] \fifo_inst/reset_r ;
 wire [1:0] \fifo_inst/reset_w ;
 wire [1:0] \fifo_inst/rbin_num ;
-wire [1:0] \fifo_inst/Equal.rq1_wptr ;
-wire [1:0] \fifo_inst/Equal.rq2_wptr ;
 wire [0:0] \fifo_inst/rptr ;
 wire [1:0] \fifo_inst/wptr ;
 wire [0:0] \fifo_inst/Equal.wbin ;
@@ -82,41 +82,39 @@ LUT4 \fifo_inst/n20_s1  (
 	.F(\fifo_inst/n20_5 )
 );
 defparam \fifo_inst/n20_s1 .INIT=16'h5300;
-LUT3 \fifo_inst/n26_s1  (
-	.I0(RdEn),
-	.I1(Empty),
-	.I2(\fifo_inst/rempty_val ),
-	.F(\fifo_inst/n26_4 )
-);
-defparam \fifo_inst/n26_s1 .INIT=8'h0E;
-LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
-	.I0(\fifo_inst/rbin_num [0]),
-	.I1(\fifo_inst/rbin_num_next [0]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/Equal.rgraynext [0])
+LUT2 \fifo_inst/n24_s0  (
+	.I0(Empty),
+	.I1(RdEn),
+	.F(\fifo_inst/n24_3 )
 );
-defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+defparam \fifo_inst/n24_s0 .INIT=4'h4;
 LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wgraynext [0])
 );
 defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
-LUT2 \fifo_inst/n537_s1  (
+LUT2 \fifo_inst/n423_s0  (
+	.I0(\fifo_inst/rempty_val ),
+	.I1(\fifo_inst/reset_r [1]),
+	.F(\fifo_inst/n423_3 )
+);
+defparam \fifo_inst/n423_s0 .INIT=4'hE;
+LUT2 \fifo_inst/n538_s1  (
 	.I0(\fifo_inst/reset_w [1]),
 	.I1(\fifo_inst/wfull_val_7 ),
-	.F(\fifo_inst/n537_4 )
+	.F(\fifo_inst/n538_4 )
 );
-defparam \fifo_inst/n537_s1 .INIT=4'h4;
+defparam \fifo_inst/n538_s1 .INIT=4'h4;
 LUT4 \fifo_inst/rempty_val_s3  (
-	.I0(\fifo_inst/Equal.rq2_wptr [1]),
-	.I1(\fifo_inst/rempty_val_8 ),
-	.I2(\fifo_inst/Equal.rq2_wptr [0]),
-	.I3(\fifo_inst/rbin_num_next [0]),
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.I3(\fifo_inst/rbin_num [1]),
 	.F(\fifo_inst/rempty_val )
 );
-defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h9009;
 LUT4 \fifo_inst/wfull_val_s3  (
 	.I0(\fifo_inst/wptr [0]),
 	.I1(\fifo_inst/wptr [1]),
@@ -133,8 +131,8 @@ LUT3 \fifo_inst/wfull_val1_s9  (
 );
 defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
 LUT3 \fifo_inst/wfull_val1_s10  (
-	.I0(\fifo_inst/wfull_val_7 ),
-	.I1(\fifo_inst/wfull_val1_0 ),
+	.I0(\fifo_inst/wfull_val1_0 ),
+	.I1(\fifo_inst/wfull_val_7 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/wfull_val1_0 )
 );
@@ -147,47 +145,48 @@ LUT3 \fifo_inst/Full_d_s  (
 );
 defparam \fifo_inst/Full_d_s .INIT=8'hAC;
 LUT3 \fifo_inst/Full_s8  (
-	.I0(\fifo_inst/wfull_val_7 ),
-	.I1(\fifo_inst/Full_1 ),
+	.I0(\fifo_inst/Full_1 ),
+	.I1(\fifo_inst/wfull_val_7 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/Full_1 )
 );
 defparam \fifo_inst/Full_s8 .INIT=8'h0E;
-LUT3 \fifo_inst/rbin_num_next_0_s5  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rbin_num_next [0])
-);
-defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
-LUT3 \fifo_inst/rbin_num_next_1_s2  (
-	.I0(\fifo_inst/rbin_num_next [0]),
-	.I1(\fifo_inst/rbin_num [0]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/rbin_num_next [1])
-);
-defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
 LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
-	.F(\fifo_inst/Equal.wbinnext_0_7 )
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wbinnext_0_8 )
 );
 defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
 LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wbinnext [1])
 );
 defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
-LUT4 \fifo_inst/rempty_val_s4  (
-	.I0(\fifo_inst/Equal.rq2_wptr [0]),
-	.I1(\fifo_inst/Equal.rq2_wptr [1]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.I3(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rempty_val_8 )
+LUT4 \fifo_inst/rbin_num_next_1_s3  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s3 .INIT=16'hBF40;
+LUT3 \fifo_inst/rbin_num_next_0_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next_0_10 )
+);
+defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
+LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
 );
-defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
+defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
 DFFP \fifo_inst/reset_r_0_s0  (
 	.D(GND),
 	.CLK(\fifo_inst/n4_6 ),
@@ -217,40 +216,12 @@ DFFC \fifo_inst/rbin_num_1_s0  (
 );
 defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/rbin_num_0_s0  (
-	.D(\fifo_inst/rbin_num_next [0]),
+	.D(\fifo_inst/rbin_num_next_0_10 ),
 	.CLK(RdClk),
 	.CLEAR(\fifo_inst/reset_r [1]),
 	.Q(\fifo_inst/rbin_num [0])
 );
 defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
-	.D(\fifo_inst/wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [1])
-);
-defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
-	.D(\fifo_inst/wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [0])
-);
-defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [1])
-);
-defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [0])
-);
-defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/rptr_0_s0  (
 	.D(\fifo_inst/Equal.rgraynext [0]),
 	.CLK(RdClk),
@@ -273,16 +244,23 @@ DFFC \fifo_inst/wptr_0_s0  (
 );
 defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/Equal.wbin_0_s0  (
-	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.D(\fifo_inst/Equal.wbinnext_0_8 ),
 	.CLK(WrClk),
 	.CLEAR(\fifo_inst/reset_w [1]),
 	.Q(\fifo_inst/Equal.wbin [0])
 );
 defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
-DFFP \fifo_inst/Empty_s0  (
+DFFP \fifo_inst/rempty_val1_s0  (
 	.D(\fifo_inst/rempty_val ),
 	.CLK(RdClk),
-	.PRESET(\fifo_inst/reset_r [1]),
+	.PRESET(\fifo_inst/n423_3 ),
+	.Q(\fifo_inst/rempty_val1 )
+);
+defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val1 ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n423_3 ),
 	.Q(Empty)
 );
 defparam \fifo_inst/Empty_s0 .INIT=1'b1;
@@ -303,7 +281,7 @@ defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
 	.D(\fifo_inst/wfull_val_7 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n537_4 ),
+	.PRESET(\fifo_inst/n538_4 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -317,7 +295,7 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n537_4 ),
+	.PRESET(\fifo_inst/n538_4 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
@@ -326,14 +304,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
 	.CEA(\fifo_inst/n20_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n26_4 ),
+	.CEB(\fifo_inst/n24_3 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({Data[31:0]}),
 	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND, GND, GND}),
 	.DO({Q[31:0]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
@@ -347,14 +325,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_1_s  (
 	.CEA(\fifo_inst/n20_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n26_4 ),
+	.CEB(\fifo_inst/n24_3 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({Data[63:32]}),
 	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND, GND, GND}),
 	.DO({Q[63:32]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .READ_MODE=1'b0;
@@ -368,14 +346,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_2_s  (
 	.CEA(\fifo_inst/n20_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n26_4 ),
+	.CEB(\fifo_inst/n24_3 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[79:64]}),
 	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND, GND, GND}),
 	.DO({\fifo_inst/DO [31:16], Q[79:64]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .READ_MODE=1'b0;

src/src/WrapFifoChain/FifoDDS/FifoDDS_tmp.v

@@ -1,10 +1,10 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.03 (64-bit)
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
-//Created Time: Tue May 28 15:49:41 2024
+//Created Time: Thu Jun 26 11:09:20 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FIFOHS.prj

@@ -4,17 +4,19 @@
     <Version>beta</Version>
     <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
     <FileList>
-        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
-        <File path="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
     </FileList>
     <OptionList>
         <Option type="disable_insert_pad" value="1"/>
-        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data"/>
         <Option type="include_path" value="C:/Gowin/Projects/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoDDS/temp/FIFOHS"/>
         <Option type="output_file" value="FifoDDS.vg"/>
         <Option type="output_template" value="FifoDDS_tmp.v"/>
         <Option type="ram_balance" value="1"/>
         <Option type="ram_rw_check" value="1"/>
+        <Option type="vcc" value="1.2"/>
+        <Option type="vccx" value="3.3"/>
         <Option type="verilog_language" value="sysv-2017"/>
     </OptionList>
 </Project>

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS.log

@@ -1,19 +1,28 @@
 GowinSynthesis start
 Running parser ...
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
-Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Back to file '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
-Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Analyzing included file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Back to file 'C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Compiling module 'FifoDDS'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
-Compiling module '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'Reset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'RPReset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoDDS'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 NOTE  (EX0101) : Current top module is "FifoDDS"
 [5%] Running netlist conversion ...
 Running device independent optimization ...
@@ -29,13 +38,13 @@ Running technical mapping ...
 [60%] Tech-Mapping Phase 0 completed
 [65%] Tech-Mapping Phase 1 completed
 [75%] Tech-Mapping Phase 2 completed
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.03_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
 [80%] Tech-Mapping Phase 3 completed
 [90%] Tech-Mapping Phase 4 completed

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS.vg

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.03 (64-bit)"
-//Tue May 28 15:49:41 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 11:09:20 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,156 +17,146 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
-HBNA+/9oSsy54/JlKoiN4gbbgk61v4S0vzu1SlxVV1FpSHLGFM3OwH9RYuOhFT+UXDcUiyGSTSim
-K+dcHv0CeFpV/YQWR5St8DdQGG+R45m6XWDErYGEafyEor0OduRaUiVP0XYqOL50oW/9d9x2NNiT
-ln6/o/IJCxIEaVblBTKR3tD4Ofb06tQw/6ZuEVhgWtapp5r+TlGiaQP6jx3uNfn+NBjuwyUzYkQ0
-MJjDVvgoM3zUdhRo+JtyCKggxSnoc2ym6iCL/mV/5ly8CtyjxhgYzms2pS3M3jxp5ii+uQ3L2s40
-krH8Dc9bcX5adde2FYFmhmRyz3sc5c38ia3cWA==
+h2Hk2PsTwq/dtAZ9cFVv1LIjE8XyjgauxqVI0H0KYFOYx3Oczh/IQEEmZNFaGIpF5+tpslMYL+Ka
++ZHdv2OmWeemN9OQUti1xK5PjD+tkvCGzpdHcDiZwF13UtlVVZAsEeOwAXH/+xl5iVD4XG1+sLw+
+0nK6e/8txanFzml+X3aHiYsP7g37sp/fbBNzYVGbvOdk5dBM9oFfusDzrd57y56OLNqQN8Xkw7X7
+YXRy46gZSPhUEew64wB1//OkcYXy/XR1SG8GKx0WW1dETf37zkyuWnWhtogDgOzFcnQjd4KWvyx8
+sPn/fYjDgkHcdGVe++mN41kzGiD37X68lMYU8Q==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=7872)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7312)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module FifoDDS (
   Data,

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS_syn_resource.html

@@ -30,8 +30,8 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 <th class="label">ROM16 NUMBER</th>
 </tr>
 <tr>
-<td class="label">FifoDDS (C:/Gowin/Gowin_V1.9.9.03_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
-<td align = "center">19</td>
+<td class="label">FifoDDS (C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">16</td>
 <td align = "center">-</td>
 <td align = "center">18</td>
 <td align = "center">-</td>

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="FifoDDS" Register="19" Lut="18" Bsram="3" T_Register="19(19)" T_Lut="18(18)" T_Bsram="3(3)"/>
+<Module name="FifoDDS" Register="16" Lut="18" Bsram="3" T_Register="16(16)" T_Lut="18(18)" T_Bsram="3(3)"/>

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/FifoDDS_tmp.v

@@ -1,10 +1,10 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.03 (64-bit)
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
 //Device: GW1N-9
-//Created Time: Tue May 28 15:49:41 2024
+//Created Time: Thu Jun 26 11:09:20 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------

src/src/WrapFifoChain/FifoDDS/temp/FIFOHS/fifo_define.v

@@ -1,5 +1,4 @@
 `define module_name FifoDDS
 `define EBR_BASED
-`define FWFT
 `define En_Reset
 `define Reset_Synchronization

src/src/WrapFifoChain/FifoLMX/FifoLMX.ipc

@@ -17,7 +17,7 @@ ECCSelected=false
 EmptyClear=1
 EmptySet=1
 EnReset=true
-FirstWordFallThrough=true
+FirstWordFallThrough=false
 FullClear=1
 FullSet=1
 LANG=0
@@ -28,7 +28,7 @@ ReadDataWidth=24
 ReadDepth=16
 ResetSynchronization=true
 SSRAM=false
-StandardFIFO=false
+StandardFIFO=true
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
 WriteDataWidth=24

src/src/WrapFifoChain/FifoLMX/FifoLMX.v

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:07:21 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 10:59:11 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,246 +17,225 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+vflXgIPlnA4Fz6U/GJBjaBy+jPW4yirAZG0Xmw==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=13040)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=11840)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module FifoLMX (
   Data,

src/src/WrapFifoChain/FifoLMX/FifoLMX.vo

@@ -1,8 +1,8 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
-//File Title: Post-PnR Simulation Model file
-//Tool Version: V1.9.9.02
-//Created Time: Thu Apr 25 16:07:21 2024
+//File Title: Post-PnR Verilog Simulation Model file
+//Tool Version: V1.9.11.02 (64-bit)
+//Created Time: Thu Jun 26 10:59:11 2025
 
 `timescale 100 ps/100 ps
 module FifoLMX(
@@ -37,46 +37,47 @@ wire VCC;
 wire WrClk;
 wire WrEn;
 wire \fifo_inst/n23_5 ;
-wire \fifo_inst/n29_4 ;
+wire \fifo_inst/n27_3 ;
 wire \fifo_inst/wfull_val ;
-wire \fifo_inst/n371_4 ;
+wire \fifo_inst/n277_3 ;
+wire \fifo_inst/n372_4 ;
 wire \fifo_inst/wfull_val1 ;
 wire \fifo_inst/wfull_val1_0 ;
 wire \fifo_inst/Full_1 ;
-wire \fifo_inst/Equal.wbinnext_0_7 ;
-wire \fifo_inst/Equal.rgraynext_1_4 ;
+wire \fifo_inst/Equal.wbinnext_0_8 ;
+wire \fifo_inst/Equal.rgraynext_2_4 ;
 wire \fifo_inst/Equal.wgraynext_1_4 ;
 wire \fifo_inst/Equal.wgraynext_2_4 ;
 wire \fifo_inst/Equal.wgraynext_3_4 ;
 wire \fifo_inst/wfull_val_4 ;
 wire \fifo_inst/wfull_val_5 ;
-wire \fifo_inst/n371_5 ;
+wire \fifo_inst/n372_5 ;
 wire \fifo_inst/wfull_val1_16 ;
 wire \fifo_inst/Full_11 ;
+wire \fifo_inst/rbin_num_next_0_10 ;
 wire \fifo_inst/rempty_val ;
+wire \fifo_inst/rempty_val1 ;
 wire \fifo_inst/wfull_val1_2 ;
 wire \fifo_inst/wfull_val1_3 ;
 wire \fifo_inst/Full_1_2 ;
 wire \fifo_inst/Full_2 ;
+wire \fifo_inst/n128_1_SUM ;
+wire \fifo_inst/n128_3 ;
+wire \fifo_inst/n129_1_SUM ;
+wire \fifo_inst/n129_3 ;
 wire \fifo_inst/n130_1_SUM ;
 wire \fifo_inst/n130_3 ;
 wire \fifo_inst/n131_1_SUM ;
 wire \fifo_inst/n131_3 ;
-wire \fifo_inst/n132_1_SUM ;
-wire \fifo_inst/n132_3 ;
-wire \fifo_inst/n133_1_SUM ;
-wire \fifo_inst/n133_3 ;
 wire \fifo_inst/n4_6 ;
 wire \fifo_inst/n9_6 ;
 wire [3:0] \fifo_inst/Equal.rgraynext ;
 wire [3:0] \fifo_inst/Equal.wgraynext ;
-wire [4:0] \fifo_inst/rbin_num_next ;
+wire [4:1] \fifo_inst/rbin_num_next ;
 wire [4:1] \fifo_inst/Equal.wbinnext ;
 wire [1:0] \fifo_inst/reset_r ;
 wire [1:0] \fifo_inst/reset_w ;
 wire [4:0] \fifo_inst/rbin_num ;
-wire [4:0] \fifo_inst/Equal.rq1_wptr ;
-wire [4:0] \fifo_inst/Equal.rq2_wptr ;
 wire [3:0] \fifo_inst/rptr ;
 wire [4:0] \fifo_inst/wptr ;
 wire [3:0] \fifo_inst/Equal.wbin ;
@@ -98,29 +99,29 @@ LUT4 \fifo_inst/n23_s1  (
 	.F(\fifo_inst/n23_5 )
 );
 defparam \fifo_inst/n23_s1 .INIT=16'h5300;
-LUT3 \fifo_inst/n29_s1  (
-	.I0(RdEn),
-	.I1(Empty),
-	.I2(\fifo_inst/rempty_val ),
-	.F(\fifo_inst/n29_4 )
-);
-defparam \fifo_inst/n29_s1 .INIT=8'h0E;
-LUT3 \fifo_inst/Equal.rgraynext_1_s0  (
-	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
-	.I1(\fifo_inst/rbin_num_next [1]),
-	.I2(\fifo_inst/rbin_num [2]),
+LUT2 \fifo_inst/n27_s0  (
+	.I0(Empty),
+	.I1(RdEn),
+	.F(\fifo_inst/n27_3 )
+);
+defparam \fifo_inst/n27_s0 .INIT=4'h4;
+LUT4 \fifo_inst/Equal.rgraynext_1_s0  (
+	.I0(\fifo_inst/n27_3 ),
+	.I1(\fifo_inst/rbin_num [0]),
+	.I2(\fifo_inst/rbin_num [1]),
+	.I3(\fifo_inst/rbin_num [2]),
 	.F(\fifo_inst/Equal.rgraynext [1])
 );
-defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=8'h1E;
+defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=16'h07F8;
 LUT3 \fifo_inst/Equal.rgraynext_2_s0  (
-	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
+	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
 	.I1(\fifo_inst/rbin_num [2]),
 	.I2(\fifo_inst/rbin_num [3]),
 	.F(\fifo_inst/Equal.rgraynext [2])
 );
 defparam \fifo_inst/Equal.rgraynext_2_s0 .INIT=8'h1E;
 LUT4 \fifo_inst/Equal.rgraynext_3_s0  (
-	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
+	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
 	.I1(\fifo_inst/rbin_num [2]),
 	.I2(\fifo_inst/rbin_num [3]),
 	.I3(\fifo_inst/rbin_num [4]),
@@ -166,13 +167,19 @@ LUT4 \fifo_inst/wfull_val_s0  (
 	.F(\fifo_inst/wfull_val )
 );
 defparam \fifo_inst/wfull_val_s0 .INIT=16'h6000;
-LUT3 \fifo_inst/n371_s1  (
+LUT2 \fifo_inst/n277_s0  (
+	.I0(\fifo_inst/rempty_val ),
+	.I1(\fifo_inst/reset_r [1]),
+	.F(\fifo_inst/n277_3 )
+);
+defparam \fifo_inst/n277_s0 .INIT=4'hE;
+LUT3 \fifo_inst/n372_s1  (
 	.I0(\fifo_inst/wfull_val_4 ),
 	.I1(\fifo_inst/wfull_val_5 ),
-	.I2(\fifo_inst/n371_5 ),
-	.F(\fifo_inst/n371_4 )
+	.I2(\fifo_inst/n372_5 ),
+	.F(\fifo_inst/n372_4 )
 );
-defparam \fifo_inst/n371_s1 .INIT=8'h80;
+defparam \fifo_inst/n372_s1 .INIT=8'h80;
 LUT3 \fifo_inst/wfull_val1_s9  (
 	.I0(\fifo_inst/wfull_val1_3 ),
 	.I1(\fifo_inst/wfull_val1_2 ),
@@ -182,7 +189,7 @@ LUT3 \fifo_inst/wfull_val1_s9  (
 defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
 LUT4 \fifo_inst/wfull_val1_s10  (
 	.I0(\fifo_inst/wfull_val_5 ),
-	.I1(\fifo_inst/n371_5 ),
+	.I1(\fifo_inst/n372_5 ),
 	.I2(\fifo_inst/wfull_val_4 ),
 	.I3(\fifo_inst/wfull_val1_16 ),
 	.F(\fifo_inst/wfull_val1_0 )
@@ -197,42 +204,27 @@ LUT3 \fifo_inst/Full_d_s  (
 defparam \fifo_inst/Full_d_s .INIT=8'hAC;
 LUT4 \fifo_inst/Full_s8  (
 	.I0(\fifo_inst/wfull_val_5 ),
-	.I1(\fifo_inst/n371_5 ),
+	.I1(\fifo_inst/n372_5 ),
 	.I2(\fifo_inst/wfull_val_4 ),
 	.I3(\fifo_inst/Full_11 ),
 	.F(\fifo_inst/Full_1 )
 );
 defparam \fifo_inst/Full_s8 .INIT=16'hFF80;
-LUT3 \fifo_inst/rbin_num_next_0_s5  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rbin_num_next [0])
-);
-defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
-LUT4 \fifo_inst/rbin_num_next_1_s5  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.I3(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/rbin_num_next [1])
-);
-defparam \fifo_inst/rbin_num_next_1_s5 .INIT=16'hBF40;
-LUT2 \fifo_inst/rbin_num_next_2_s5  (
-	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
+LUT2 \fifo_inst/rbin_num_next_2_s3  (
+	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
 	.I1(\fifo_inst/rbin_num [2]),
 	.F(\fifo_inst/rbin_num_next [2])
 );
-defparam \fifo_inst/rbin_num_next_2_s5 .INIT=4'h6;
-LUT3 \fifo_inst/rbin_num_next_3_s5  (
-	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
+defparam \fifo_inst/rbin_num_next_2_s3 .INIT=4'h6;
+LUT3 \fifo_inst/rbin_num_next_3_s3  (
+	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
 	.I1(\fifo_inst/rbin_num [2]),
 	.I2(\fifo_inst/rbin_num [3]),
 	.F(\fifo_inst/rbin_num_next [3])
 );
-defparam \fifo_inst/rbin_num_next_3_s5 .INIT=8'h78;
+defparam \fifo_inst/rbin_num_next_3_s3 .INIT=8'h78;
 LUT4 \fifo_inst/rbin_num_next_4_s2  (
-	.I0(\fifo_inst/Equal.rgraynext_1_4 ),
+	.I0(\fifo_inst/Equal.rgraynext_2_4 ),
 	.I1(\fifo_inst/rbin_num [2]),
 	.I2(\fifo_inst/rbin_num [3]),
 	.I3(\fifo_inst/rbin_num [4]),
@@ -242,7 +234,7 @@ defparam \fifo_inst/rbin_num_next_4_s2 .INIT=16'h7F80;
 LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
 	.I0(\fifo_inst/n23_5 ),
 	.I1(\fifo_inst/Equal.wbin [0]),
-	.F(\fifo_inst/Equal.wbinnext_0_7 )
+	.F(\fifo_inst/Equal.wbinnext_0_8 )
 );
 defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
 LUT3 \fifo_inst/Equal.wbinnext_2_s3  (
@@ -267,14 +259,14 @@ LUT4 \fifo_inst/Equal.wbinnext_4_s2  (
 	.F(\fifo_inst/Equal.wbinnext [4])
 );
 defparam \fifo_inst/Equal.wbinnext_4_s2 .INIT=16'hBF40;
-LUT4 \fifo_inst/Equal.rgraynext_1_s1  (
+LUT4 \fifo_inst/Equal.rgraynext_2_s1  (
 	.I0(Empty),
 	.I1(RdEn),
 	.I2(\fifo_inst/rbin_num [0]),
 	.I3(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/Equal.rgraynext_1_4 )
+	.F(\fifo_inst/Equal.rgraynext_2_4 )
 );
-defparam \fifo_inst/Equal.rgraynext_1_s1 .INIT=16'h4000;
+defparam \fifo_inst/Equal.rgraynext_2_s1 .INIT=16'h4000;
 LUT2 \fifo_inst/Equal.wgraynext_1_s1  (
 	.I0(WrEn),
 	.I1(\fifo_inst/Equal.wbin [0]),
@@ -312,13 +304,13 @@ LUT4 \fifo_inst/wfull_val_s2  (
 	.F(\fifo_inst/wfull_val_5 )
 );
 defparam \fifo_inst/wfull_val_s2 .INIT=16'h0990;
-LUT3 \fifo_inst/n371_s2  (
+LUT3 \fifo_inst/n372_s2  (
 	.I0(\fifo_inst/reset_w [1]),
 	.I1(\fifo_inst/wptr [4]),
 	.I2(\fifo_inst/rbin_num [4]),
-	.F(\fifo_inst/n371_5 )
+	.F(\fifo_inst/n372_5 )
 );
-defparam \fifo_inst/n371_s2 .INIT=8'h14;
+defparam \fifo_inst/n372_s2 .INIT=8'h14;
 LUT2 \fifo_inst/wfull_val1_s11  (
 	.I0(\fifo_inst/reset_w [1]),
 	.I1(\fifo_inst/wfull_val1_0 ),
@@ -339,21 +331,36 @@ LUT4 \fifo_inst/Equal.wbinnext_1_s4  (
 	.F(\fifo_inst/Equal.wbinnext [1])
 );
 defparam \fifo_inst/Equal.wbinnext_1_s4 .INIT=16'hBF40;
+LUT4 \fifo_inst/rbin_num_next_1_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s4 .INIT=16'hBF40;
+LUT3 \fifo_inst/rbin_num_next_0_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next_0_10 )
+);
+defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
 LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
 	.I0(Empty),
 	.I1(RdEn),
 	.I2(\fifo_inst/rbin_num [0]),
-	.I3(\fifo_inst/rbin_num_next [1]),
+	.I3(\fifo_inst/rbin_num [1]),
 	.F(\fifo_inst/Equal.rgraynext [0])
 );
-defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h4BB4;
+defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
 LUT3 \fifo_inst/rempty_val_s2  (
-	.I0(\fifo_inst/rbin_num_next [4]),
-	.I1(\fifo_inst/Equal.rq2_wptr [4]),
-	.I2(\fifo_inst/n133_3 ),
+	.I0(\fifo_inst/n131_3 ),
+	.I1(\fifo_inst/rbin_num [4]),
+	.I2(\fifo_inst/wptr [4]),
 	.F(\fifo_inst/rempty_val )
 );
-defparam \fifo_inst/rempty_val_s2 .INIT=8'h09;
+defparam \fifo_inst/rempty_val_s2 .INIT=8'h41;
 DFFP \fifo_inst/reset_r_0_s0  (
 	.D(GND),
 	.CLK(\fifo_inst/n4_6 ),
@@ -404,82 +411,12 @@ DFFC \fifo_inst/rbin_num_1_s0  (
 );
 defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/rbin_num_0_s0  (
-	.D(\fifo_inst/rbin_num_next [0]),
+	.D(\fifo_inst/rbin_num_next_0_10 ),
 	.CLK(RdClk),
 	.CLEAR(\fifo_inst/reset_r [1]),
 	.Q(\fifo_inst/rbin_num [0])
 );
 defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_4_s0  (
-	.D(\fifo_inst/wptr [4]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [4])
-);
-defparam \fifo_inst/Equal.rq1_wptr_4_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_3_s0  (
-	.D(\fifo_inst/wptr [3]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [3])
-);
-defparam \fifo_inst/Equal.rq1_wptr_3_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_2_s0  (
-	.D(\fifo_inst/wptr [2]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [2])
-);
-defparam \fifo_inst/Equal.rq1_wptr_2_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
-	.D(\fifo_inst/wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [1])
-);
-defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
-	.D(\fifo_inst/wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [0])
-);
-defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_4_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [4]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [4])
-);
-defparam \fifo_inst/Equal.rq2_wptr_4_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_3_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [3]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [3])
-);
-defparam \fifo_inst/Equal.rq2_wptr_3_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_2_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [2]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [2])
-);
-defparam \fifo_inst/Equal.rq2_wptr_2_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [1])
-);
-defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [0])
-);
-defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/rptr_3_s0  (
 	.D(\fifo_inst/Equal.rgraynext [3]),
 	.CLK(RdClk),
@@ -565,16 +502,23 @@ DFFC \fifo_inst/Equal.wbin_1_s0  (
 );
 defparam \fifo_inst/Equal.wbin_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/Equal.wbin_0_s0  (
-	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.D(\fifo_inst/Equal.wbinnext_0_8 ),
 	.CLK(WrClk),
 	.CLEAR(\fifo_inst/reset_w [1]),
 	.Q(\fifo_inst/Equal.wbin [0])
 );
 defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
-DFFP \fifo_inst/Empty_s0  (
+DFFP \fifo_inst/rempty_val1_s0  (
 	.D(\fifo_inst/rempty_val ),
 	.CLK(RdClk),
-	.PRESET(\fifo_inst/reset_r [1]),
+	.PRESET(\fifo_inst/n277_3 ),
+	.Q(\fifo_inst/rempty_val1 )
+);
+defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val1 ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n277_3 ),
 	.Q(Empty)
 );
 defparam \fifo_inst/Empty_s0 .INIT=1'b1;
@@ -595,7 +539,7 @@ defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
 	.D(\fifo_inst/wfull_val ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n371_4 ),
+	.PRESET(\fifo_inst/n372_4 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -609,7 +553,7 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n371_4 ),
+	.PRESET(\fifo_inst/n372_4 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
@@ -618,14 +562,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
 	.CEA(\fifo_inst/n23_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n29_4 ),
+	.CEB(\fifo_inst/n27_3 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({GND, GND, GND, GND, GND, GND, GND, GND, Data[23:0]}),
 	.ADA({GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [3:0], GND, VCC, VCC, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [3:0], GND, GND, GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, \fifo_inst/rbin_num [3:0], GND, GND, GND, GND, GND}),
 	.DO({\fifo_inst/DO [31:24], Q[23:0]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
@@ -634,42 +578,42 @@ defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=32;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
-ALU \fifo_inst/n130_s0  (
-	.I0(\fifo_inst/Equal.rgraynext [0]),
-	.I1(\fifo_inst/Equal.rq2_wptr [0]),
+ALU \fifo_inst/n128_s0  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
 	.I3(GND),
 	.CIN(GND),
+	.COUT(\fifo_inst/n128_3 ),
+	.SUM(\fifo_inst/n128_1_SUM )
+);
+defparam \fifo_inst/n128_s0 .ALU_MODE=3;
+ALU \fifo_inst/n129_s0  (
+	.I0(\fifo_inst/wptr [1]),
+	.I1(\fifo_inst/rptr [1]),
+	.I3(GND),
+	.CIN(\fifo_inst/n128_3 ),
+	.COUT(\fifo_inst/n129_3 ),
+	.SUM(\fifo_inst/n129_1_SUM )
+);
+defparam \fifo_inst/n129_s0 .ALU_MODE=3;
+ALU \fifo_inst/n130_s0  (
+	.I0(\fifo_inst/wptr [2]),
+	.I1(\fifo_inst/rptr [2]),
+	.I3(GND),
+	.CIN(\fifo_inst/n129_3 ),
 	.COUT(\fifo_inst/n130_3 ),
 	.SUM(\fifo_inst/n130_1_SUM )
 );
 defparam \fifo_inst/n130_s0 .ALU_MODE=3;
 ALU \fifo_inst/n131_s0  (
-	.I0(\fifo_inst/Equal.rgraynext [1]),
-	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+	.I0(\fifo_inst/wptr [3]),
+	.I1(\fifo_inst/rptr [3]),
 	.I3(GND),
 	.CIN(\fifo_inst/n130_3 ),
 	.COUT(\fifo_inst/n131_3 ),
 	.SUM(\fifo_inst/n131_1_SUM )
 );
 defparam \fifo_inst/n131_s0 .ALU_MODE=3;
-ALU \fifo_inst/n132_s0  (
-	.I0(\fifo_inst/Equal.rgraynext [2]),
-	.I1(\fifo_inst/Equal.rq2_wptr [2]),
-	.I3(GND),
-	.CIN(\fifo_inst/n131_3 ),
-	.COUT(\fifo_inst/n132_3 ),
-	.SUM(\fifo_inst/n132_1_SUM )
-);
-defparam \fifo_inst/n132_s0 .ALU_MODE=3;
-ALU \fifo_inst/n133_s0  (
-	.I0(\fifo_inst/Equal.rgraynext [3]),
-	.I1(\fifo_inst/Equal.rq2_wptr [3]),
-	.I3(GND),
-	.CIN(\fifo_inst/n132_3 ),
-	.COUT(\fifo_inst/n133_3 ),
-	.SUM(\fifo_inst/n133_1_SUM )
-);
-defparam \fifo_inst/n133_s0 .ALU_MODE=3;
 INV \fifo_inst/n4_s2  (
 	.I(RdClk),
 	.O(\fifo_inst/n4_6 )

src/src/WrapFifoChain/FifoLMX/FifoLMX_tmp.v

@@ -1,24 +1,24 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:07:21 2024
+//Device: GW1N-9
+//Created Time: Thu Jun 26 10:59:11 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	FifoLMX your_instance_name(
-		.Data(Data_i), //input [23:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [23:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [23:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [23:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FIFOHS.prj

@@ -4,17 +4,19 @@
     <Version>beta</Version>
     <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
     <FileList>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
     </FileList>
     <OptionList>
         <Option type="disable_insert_pad" value="1"/>
-        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
-        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/FifoLMX/temp/FIFOHS"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Gowin/Projects/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoLMX/temp/FIFOHS"/>
         <Option type="output_file" value="FifoLMX.vg"/>
         <Option type="output_template" value="FifoLMX_tmp.v"/>
         <Option type="ram_balance" value="1"/>
         <Option type="ram_rw_check" value="1"/>
+        <Option type="vcc" value="1.2"/>
+        <Option type="vccx" value="3.3"/>
         <Option type="verilog_language" value="sysv-2017"/>
     </OptionList>
 </Project>

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FifoLMX.log

@@ -1,19 +1,28 @@
 GowinSynthesis start
 Running parser ...
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
-Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
-Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Compiling module 'FifoLMX'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
-Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'Reset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'RPReset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoLMX'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 NOTE  (EX0101) : Current top module is "FifoLMX"
 [5%] Running netlist conversion ...
 Running device independent optimization ...
@@ -29,17 +38,17 @@ Running technical mapping ...
 [60%] Tech-Mapping Phase 0 completed
 [65%] Tech-Mapping Phase 1 completed
 [75%] Tech-Mapping Phase 2 completed
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
 [80%] Tech-Mapping Phase 3 completed
 [90%] Tech-Mapping Phase 4 completed
-[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoLMX\temp\FIFOHS\FifoLMX.vg" completed
-Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoLMX\temp\FIFOHS\FifoLMX_tmp.v" completed
-[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoLMX\temp\FIFOHS\FifoLMX_syn.rpt.html" completed
+[95%] Generate netlist file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoLMX\temp\FIFOHS\FifoLMX.vg" completed
+Generate template file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoLMX\temp\FIFOHS\FifoLMX_tmp.v" completed
+[100%] Generate report file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoLMX\temp\FIFOHS\FifoLMX_syn.rpt.html" completed
 GowinSynthesis finish

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FifoLMX.vg

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:07:21 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 10:59:11 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,246 +17,225 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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-Eeo9r6zKZBCzzoX/vEjCCVRH/vbTUoQQ9buY6g==
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+vflXgIPlnA4Fz6U/GJBjaBy+jPW4yirAZG0Xmw==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=13040)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=11840)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module FifoLMX (
   Data,

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FifoLMX_syn_resource.html

@@ -30,10 +30,10 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 <th class="label">ROM16 NUMBER</th>
 </tr>
 <tr>
-<td class="label">FifoLMX (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
-<td align = "center">37</td>
+<td class="label">FifoLMX (C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">28</td>
 <td align = "center">4</td>
-<td align = "center">38</td>
+<td align = "center">39</td>
 <td align = "center">-</td>
 <td align = "center">1</td>
 <td align = "center">-</td>

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FifoLMX_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="FifoLMX" Register="37" Alu="4" Lut="38" Bsram="1" T_Register="37(37)" T_Alu="4(4)" T_Lut="38(38)" T_Bsram="1(1)"/>
+<Module name="FifoLMX" Register="28" Alu="4" Lut="39" Bsram="1" T_Register="28(28)" T_Alu="4(4)" T_Lut="39(39)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/FifoLMX_tmp.v

@@ -1,24 +1,24 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:07:21 2024
+//Device: GW1N-9
+//Created Time: Thu Jun 26 10:59:11 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	FifoLMX your_instance_name(
-		.Data(Data_i), //input [23:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [23:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [23:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [23:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/FifoLMX/temp/FIFOHS/fifo_define.v

@@ -1,5 +1,4 @@
 `define module_name FifoLMX
 `define EBR_BASED
-`define FWFT
 `define En_Reset
 `define Reset_Synchronization

src/src/WrapFifoChain/FifoMax2870/FifoMax2870.ipc

@@ -17,7 +17,7 @@ ECCSelected=false
 EmptyClear=1
 EmptySet=1
 EnReset=true
-FirstWordFallThrough=true
+FirstWordFallThrough=false
 FullClear=1
 FullSet=1
 LANG=0
@@ -28,7 +28,7 @@ ReadDataWidth=32
 ReadDepth=4
 ResetSynchronization=true
 SSRAM=false
-StandardFIFO=false
+StandardFIFO=true
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
 WriteDataWidth=32

src/src/WrapFifoChain/FifoMax2870/FifoMax2870.v

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:07:36 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 11:10:16 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,164 +17,156 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+8ygXDzlmPp+ZRlqJdLYAUkCus73410L9DCj0mg==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=8352)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7904)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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+GqFWL9qdj1U/Iysta7gKHNXNVJgzYw/XloyTS0QxCtmMnsOkYo4pgARi8BlngDQcC/Z3AHxBfOE3
+xLuu/lweV7XGyO/OognCnhWN8HFUCWPttL7B4MmNEjBulfZl4gKEpHyt73o1iXUbnyraZybCuc5/
+H4bFA4I7rrHJbfyTnnLDx6kdU5AU9bPhHWXnAKXjHCUYAz9jEkrIJ9orsjSAhVustJJ4BdakfNEo
+srFllOh2lQYXoauOXoNfPRodxB0+d24jgjTD9PJW8OAE5vfKpRjtnDyFMmnTuztirwxR26mnWhDL
+uYWRqA3cSOT79bkRo6KC0rZjGHzCZe76ldAV/WRNgor69Sn5kp2CDoqb0RGoXl832YizDp9cccXs
+zG7Z44wP2cunpJrUuU2Dg8wdKK77t8k7ph7kQovaXhsaz6S6uSGLD2gF1YygCuy5vs8p+eFgn6Lr
+llhZqyOZ/VFPO1hR3VyLHTKdCSpealYt36LeyslIUreVduWuUQl4+3QplmgZTS18/Nztb3n/OYF0
+Vc/J+q+badQoqq6ZWk5+cEVjCBcM/FvVq9Wyt+g8/pG7Chnt+Zs=
 `pragma protect end_protected
 module FifoMax2870 (
   Data,

src/src/WrapFifoChain/FifoMax2870/FifoMax2870.vo

@@ -1,8 +1,8 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
-//File Title: Post-PnR Simulation Model file
-//Tool Version: V1.9.9.02
-//Created Time: Thu Apr 25 16:07:36 2024
+//File Title: Post-PnR Verilog Simulation Model file
+//Tool Version: V1.9.11.02 (64-bit)
+//Created Time: Thu Jun 26 11:10:16 2025
 
 `timescale 100 ps/100 ps
 module FifoMax2870(
@@ -37,35 +37,37 @@ wire VCC;
 wire WrClk;
 wire WrEn;
 wire \fifo_inst/n21_5 ;
-wire \fifo_inst/n27_4 ;
+wire \fifo_inst/n25_3 ;
+wire \fifo_inst/n257_3 ;
 wire \fifo_inst/wfull_val1 ;
 wire \fifo_inst/wfull_val1_0 ;
 wire \fifo_inst/Full_1 ;
-wire \fifo_inst/Equal.wbinnext_0_7 ;
+wire \fifo_inst/Equal.wbinnext_0_8 ;
+wire \fifo_inst/Equal.wgraynext_1_4 ;
 wire \fifo_inst/wfull_val_4 ;
 wire \fifo_inst/wfull_val_5 ;
-wire \fifo_inst/n335_6 ;
+wire \fifo_inst/n336_6 ;
 wire \fifo_inst/wfull_val ;
+wire \fifo_inst/rbin_num_next_0_10 ;
 wire \fifo_inst/rempty_val ;
+wire \fifo_inst/rempty_val1 ;
 wire \fifo_inst/wfull_val1_2 ;
 wire \fifo_inst/wfull_val1_3 ;
 wire \fifo_inst/Full_1_2 ;
 wire \fifo_inst/Full_2 ;
-wire \fifo_inst/n158_1_SUM ;
-wire \fifo_inst/n158_3 ;
-wire \fifo_inst/n159_1_SUM ;
-wire \fifo_inst/n159_3 ;
+wire \fifo_inst/n156_1_SUM ;
+wire \fifo_inst/n156_3 ;
+wire \fifo_inst/n157_1_SUM ;
+wire \fifo_inst/n157_3 ;
 wire \fifo_inst/n4_6 ;
 wire \fifo_inst/n9_6 ;
 wire [1:0] \fifo_inst/Equal.rgraynext ;
 wire [1:0] \fifo_inst/Equal.wgraynext ;
-wire [2:0] \fifo_inst/rbin_num_next ;
+wire [2:1] \fifo_inst/rbin_num_next ;
 wire [2:1] \fifo_inst/Equal.wbinnext ;
 wire [1:0] \fifo_inst/reset_r ;
 wire [1:0] \fifo_inst/reset_w ;
 wire [2:0] \fifo_inst/rbin_num ;
-wire [2:0] \fifo_inst/Equal.rq1_wptr ;
-wire [2:0] \fifo_inst/Equal.rq2_wptr ;
 wire [1:0] \fifo_inst/rptr ;
 wire [2:0] \fifo_inst/wptr ;
 wire [1:0] \fifo_inst/Equal.wbin ;
@@ -86,28 +88,20 @@ LUT4 \fifo_inst/n21_s1  (
 	.F(\fifo_inst/n21_5 )
 );
 defparam \fifo_inst/n21_s1 .INIT=16'h5300;
-LUT3 \fifo_inst/n27_s1  (
-	.I0(RdEn),
-	.I1(Empty),
-	.I2(\fifo_inst/rempty_val ),
-	.F(\fifo_inst/n27_4 )
-);
-defparam \fifo_inst/n27_s1 .INIT=8'h0E;
-LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
-	.I0(\fifo_inst/rbin_num_next [0]),
-	.I1(\fifo_inst/rbin_num [0]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/Equal.rgraynext [0])
+LUT2 \fifo_inst/n25_s0  (
+	.I0(Empty),
+	.I1(RdEn),
+	.F(\fifo_inst/n25_3 )
 );
-defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+defparam \fifo_inst/n25_s0 .INIT=4'h4;
 LUT4 \fifo_inst/Equal.rgraynext_1_s0  (
-	.I0(\fifo_inst/rbin_num_next [0]),
+	.I0(\fifo_inst/n25_3 ),
 	.I1(\fifo_inst/rbin_num [0]),
 	.I2(\fifo_inst/rbin_num [1]),
 	.I3(\fifo_inst/rbin_num [2]),
 	.F(\fifo_inst/Equal.rgraynext [1])
 );
-defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=16'h0BF4;
+defparam \fifo_inst/Equal.rgraynext_1_s0 .INIT=16'h07F8;
 LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
 	.I0(\fifo_inst/n21_5 ),
 	.I1(\fifo_inst/Equal.wbin [0]),
@@ -116,13 +110,19 @@ LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
 );
 defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
 LUT4 \fifo_inst/Equal.wgraynext_1_s0  (
-	.I0(\fifo_inst/n21_5 ),
-	.I1(\fifo_inst/Equal.wbin [0]),
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_1_4 ),
 	.I2(\fifo_inst/Equal.wbin [1]),
 	.I3(\fifo_inst/wptr [2]),
 	.F(\fifo_inst/Equal.wgraynext [1])
 );
-defparam \fifo_inst/Equal.wgraynext_1_s0 .INIT=16'h07F8;
+defparam \fifo_inst/Equal.wgraynext_1_s0 .INIT=16'h0BF4;
+LUT2 \fifo_inst/n257_s0  (
+	.I0(\fifo_inst/rempty_val ),
+	.I1(\fifo_inst/reset_r [1]),
+	.F(\fifo_inst/n257_3 )
+);
+defparam \fifo_inst/n257_s0 .INIT=4'hE;
 LUT3 \fifo_inst/wfull_val1_s9  (
 	.I0(\fifo_inst/wfull_val1_3 ),
 	.I1(\fifo_inst/wfull_val1_2 ),
@@ -153,49 +153,34 @@ LUT4 \fifo_inst/Full_s8  (
 	.F(\fifo_inst/Full_1 )
 );
 defparam \fifo_inst/Full_s8 .INIT=16'h00F8;
-LUT3 \fifo_inst/rbin_num_next_0_s5  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rbin_num_next [0])
-);
-defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
-LUT3 \fifo_inst/rbin_num_next_1_s5  (
-	.I0(\fifo_inst/rbin_num_next [0]),
-	.I1(\fifo_inst/rbin_num [0]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/rbin_num_next [1])
-);
-defparam \fifo_inst/rbin_num_next_1_s5 .INIT=8'hB4;
 LUT4 \fifo_inst/rbin_num_next_2_s2  (
-	.I0(\fifo_inst/rbin_num_next [0]),
+	.I0(\fifo_inst/n25_3 ),
 	.I1(\fifo_inst/rbin_num [0]),
 	.I2(\fifo_inst/rbin_num [1]),
 	.I3(\fifo_inst/rbin_num [2]),
 	.F(\fifo_inst/rbin_num_next [2])
 );
-defparam \fifo_inst/rbin_num_next_2_s2 .INIT=16'hBF40;
+defparam \fifo_inst/rbin_num_next_2_s2 .INIT=16'h7F80;
 LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
 	.I0(\fifo_inst/n21_5 ),
 	.I1(\fifo_inst/Equal.wbin [0]),
-	.F(\fifo_inst/Equal.wbinnext_0_7 )
+	.F(\fifo_inst/Equal.wbinnext_0_8 )
 );
 defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
-LUT3 \fifo_inst/Equal.wbinnext_1_s3  (
-	.I0(\fifo_inst/n21_5 ),
-	.I1(\fifo_inst/Equal.wbin [0]),
-	.I2(\fifo_inst/Equal.wbin [1]),
-	.F(\fifo_inst/Equal.wbinnext [1])
-);
-defparam \fifo_inst/Equal.wbinnext_1_s3 .INIT=8'h78;
 LUT4 \fifo_inst/Equal.wbinnext_2_s2  (
-	.I0(\fifo_inst/n21_5 ),
-	.I1(\fifo_inst/Equal.wbin [0]),
+	.I0(Full),
+	.I1(\fifo_inst/Equal.wgraynext_1_4 ),
 	.I2(\fifo_inst/Equal.wbin [1]),
 	.I3(\fifo_inst/wptr [2]),
 	.F(\fifo_inst/Equal.wbinnext [2])
 );
-defparam \fifo_inst/Equal.wbinnext_2_s2 .INIT=16'h7F80;
+defparam \fifo_inst/Equal.wbinnext_2_s2 .INIT=16'hBF40;
+LUT2 \fifo_inst/Equal.wgraynext_1_s1  (
+	.I0(WrEn),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wgraynext_1_4 )
+);
+defparam \fifo_inst/Equal.wgraynext_1_s1 .INIT=4'h8;
 LUT2 \fifo_inst/wfull_val_s1  (
 	.I0(\fifo_inst/wptr [2]),
 	.I1(\fifo_inst/rbin_num [2]),
@@ -210,14 +195,22 @@ LUT4 \fifo_inst/wfull_val_s2  (
 	.F(\fifo_inst/wfull_val_5 )
 );
 defparam \fifo_inst/wfull_val_s2 .INIT=16'h0990;
-LUT4 \fifo_inst/n335_s2  (
+LUT4 \fifo_inst/Equal.wbinnext_1_s4  (
+	.I0(Full),
+	.I1(WrEn),
+	.I2(\fifo_inst/Equal.wbin [0]),
+	.I3(\fifo_inst/Equal.wbin [1]),
+	.F(\fifo_inst/Equal.wbinnext [1])
+);
+defparam \fifo_inst/Equal.wbinnext_1_s4 .INIT=16'hBF40;
+LUT4 \fifo_inst/n336_s2  (
 	.I0(\fifo_inst/wptr [2]),
 	.I1(\fifo_inst/rbin_num [2]),
 	.I2(\fifo_inst/reset_w [1]),
 	.I3(\fifo_inst/wfull_val_5 ),
-	.F(\fifo_inst/n335_6 )
+	.F(\fifo_inst/n336_6 )
 );
-defparam \fifo_inst/n335_s2 .INIT=16'h0600;
+defparam \fifo_inst/n336_s2 .INIT=16'h0600;
 LUT3 \fifo_inst/wfull_val_s3  (
 	.I0(\fifo_inst/wptr [2]),
 	.I1(\fifo_inst/rbin_num [2]),
@@ -225,13 +218,36 @@ LUT3 \fifo_inst/wfull_val_s3  (
 	.F(\fifo_inst/wfull_val )
 );
 defparam \fifo_inst/wfull_val_s3 .INIT=8'h60;
+LUT4 \fifo_inst/rbin_num_next_1_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s4 .INIT=16'hBF40;
+LUT3 \fifo_inst/rbin_num_next_0_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next_0_10 )
+);
+defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
+LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
+);
+defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
 LUT3 \fifo_inst/rempty_val_s2  (
-	.I0(\fifo_inst/rbin_num_next [2]),
-	.I1(\fifo_inst/Equal.rq2_wptr [2]),
-	.I2(\fifo_inst/n159_3 ),
+	.I0(\fifo_inst/n157_3 ),
+	.I1(\fifo_inst/rbin_num [2]),
+	.I2(\fifo_inst/wptr [2]),
 	.F(\fifo_inst/rempty_val )
 );
-defparam \fifo_inst/rempty_val_s2 .INIT=8'h09;
+defparam \fifo_inst/rempty_val_s2 .INIT=8'h41;
 DFFP \fifo_inst/reset_r_0_s0  (
 	.D(GND),
 	.CLK(\fifo_inst/n4_6 ),
@@ -268,54 +284,12 @@ DFFC \fifo_inst/rbin_num_1_s0  (
 );
 defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/rbin_num_0_s0  (
-	.D(\fifo_inst/rbin_num_next [0]),
+	.D(\fifo_inst/rbin_num_next_0_10 ),
 	.CLK(RdClk),
 	.CLEAR(\fifo_inst/reset_r [1]),
 	.Q(\fifo_inst/rbin_num [0])
 );
 defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_2_s0  (
-	.D(\fifo_inst/wptr [2]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [2])
-);
-defparam \fifo_inst/Equal.rq1_wptr_2_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
-	.D(\fifo_inst/wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [1])
-);
-defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
-	.D(\fifo_inst/wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [0])
-);
-defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_2_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [2]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [2])
-);
-defparam \fifo_inst/Equal.rq2_wptr_2_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [1])
-);
-defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [0])
-);
-defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/rptr_1_s0  (
 	.D(\fifo_inst/Equal.rgraynext [1]),
 	.CLK(RdClk),
@@ -359,16 +333,23 @@ DFFC \fifo_inst/Equal.wbin_1_s0  (
 );
 defparam \fifo_inst/Equal.wbin_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/Equal.wbin_0_s0  (
-	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.D(\fifo_inst/Equal.wbinnext_0_8 ),
 	.CLK(WrClk),
 	.CLEAR(\fifo_inst/reset_w [1]),
 	.Q(\fifo_inst/Equal.wbin [0])
 );
 defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
-DFFP \fifo_inst/Empty_s0  (
+DFFP \fifo_inst/rempty_val1_s0  (
 	.D(\fifo_inst/rempty_val ),
 	.CLK(RdClk),
-	.PRESET(\fifo_inst/reset_r [1]),
+	.PRESET(\fifo_inst/n257_3 ),
+	.Q(\fifo_inst/rempty_val1 )
+);
+defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val1 ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n257_3 ),
 	.Q(Empty)
 );
 defparam \fifo_inst/Empty_s0 .INIT=1'b1;
@@ -389,7 +370,7 @@ defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
 	.D(\fifo_inst/wfull_val ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n335_6 ),
+	.PRESET(\fifo_inst/n336_6 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -403,7 +384,7 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n335_6 ),
+	.PRESET(\fifo_inst/n336_6 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
@@ -412,14 +393,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
 	.CEA(\fifo_inst/n21_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n27_4 ),
+	.CEB(\fifo_inst/n25_3 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({Data[31:0]}),
 	.ADA({GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [1:0], GND, VCC, VCC, VCC, VCC}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [1:0], GND, GND, GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [1:0], GND, GND, GND, GND, GND}),
 	.DO({Q[31:0]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
@@ -428,24 +409,24 @@ defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=32;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
-ALU \fifo_inst/n158_s0  (
-	.I0(\fifo_inst/Equal.rgraynext [0]),
-	.I1(\fifo_inst/Equal.rq2_wptr [0]),
+ALU \fifo_inst/n156_s0  (
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
 	.I3(GND),
 	.CIN(GND),
-	.COUT(\fifo_inst/n158_3 ),
-	.SUM(\fifo_inst/n158_1_SUM )
+	.COUT(\fifo_inst/n156_3 ),
+	.SUM(\fifo_inst/n156_1_SUM )
 );
-defparam \fifo_inst/n158_s0 .ALU_MODE=3;
-ALU \fifo_inst/n159_s0  (
-	.I0(\fifo_inst/Equal.rgraynext [1]),
-	.I1(\fifo_inst/Equal.rq2_wptr [1]),
+defparam \fifo_inst/n156_s0 .ALU_MODE=3;
+ALU \fifo_inst/n157_s0  (
+	.I0(\fifo_inst/wptr [1]),
+	.I1(\fifo_inst/rptr [1]),
 	.I3(GND),
-	.CIN(\fifo_inst/n158_3 ),
-	.COUT(\fifo_inst/n159_3 ),
-	.SUM(\fifo_inst/n159_1_SUM )
+	.CIN(\fifo_inst/n156_3 ),
+	.COUT(\fifo_inst/n157_3 ),
+	.SUM(\fifo_inst/n157_1_SUM )
 );
-defparam \fifo_inst/n159_s0 .ALU_MODE=3;
+defparam \fifo_inst/n157_s0 .ALU_MODE=3;
 INV \fifo_inst/n4_s2  (
 	.I(RdClk),
 	.O(\fifo_inst/n4_6 )

src/src/WrapFifoChain/FifoMax2870/FifoMax2870_tmp.v

@@ -1,24 +1,24 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:07:36 2024
+//Device: GW1N-9
+//Created Time: Thu Jun 26 11:10:16 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	FifoMax2870 your_instance_name(
-		.Data(Data_i), //input [31:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [31:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [31:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [31:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FIFOHS.prj

@@ -4,17 +4,19 @@
     <Version>beta</Version>
     <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
     <FileList>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
     </FileList>
     <OptionList>
         <Option type="disable_insert_pad" value="1"/>
-        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
-        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/FifoMax2870/temp/FIFOHS"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Gowin/Projects/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS"/>
         <Option type="output_file" value="FifoMax2870.vg"/>
         <Option type="output_template" value="FifoMax2870_tmp.v"/>
         <Option type="ram_balance" value="1"/>
         <Option type="ram_rw_check" value="1"/>
+        <Option type="vcc" value="1.2"/>
+        <Option type="vccx" value="3.3"/>
         <Option type="verilog_language" value="sysv-2017"/>
     </OptionList>
 </Project>

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FifoMax2870.log

@@ -1,19 +1,28 @@
 GowinSynthesis start
 Running parser ...
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
-Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
-Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Compiling module 'FifoMax2870'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
-Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'Reset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'RPReset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoMax2870'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 NOTE  (EX0101) : Current top module is "FifoMax2870"
 [5%] Running netlist conversion ...
 Running device independent optimization ...
@@ -29,17 +38,17 @@ Running technical mapping ...
 [60%] Tech-Mapping Phase 0 completed
 [65%] Tech-Mapping Phase 1 completed
 [75%] Tech-Mapping Phase 2 completed
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
 [80%] Tech-Mapping Phase 3 completed
 [90%] Tech-Mapping Phase 4 completed
-[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\temp\FIFOHS\FifoMax2870.vg" completed
-Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\temp\FIFOHS\FifoMax2870_tmp.v" completed
-[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoMax2870\temp\FIFOHS\FifoMax2870_syn.rpt.html" completed
+[95%] Generate netlist file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoMax2870\temp\FIFOHS\FifoMax2870.vg" completed
+Generate template file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoMax2870\temp\FIFOHS\FifoMax2870_tmp.v" completed
+[100%] Generate report file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoMax2870\temp\FIFOHS\FifoMax2870_syn.rpt.html" completed
 GowinSynthesis finish

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FifoMax2870.vg

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:07:36 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 11:10:16 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,164 +17,156 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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+8ygXDzlmPp+ZRlqJdLYAUkCus73410L9DCj0mg==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=8352)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=7904)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module FifoMax2870 (
   Data,

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FifoMax2870_syn_resource.html

@@ -30,10 +30,10 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 <th class="label">ROM16 NUMBER</th>
 </tr>
 <tr>
-<td class="label">FifoMax2870 (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
-<td align = "center">25</td>
+<td class="label">FifoMax2870 (C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">20</td>
 <td align = "center">2</td>
-<td align = "center">23</td>
+<td align = "center">25</td>
 <td align = "center">-</td>
 <td align = "center">1</td>
 <td align = "center">-</td>

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FifoMax2870_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="FifoMax2870" Register="25" Alu="2" Lut="23" Bsram="1" T_Register="25(25)" T_Alu="2(2)" T_Lut="23(23)" T_Bsram="1(1)"/>
+<Module name="FifoMax2870" Register="20" Alu="2" Lut="25" Bsram="1" T_Register="20(20)" T_Alu="2(2)" T_Lut="25(25)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/FifoMax2870_tmp.v

@@ -1,24 +1,24 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:07:36 2024
+//Device: GW1N-9
+//Created Time: Thu Jun 26 11:10:16 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	FifoMax2870 your_instance_name(
-		.Data(Data_i), //input [31:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [31:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [31:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [31:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/FifoMax2870/temp/FIFOHS/fifo_define.v

@@ -1,5 +1,4 @@
 `define module_name FifoMax2870
 `define EBR_BASED
-`define FWFT
 `define En_Reset
 `define Reset_Synchronization

src/src/WrapFifoChain/FifoShiftReg/FifoShiftReg.ipc

@@ -17,7 +17,7 @@ ECCSelected=false
 EmptyClear=1
 EmptySet=1
 EnReset=true
-FirstWordFallThrough=true
+FirstWordFallThrough=false
 FullClear=1
 FullSet=1
 LANG=0
@@ -28,7 +28,7 @@ ReadDataWidth=8
 ReadDepth=2
 ResetSynchronization=true
 SSRAM=false
-StandardFIFO=false
+StandardFIFO=true
 Synthesis_tool=GowinSynthesis
 WriteDataNum=false
 WriteDataWidth=8

src/src/WrapFifoChain/FifoShiftReg/FifoShiftReg.v

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:08:18 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 12:23:20 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,130 +17,120 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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-8DM4h8FNMqFHubE/tetwFYOqKFxGclYw1Xqrhw==
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+HIh3VFyc2t5fnAnrVhmzNZEMicj1U34soUinRQ==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=6400)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=5840)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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+BfEUBlASDwCIOUXz90zB1rtT+awvNQfLQ0k=
 `pragma protect end_protected
 module FifoShiftReg (
   Data,

src/src/WrapFifoChain/FifoShiftReg/FifoShiftReg.vo

@@ -1,8 +1,8 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
-//File Title: Post-PnR Simulation Model file
-//Tool Version: V1.9.9.02
-//Created Time: Thu Apr 25 16:08:18 2024
+//File Title: Post-PnR Verilog Simulation Model file
+//Tool Version: V1.9.11.02 (64-bit)
+//Created Time: Thu Jun 26 12:23:20 2025
 
 `timescale 100 ps/100 ps
 module FifoShiftReg(
@@ -37,30 +37,30 @@ wire VCC;
 wire WrClk;
 wire WrEn;
 wire \fifo_inst/n20_5 ;
-wire \fifo_inst/n26_4 ;
-wire \fifo_inst/n177_4 ;
+wire \fifo_inst/n24_3 ;
+wire \fifo_inst/n135_3 ;
+wire \fifo_inst/n178_4 ;
 wire \fifo_inst/rempty_val ;
 wire \fifo_inst/wfull_val_7 ;
 wire \fifo_inst/wfull_val1 ;
 wire \fifo_inst/wfull_val1_0 ;
 wire \fifo_inst/Full_1 ;
-wire \fifo_inst/Equal.wbinnext_0_7 ;
-wire \fifo_inst/rempty_val_8 ;
+wire \fifo_inst/Equal.wbinnext_0_8 ;
+wire \fifo_inst/rbin_num_next_0_10 ;
+wire \fifo_inst/rempty_val1 ;
 wire \fifo_inst/wfull_val1_2 ;
 wire \fifo_inst/wfull_val1_3 ;
 wire \fifo_inst/Full_1_2 ;
 wire \fifo_inst/Full_2 ;
 wire \fifo_inst/n4_6 ;
 wire \fifo_inst/n9_6 ;
-wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [0:0] \fifo_inst/Equal.wgraynext ;
-wire [1:0] \fifo_inst/rbin_num_next ;
 wire [1:1] \fifo_inst/Equal.wbinnext ;
+wire [1:1] \fifo_inst/rbin_num_next ;
+wire [0:0] \fifo_inst/Equal.rgraynext ;
 wire [1:0] \fifo_inst/reset_r ;
 wire [1:0] \fifo_inst/reset_w ;
 wire [1:0] \fifo_inst/rbin_num ;
-wire [1:0] \fifo_inst/Equal.rq1_wptr ;
-wire [1:0] \fifo_inst/Equal.rq2_wptr ;
 wire [0:0] \fifo_inst/rptr ;
 wire [1:0] \fifo_inst/wptr ;
 wire [0:0] \fifo_inst/Equal.wbin ;
@@ -82,41 +82,39 @@ LUT4 \fifo_inst/n20_s1  (
 	.F(\fifo_inst/n20_5 )
 );
 defparam \fifo_inst/n20_s1 .INIT=16'h5300;
-LUT3 \fifo_inst/n26_s1  (
-	.I0(RdEn),
-	.I1(Empty),
-	.I2(\fifo_inst/rempty_val ),
-	.F(\fifo_inst/n26_4 )
-);
-defparam \fifo_inst/n26_s1 .INIT=8'h0E;
-LUT3 \fifo_inst/Equal.rgraynext_0_s0  (
-	.I0(\fifo_inst/rbin_num [0]),
-	.I1(\fifo_inst/rbin_num_next [0]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/Equal.rgraynext [0])
+LUT2 \fifo_inst/n24_s0  (
+	.I0(Empty),
+	.I1(RdEn),
+	.F(\fifo_inst/n24_3 )
 );
-defparam \fifo_inst/Equal.rgraynext_0_s0 .INIT=8'h1E;
+defparam \fifo_inst/n24_s0 .INIT=4'h4;
 LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wgraynext [0])
 );
 defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
-LUT2 \fifo_inst/n177_s1  (
+LUT2 \fifo_inst/n135_s0  (
+	.I0(\fifo_inst/rempty_val ),
+	.I1(\fifo_inst/reset_r [1]),
+	.F(\fifo_inst/n135_3 )
+);
+defparam \fifo_inst/n135_s0 .INIT=4'hE;
+LUT2 \fifo_inst/n178_s1  (
 	.I0(\fifo_inst/reset_w [1]),
 	.I1(\fifo_inst/wfull_val_7 ),
-	.F(\fifo_inst/n177_4 )
+	.F(\fifo_inst/n178_4 )
 );
-defparam \fifo_inst/n177_s1 .INIT=4'h4;
+defparam \fifo_inst/n178_s1 .INIT=4'h4;
 LUT4 \fifo_inst/rempty_val_s3  (
-	.I0(\fifo_inst/Equal.rq2_wptr [1]),
-	.I1(\fifo_inst/rempty_val_8 ),
-	.I2(\fifo_inst/Equal.rq2_wptr [0]),
-	.I3(\fifo_inst/rbin_num_next [0]),
+	.I0(\fifo_inst/wptr [0]),
+	.I1(\fifo_inst/rptr [0]),
+	.I2(\fifo_inst/wptr [1]),
+	.I3(\fifo_inst/rbin_num [1]),
 	.F(\fifo_inst/rempty_val )
 );
-defparam \fifo_inst/rempty_val_s3 .INIT=16'h4221;
+defparam \fifo_inst/rempty_val_s3 .INIT=16'h9009;
 LUT4 \fifo_inst/wfull_val_s3  (
 	.I0(\fifo_inst/wptr [0]),
 	.I1(\fifo_inst/wptr [1]),
@@ -133,8 +131,8 @@ LUT3 \fifo_inst/wfull_val1_s9  (
 );
 defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
 LUT3 \fifo_inst/wfull_val1_s10  (
-	.I0(\fifo_inst/wfull_val_7 ),
-	.I1(\fifo_inst/wfull_val1_0 ),
+	.I0(\fifo_inst/wfull_val1_0 ),
+	.I1(\fifo_inst/wfull_val_7 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/wfull_val1_0 )
 );
@@ -147,47 +145,48 @@ LUT3 \fifo_inst/Full_d_s  (
 );
 defparam \fifo_inst/Full_d_s .INIT=8'hAC;
 LUT3 \fifo_inst/Full_s8  (
-	.I0(\fifo_inst/wfull_val_7 ),
-	.I1(\fifo_inst/Full_1 ),
+	.I0(\fifo_inst/Full_1 ),
+	.I1(\fifo_inst/wfull_val_7 ),
 	.I2(\fifo_inst/reset_w [1]),
 	.F(\fifo_inst/Full_1 )
 );
 defparam \fifo_inst/Full_s8 .INIT=8'h0E;
-LUT3 \fifo_inst/rbin_num_next_0_s5  (
-	.I0(Empty),
-	.I1(RdEn),
-	.I2(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rbin_num_next [0])
-);
-defparam \fifo_inst/rbin_num_next_0_s5 .INIT=8'hB4;
-LUT3 \fifo_inst/rbin_num_next_1_s2  (
-	.I0(\fifo_inst/rbin_num_next [0]),
-	.I1(\fifo_inst/rbin_num [0]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.F(\fifo_inst/rbin_num_next [1])
-);
-defparam \fifo_inst/rbin_num_next_1_s2 .INIT=8'hB4;
 LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
-	.F(\fifo_inst/Equal.wbinnext_0_7 )
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
+	.F(\fifo_inst/Equal.wbinnext_0_8 )
 );
 defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
 LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
-	.I0(\fifo_inst/Equal.wbin [0]),
-	.I1(\fifo_inst/n20_5 ),
+	.I0(\fifo_inst/n20_5 ),
+	.I1(\fifo_inst/Equal.wbin [0]),
 	.I2(\fifo_inst/wptr [1]),
 	.F(\fifo_inst/Equal.wbinnext [1])
 );
 defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
-LUT4 \fifo_inst/rempty_val_s4  (
-	.I0(\fifo_inst/Equal.rq2_wptr [0]),
-	.I1(\fifo_inst/Equal.rq2_wptr [1]),
-	.I2(\fifo_inst/rbin_num [1]),
-	.I3(\fifo_inst/rbin_num [0]),
-	.F(\fifo_inst/rempty_val_8 )
+LUT4 \fifo_inst/rbin_num_next_1_s3  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/rbin_num_next [1])
+);
+defparam \fifo_inst/rbin_num_next_1_s3 .INIT=16'hBF40;
+LUT3 \fifo_inst/rbin_num_next_0_s4  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.F(\fifo_inst/rbin_num_next_0_10 )
+);
+defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
+LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
+	.I0(Empty),
+	.I1(RdEn),
+	.I2(\fifo_inst/rbin_num [0]),
+	.I3(\fifo_inst/rbin_num [1]),
+	.F(\fifo_inst/Equal.rgraynext [0])
 );
-defparam \fifo_inst/rempty_val_s4 .INIT=16'h871E;
+defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
 DFFP \fifo_inst/reset_r_0_s0  (
 	.D(GND),
 	.CLK(\fifo_inst/n4_6 ),
@@ -217,40 +216,12 @@ DFFC \fifo_inst/rbin_num_1_s0  (
 );
 defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
 DFFC \fifo_inst/rbin_num_0_s0  (
-	.D(\fifo_inst/rbin_num_next [0]),
+	.D(\fifo_inst/rbin_num_next_0_10 ),
 	.CLK(RdClk),
 	.CLEAR(\fifo_inst/reset_r [1]),
 	.Q(\fifo_inst/rbin_num [0])
 );
 defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_1_s0  (
-	.D(\fifo_inst/wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [1])
-);
-defparam \fifo_inst/Equal.rq1_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq1_wptr_0_s0  (
-	.D(\fifo_inst/wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq1_wptr [0])
-);
-defparam \fifo_inst/Equal.rq1_wptr_0_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_1_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [1]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [1])
-);
-defparam \fifo_inst/Equal.rq2_wptr_1_s0 .INIT=1'b0;
-DFFC \fifo_inst/Equal.rq2_wptr_0_s0  (
-	.D(\fifo_inst/Equal.rq1_wptr [0]),
-	.CLK(RdClk),
-	.CLEAR(\fifo_inst/reset_r [1]),
-	.Q(\fifo_inst/Equal.rq2_wptr [0])
-);
-defparam \fifo_inst/Equal.rq2_wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/rptr_0_s0  (
 	.D(\fifo_inst/Equal.rgraynext [0]),
 	.CLK(RdClk),
@@ -273,16 +244,23 @@ DFFC \fifo_inst/wptr_0_s0  (
 );
 defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
 DFFC \fifo_inst/Equal.wbin_0_s0  (
-	.D(\fifo_inst/Equal.wbinnext_0_7 ),
+	.D(\fifo_inst/Equal.wbinnext_0_8 ),
 	.CLK(WrClk),
 	.CLEAR(\fifo_inst/reset_w [1]),
 	.Q(\fifo_inst/Equal.wbin [0])
 );
 defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
-DFFP \fifo_inst/Empty_s0  (
+DFFP \fifo_inst/rempty_val1_s0  (
 	.D(\fifo_inst/rempty_val ),
 	.CLK(RdClk),
-	.PRESET(\fifo_inst/reset_r [1]),
+	.PRESET(\fifo_inst/n135_3 ),
+	.Q(\fifo_inst/rempty_val1 )
+);
+defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
+DFFP \fifo_inst/Empty_s0  (
+	.D(\fifo_inst/rempty_val1 ),
+	.CLK(RdClk),
+	.PRESET(\fifo_inst/n135_3 ),
 	.Q(Empty)
 );
 defparam \fifo_inst/Empty_s0 .INIT=1'b1;
@@ -303,7 +281,7 @@ defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
 DFFP \fifo_inst/wfull_val1_s1  (
 	.D(\fifo_inst/wfull_val_7 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n177_4 ),
+	.PRESET(\fifo_inst/n178_4 ),
 	.Q(\fifo_inst/wfull_val1_3 )
 );
 defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
@@ -317,7 +295,7 @@ defparam \fifo_inst/Full_s0 .INIT=1'b0;
 DFFP \fifo_inst/Full_s1  (
 	.D(\fifo_inst/wfull_val1 ),
 	.CLK(WrClk),
-	.PRESET(\fifo_inst/n177_4 ),
+	.PRESET(\fifo_inst/n178_4 ),
 	.Q(\fifo_inst/Full_2 )
 );
 defparam \fifo_inst/Full_s1 .INIT=1'b1;
@@ -326,14 +304,14 @@ SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
 	.CEA(\fifo_inst/n20_5 ),
 	.RESETA(GND),
 	.CLKB(RdClk),
-	.CEB(\fifo_inst/n26_4 ),
+	.CEB(\fifo_inst/n24_3 ),
 	.RESETB(\fifo_inst/reset_r [1]),
 	.OCE(GND),
 	.BLKSELA({GND, GND, GND}),
 	.BLKSELB({GND, GND, GND}),
 	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[7:0]}),
 	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, GND, GND}),
-	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num_next [0], GND, GND, GND}),
+	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND}),
 	.DO({\fifo_inst/DO [31:8], Q[7:0]})
 );
 defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;

src/src/WrapFifoChain/FifoShiftReg/FifoShiftReg_tmp.v

@@ -1,24 +1,24 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:08:18 2024
+//Device: GW1N-9
+//Created Time: Thu Jun 26 12:23:20 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	FifoShiftReg your_instance_name(
-		.Data(Data_i), //input [7:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [7:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [7:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [7:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FIFOHS.prj

@@ -4,17 +4,19 @@
     <Version>beta</Version>
     <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
     <FileList>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
-        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
+        <File path="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
     </FileList>
     <OptionList>
         <Option type="disable_insert_pad" value="1"/>
-        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
-        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/FifoShiftReg/temp/FIFOHS"/>
+        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data"/>
+        <Option type="include_path" value="C:/Gowin/Projects/SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS"/>
         <Option type="output_file" value="FifoShiftReg.vg"/>
         <Option type="output_template" value="FifoShiftReg_tmp.v"/>
         <Option type="ram_balance" value="1"/>
         <Option type="ram_rw_check" value="1"/>
+        <Option type="vcc" value="1.2"/>
+        <Option type="vccx" value="3.3"/>
         <Option type="verilog_language" value="sysv-2017"/>
     </OptionList>
 </Project>

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FifoShiftReg.log

@@ -1,19 +1,28 @@
 GowinSynthesis start
 Running parser ...
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
-Analyzing included file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Back to file '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Undeclared symbol '**', assumed default net type '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
-Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
-Analyzing included file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
-Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Back to file 'C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
-Compiling module 'FifoShiftReg'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
-Compiling module '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'Reset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Undeclared symbol 'RPReset', assumed default net type 'wire'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Analyzing Verilog file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'
+Analyzing included file 'fifo_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":1)
+Analyzing included file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\static_macro_define.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":2)
+Analyzing included file 'fifo_parameter.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Back to file 'C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":57)
+Compiling module 'FifoShiftReg'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs_top.v":4)
+Compiling module '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+Extracting RAM for identifier '**'("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 NOTE  (EX0101) : Current top module is "FifoShiftReg"
 [5%] Running netlist conversion ...
 Running device independent optimization ...
@@ -29,17 +38,17 @@ Running technical mapping ...
 [60%] Tech-Mapping Phase 0 completed
 [65%] Tech-Mapping Phase 1 completed
 [75%] Tech-Mapping Phase 2 completed
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/wfull_val1_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "wfull_val1"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s6"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
-WARN  (AG0100) : Find logical loop signal : "fifo_inst/Full_s3"("C:\Gowin\Gowin_V1.9.9.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
+WARN  (AG0100) : Find logical loop signal : "Full"("C:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\FIFO_HS\data\fifo_hs.v":15293)
 WARN  (AG0101) : The netlist is not one directed acyclic graph
 [80%] Tech-Mapping Phase 3 completed
 [90%] Tech-Mapping Phase 4 completed
-[95%] Generate netlist file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoShiftReg\temp\FIFOHS\FifoShiftReg.vg" completed
-Generate template file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoShiftReg\temp\FIFOHS\FifoShiftReg_tmp.v" completed
-[100%] Generate report file "C:\Projects\QuestaProjects\main_tb\fifo_hs\FifoShiftReg\temp\FIFOHS\FifoShiftReg_syn.rpt.html" completed
+[95%] Generate netlist file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoShiftReg\temp\FIFOHS\FifoShiftReg.vg" completed
+Generate template file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoShiftReg\temp\FIFOHS\FifoShiftReg_tmp.v" completed
+[100%] Generate report file "C:\Gowin\Projects\SB_TMSG44V1_FPGA\src\src\WrapFifoChain\FifoShiftReg\temp\FIFOHS\FifoShiftReg_syn.rpt.html" completed
 GowinSynthesis finish

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FifoShiftReg.vg

@@ -1,11 +1,11 @@
 //
 //Written by GowinSynthesis
-//Tool Version "V1.9.9.02"
-//Thu Apr 25 16:08:18 2024
+//Tool Version "V1.9.11.02 (64-bit)"
+//Thu Jun 26 12:23:20 2025
 
 //Source file index table:
-//file0 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
-//file1 "\C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
+//file0 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v"
+//file1 "\C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v"
 `timescale 100 ps/100 ps
 `pragma protect begin_protected
 `pragma protect version="2.3"
@@ -17,130 +17,120 @@
 `pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
 `pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
 `pragma protect key_block
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-8DM4h8FNMqFHubE/tetwFYOqKFxGclYw1Xqrhw==
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+HIh3VFyc2t5fnAnrVhmzNZEMicj1U34soUinRQ==
 
-`pragma protect encoding=(enctype="base64", line_length=76, bytes=6400)
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=5840)
 `pragma protect data_keyowner="default-ip-vendor"
 `pragma protect data_keyname="default-ip-key"
 `pragma protect data_method="aes128-cfb"
 `pragma protect data_block
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 `pragma protect end_protected
 module FifoShiftReg (
   Data,

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FifoShiftReg_syn_resource.html

@@ -30,8 +30,8 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 <th class="label">ROM16 NUMBER</th>
 </tr>
 <tr>
-<td class="label">FifoShiftReg (C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
-<td align = "center">19</td>
+<td class="label">FifoShiftReg (C:/Gowin/Gowin_V1.9.11.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v)</td>
+<td align = "center">16</td>
 <td align = "center">-</td>
 <td align = "center">18</td>
 <td align = "center">-</td>

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FifoShiftReg_syn_rsc.xml

@@ -1,2 +1,2 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Module name="FifoShiftReg" Register="19" Lut="18" Bsram="1" T_Register="19(19)" T_Lut="18(18)" T_Bsram="1(1)"/>
+<Module name="FifoShiftReg" Register="16" Lut="18" Bsram="1" T_Register="16(16)" T_Lut="18(18)" T_Bsram="1(1)"/>

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/FifoShiftReg_tmp.v

@@ -1,24 +1,24 @@
-//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
 //All rights reserved.
 //File Title: Template file for instantiation
-//Tool Version: V1.9.9.02
+//Tool Version: V1.9.11.02 (64-bit)
 //Part Number: GW1N-LV9PG256C6/I5
-//Device: GW1N-
-//Created Time: Thu Apr 25 16:08:18 2024
+//Device: GW1N-9
+//Created Time: Thu Jun 26 12:23:20 2025
 
 //Change the instance name and port connections to the signal names
 //--------Copy here to design--------
 
 	FifoShiftReg your_instance_name(
-		.Data(Data_i), //input [7:0] Data
-		.Reset(Reset_i), //input Reset
-		.WrClk(WrClk_i), //input WrClk
-		.RdClk(RdClk_i), //input RdClk
-		.WrEn(WrEn_i), //input WrEn
-		.RdEn(RdEn_i), //input RdEn
-		.Q(Q_o), //output [7:0] Q
-		.Empty(Empty_o), //output Empty
-		.Full(Full_o) //output Full
+		.Data(Data), //input [7:0] Data
+		.Reset(Reset), //input Reset
+		.WrClk(WrClk), //input WrClk
+		.RdClk(RdClk), //input RdClk
+		.WrEn(WrEn), //input WrEn
+		.RdEn(RdEn), //input RdEn
+		.Q(Q), //output [7:0] Q
+		.Empty(Empty), //output Empty
+		.Full(Full) //output Full
 	);
 
 //--------Copy end-------------------

src/src/WrapFifoChain/FifoShiftReg/temp/FIFOHS/fifo_define.v

@@ -1,5 +1,4 @@
 `define module_name FifoShiftReg
 `define EBR_BASED
-`define FWFT
 `define En_Reset
 `define Reset_Synchronization

src/src/WrapFifoChain/LmxWrapper.v

@@ -59,7 +59,10 @@ reg plsToggleSyncB;
 
 reg ssR;
 reg ssReg;
-reg ssRegDds;
+// reg ssRegDds;
+reg ssDdsSyncA;
+reg ssDdsSyncB;
+reg ssDdsSyncC;
 reg [3:0] lmxWordNumReg; 
 reg [3:0] lmxWordNumRegR;
 //==========================================================================//
@@ -112,10 +115,14 @@ end
 
 always @(posedge RdClk_i) begin 
 	if (Rst_i) begin 
-		ssRegDds <= 1'b0;
+		ssDdsSyncA <= 1'b0;
+		ssDdsSyncB <= 1'b0;
+		ssDdsSyncC <= 1'b0;
 	end
 	else begin 
-		ssRegDds <= DdsCs_i;
+		ssDdsSyncA <= DdsCs_i;
+		ssDdsSyncB <= ssDdsSyncA;
+		ssDdsSyncC <= ssDdsSyncB;
 	end
 end
 
@@ -141,10 +148,10 @@ always @(posedge RdClk_i) begin
 	end
 	else begin
 		if (!LmxDirectFlag_i) begin  
-			if (lmxWordNumReg == 0 ) begin
+			if ((lmxWordNumReg == 0) && (DdsWordNumReg_i == 0)) begin
 				PllVtuneCtrl_o <= 1'b1;
 			end
-			else if ((!DdsCs_i && ssRegDds) && (DdsWordNumReg_i != 0)) begin 
+			else if ((!ssDdsSyncC && ssDdsSyncB ) && (DdsWordNumReg_i != 0)) begin 
 				PllVtuneCtrl_o <= 1'b0;
 			end
 			else if ((!Ss_o && ssReg) && (lmxWordNumReg != 0) ) begin 
@@ -190,7 +197,9 @@ FifoLMX FifoLMX_inst (
 );
 
 SpiM #(
-	.DATA_WIDTH	(DATA_WIDTH)
+	.DATA_WIDTH	(DATA_WIDTH),
+	.CS_DELAY	(3'h1), 
+	.IS_LMX_DELAY(1'b1)
 )SpiMLmx(
 	.Clk_i		(RdClk_i),
 	.Rst_i		(Rst_i),