//Copyright (C)2014-2024 GOWIN Semiconductor Corporation.
//All rights reserved.
//File Title: Timing Constraints file
//Tool Version: V1.9.9.02 
//Created Time: 2024-05-02 15:55:01
create_clock -name clk5 -period 200 -waveform {0 100} [get_nets {clk5}]
create_clock -name clk50 -period 20 -waveform {0 10} [get_nets {clk50}]
create_clock -name clk26dot25 -period 38.095 -waveform {0 19.047} [get_nets {clk26dot25}]
create_clock -name clk20 -period 50 -waveform {0 25} [get_nets {clk20}]
create_clock -name clk100 -period 10 -waveform {0 5} [get_nets {gclk100}]
create_clock -name clk210 -period 4.762 -waveform {0 2.381} [get_nets {ClkGen/clk210Mhz}]
create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
//create_clock -name clk60 -period 16.667 -waveform {0 8.334} [get_nets {clk60}]
set_clock_groups -asynchronous -group [get_clocks {Clk_i}] -group [get_clocks {Sck_i}]
set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Clk_i}] 
set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Sck_i}] 
report_timing -setup -from_clock [get_clocks {clk100}] -max_paths 1000 -max_common_paths 1