//Copyright (C)2014-2024 GOWIN Semiconductor Corporation.
//All rights reserved.
//File Title: Timing Constraints file
//Tool Version: V1.9.9.01 (64-bit) 
//Created Time: 2024-03-18 14:44:39
create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
create_generated_clock -name clk30 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 30 [get_ports {Clk30_o}]
create_generated_clock -name clk40 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 40 [get_ports {Clk40_o}]
create_generated_clock -name clk50 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 50 [get_ports {Clk50_o}]
create_generated_clock -name clk5 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 5 [get_ports {Clk5_o}]
create_generated_clock -name clk360 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 360 [get_ports {Clk600_o}]
create_generated_clock -name clk100 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 100 [get_ports {Clk100_o}]
create_generated_clock -name clk20 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 20 [get_ports {Clk20_o}]
create_generated_clock -name clk75 -source [get_ports {Clk_i}] -master_clock Clk_i -divide_by 24 -multiply_by 72 [get_ports {Clk75_o}]
set_clock_groups -asynchronous -group [get_clocks {Clk_i Sck_i}]
report_timing -setup -from_clock [get_clocks {clk100}] -max_paths 100 -max_common_paths 1
report_timing -setup -from_clock [get_clocks {clk360}] -max_paths 100 -max_common_paths 1
report_timing -setup -from_clock [get_clocks {clk75}] -max_paths 100 -max_common_paths 1
report_timing -setup -from_clock [get_clocks {clk50}] -max_paths 100 -max_common_paths 1
report_timing -setup -from [get_ports {Rst_i}]