- //Copyright (C)2014-2024 GOWIN Semiconductor Corporation.
- //All rights reserved.
- //File Title: Timing Constraints file
- //Tool Version: V1.9.9.03 (64-bit)
- //Created Time: 2024-05-31 16:04:42
- create_clock -name clk5 -period 200 -waveform {0 100} [get_nets {clk5}]
- create_clock -name clk60 -period 16.667 -waveform {0 8.334} [get_nets {clk60}]
- create_clock -name Clk_i -period 41.667 -waveform {0 20.834} [get_ports {Clk_i}]
- create_clock -name Sck_i -period 10 -waveform {0 5} [get_ports {Sck_i}]
- //create_clock -name clk100 -period 10 -waveform {0 5} [get_nets {gclk100}]
- set_clock_groups -asynchronous -group [get_clocks {Clk_i}] -group [get_clocks {Sck_i}]
- set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Clk_i}]
- set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {Sck_i}]
- set_false_path -from [get_clocks {Sck_i}] -to [get_clocks {clk60}]
- set_false_path -from [get_clocks {clk60}] -to [get_clocks {Sck_i}]
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