SB_TMSG44V1_FPGA/src/src/WrapFifoChain/Fifo16x3/temp/FIFOHS/FIFOHS.prj

<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
    <Version>beta</Version>
    <Device id="GW1N-9" package="PBGA256" speed="6" partNumber="GW1N-LV9PG256C6/I5"/>
    <FileList>
        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs.v" type="verilog"/>
        <File path="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data/fifo_hs_top.v" type="verilog"/>
    </FileList>
    <OptionList>
        <Option type="disable_insert_pad" value="1"/>
        <Option type="include_path" value="C:/Gowin/Gowin_V1.9.9.02_x64/IDE/ipcore/FIFO_HS/data"/>
        <Option type="include_path" value="C:/Projects/QuestaProjects/main_tb/fifo_hs/Fifo16x3/temp/FIFOHS"/>
        <Option type="output_file" value="Fifo16x3.vg"/>
        <Option type="output_template" value="Fifo16x3_tmp.v"/>
        <Option type="ram_balance" value="1"/>
        <Option type="ram_rw_check" value="1"/>
        <Option type="verilog_language" value="sysv-2017"/>
    </OptionList>
</Project>