SB_TMSG44V1_FPGA/src/src/WrapFifoChain/FifoDDS/FifoDDS.vo

//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Post-PnR Verilog Simulation Model file
//Tool Version: V1.9.11.02 (64-bit)
//Created Time: Thu Jun 26 11:09:20 2025

`timescale 100 ps/100 ps
module FifoDDS(
	Data,
	Reset,
	WrClk,
	RdClk,
	WrEn,
	RdEn,
	Q,
	Empty,
	Full
);
input [79:0] Data;
input Reset;
input WrClk;
input RdClk;
input WrEn;
input RdEn;
output [79:0] Q;
output Empty;
output Full;
wire [79:0] Data;
wire Empty;
wire Full;
wire GND;
wire [79:0] Q;
wire RdClk;
wire RdEn;
wire Reset;
wire VCC;
wire WrClk;
wire WrEn;
wire \fifo_inst/n20_5 ;
wire \fifo_inst/n24_3 ;
wire \fifo_inst/n423_3 ;
wire \fifo_inst/n538_4 ;
wire \fifo_inst/rempty_val ;
wire \fifo_inst/wfull_val_7 ;
wire \fifo_inst/wfull_val1 ;
wire \fifo_inst/wfull_val1_0 ;
wire \fifo_inst/Full_1 ;
wire \fifo_inst/Equal.wbinnext_0_8 ;
wire \fifo_inst/rbin_num_next_0_10 ;
wire \fifo_inst/rempty_val1 ;
wire \fifo_inst/wfull_val1_2 ;
wire \fifo_inst/wfull_val1_3 ;
wire \fifo_inst/Full_1_2 ;
wire \fifo_inst/Full_2 ;
wire \fifo_inst/n4_6 ;
wire \fifo_inst/n9_6 ;
wire [0:0] \fifo_inst/Equal.wgraynext ;
wire [1:1] \fifo_inst/Equal.wbinnext ;
wire [1:1] \fifo_inst/rbin_num_next ;
wire [0:0] \fifo_inst/Equal.rgraynext ;
wire [1:0] \fifo_inst/reset_r ;
wire [1:0] \fifo_inst/reset_w ;
wire [1:0] \fifo_inst/rbin_num ;
wire [0:0] \fifo_inst/rptr ;
wire [1:0] \fifo_inst/wptr ;
wire [0:0] \fifo_inst/Equal.wbin ;
wire [31:16] \fifo_inst/DO ;
VCC VCC_cZ (
  .V(VCC)
);
GND GND_cZ (
  .G(GND)
);
GSR GSR (
	.GSRI(VCC)
);
LUT4 \fifo_inst/n20_s1  (
	.I0(\fifo_inst/Full_2 ),
	.I1(\fifo_inst/Full_1_2 ),
	.I2(\fifo_inst/Full_1 ),
	.I3(WrEn),
	.F(\fifo_inst/n20_5 )
);
defparam \fifo_inst/n20_s1 .INIT=16'h5300;
LUT2 \fifo_inst/n24_s0  (
	.I0(Empty),
	.I1(RdEn),
	.F(\fifo_inst/n24_3 )
);
defparam \fifo_inst/n24_s0 .INIT=4'h4;
LUT3 \fifo_inst/Equal.wgraynext_0_s0  (
	.I0(\fifo_inst/n20_5 ),
	.I1(\fifo_inst/Equal.wbin [0]),
	.I2(\fifo_inst/wptr [1]),
	.F(\fifo_inst/Equal.wgraynext [0])
);
defparam \fifo_inst/Equal.wgraynext_0_s0 .INIT=8'h1E;
LUT2 \fifo_inst/n423_s0  (
	.I0(\fifo_inst/rempty_val ),
	.I1(\fifo_inst/reset_r [1]),
	.F(\fifo_inst/n423_3 )
);
defparam \fifo_inst/n423_s0 .INIT=4'hE;
LUT2 \fifo_inst/n538_s1  (
	.I0(\fifo_inst/reset_w [1]),
	.I1(\fifo_inst/wfull_val_7 ),
	.F(\fifo_inst/n538_4 )
);
defparam \fifo_inst/n538_s1 .INIT=4'h4;
LUT4 \fifo_inst/rempty_val_s3  (
	.I0(\fifo_inst/wptr [0]),
	.I1(\fifo_inst/rptr [0]),
	.I2(\fifo_inst/wptr [1]),
	.I3(\fifo_inst/rbin_num [1]),
	.F(\fifo_inst/rempty_val )
);
defparam \fifo_inst/rempty_val_s3 .INIT=16'h9009;
LUT4 \fifo_inst/wfull_val_s3  (
	.I0(\fifo_inst/wptr [0]),
	.I1(\fifo_inst/wptr [1]),
	.I2(\fifo_inst/rbin_num [1]),
	.I3(\fifo_inst/rptr [0]),
	.F(\fifo_inst/wfull_val_7 )
);
defparam \fifo_inst/wfull_val_s3 .INIT=16'h1428;
LUT3 \fifo_inst/wfull_val1_s9  (
	.I0(\fifo_inst/wfull_val1_3 ),
	.I1(\fifo_inst/wfull_val1_2 ),
	.I2(\fifo_inst/wfull_val1_0 ),
	.F(\fifo_inst/wfull_val1 )
);
defparam \fifo_inst/wfull_val1_s9 .INIT=8'hAC;
LUT3 \fifo_inst/wfull_val1_s10  (
	.I0(\fifo_inst/wfull_val1_0 ),
	.I1(\fifo_inst/wfull_val_7 ),
	.I2(\fifo_inst/reset_w [1]),
	.F(\fifo_inst/wfull_val1_0 )
);
defparam \fifo_inst/wfull_val1_s10 .INIT=8'h0E;
LUT3 \fifo_inst/Full_d_s  (
	.I0(\fifo_inst/Full_2 ),
	.I1(\fifo_inst/Full_1_2 ),
	.I2(\fifo_inst/Full_1 ),
	.F(Full)
);
defparam \fifo_inst/Full_d_s .INIT=8'hAC;
LUT3 \fifo_inst/Full_s8  (
	.I0(\fifo_inst/Full_1 ),
	.I1(\fifo_inst/wfull_val_7 ),
	.I2(\fifo_inst/reset_w [1]),
	.F(\fifo_inst/Full_1 )
);
defparam \fifo_inst/Full_s8 .INIT=8'h0E;
LUT2 \fifo_inst/Equal.wbinnext_0_s3  (
	.I0(\fifo_inst/n20_5 ),
	.I1(\fifo_inst/Equal.wbin [0]),
	.F(\fifo_inst/Equal.wbinnext_0_8 )
);
defparam \fifo_inst/Equal.wbinnext_0_s3 .INIT=4'h6;
LUT3 \fifo_inst/Equal.wbinnext_1_s2  (
	.I0(\fifo_inst/n20_5 ),
	.I1(\fifo_inst/Equal.wbin [0]),
	.I2(\fifo_inst/wptr [1]),
	.F(\fifo_inst/Equal.wbinnext [1])
);
defparam \fifo_inst/Equal.wbinnext_1_s2 .INIT=8'h78;
LUT4 \fifo_inst/rbin_num_next_1_s3  (
	.I0(Empty),
	.I1(RdEn),
	.I2(\fifo_inst/rbin_num [0]),
	.I3(\fifo_inst/rbin_num [1]),
	.F(\fifo_inst/rbin_num_next [1])
);
defparam \fifo_inst/rbin_num_next_1_s3 .INIT=16'hBF40;
LUT3 \fifo_inst/rbin_num_next_0_s4  (
	.I0(Empty),
	.I1(RdEn),
	.I2(\fifo_inst/rbin_num [0]),
	.F(\fifo_inst/rbin_num_next_0_10 )
);
defparam \fifo_inst/rbin_num_next_0_s4 .INIT=8'hB4;
LUT4 \fifo_inst/Equal.rgraynext_0_s1  (
	.I0(Empty),
	.I1(RdEn),
	.I2(\fifo_inst/rbin_num [0]),
	.I3(\fifo_inst/rbin_num [1]),
	.F(\fifo_inst/Equal.rgraynext [0])
);
defparam \fifo_inst/Equal.rgraynext_0_s1 .INIT=16'h0BF4;
DFFP \fifo_inst/reset_r_0_s0  (
	.D(GND),
	.CLK(\fifo_inst/n4_6 ),
	.PRESET(Reset),
	.Q(\fifo_inst/reset_r [0])
);
defparam \fifo_inst/reset_r_0_s0 .INIT=1'b1;
DFFP \fifo_inst/reset_w_1_s0  (
	.D(\fifo_inst/reset_w [0]),
	.CLK(\fifo_inst/n9_6 ),
	.PRESET(Reset),
	.Q(\fifo_inst/reset_w [1])
);
defparam \fifo_inst/reset_w_1_s0 .INIT=1'b1;
DFFP \fifo_inst/reset_w_0_s0  (
	.D(GND),
	.CLK(\fifo_inst/n9_6 ),
	.PRESET(Reset),
	.Q(\fifo_inst/reset_w [0])
);
defparam \fifo_inst/reset_w_0_s0 .INIT=1'b1;
DFFC \fifo_inst/rbin_num_1_s0  (
	.D(\fifo_inst/rbin_num_next [1]),
	.CLK(RdClk),
	.CLEAR(\fifo_inst/reset_r [1]),
	.Q(\fifo_inst/rbin_num [1])
);
defparam \fifo_inst/rbin_num_1_s0 .INIT=1'b0;
DFFC \fifo_inst/rbin_num_0_s0  (
	.D(\fifo_inst/rbin_num_next_0_10 ),
	.CLK(RdClk),
	.CLEAR(\fifo_inst/reset_r [1]),
	.Q(\fifo_inst/rbin_num [0])
);
defparam \fifo_inst/rbin_num_0_s0 .INIT=1'b0;
DFFC \fifo_inst/rptr_0_s0  (
	.D(\fifo_inst/Equal.rgraynext [0]),
	.CLK(RdClk),
	.CLEAR(\fifo_inst/reset_r [1]),
	.Q(\fifo_inst/rptr [0])
);
defparam \fifo_inst/rptr_0_s0 .INIT=1'b0;
DFFC \fifo_inst/wptr_1_s0  (
	.D(\fifo_inst/Equal.wbinnext [1]),
	.CLK(WrClk),
	.CLEAR(\fifo_inst/reset_w [1]),
	.Q(\fifo_inst/wptr [1])
);
defparam \fifo_inst/wptr_1_s0 .INIT=1'b0;
DFFC \fifo_inst/wptr_0_s0  (
	.D(\fifo_inst/Equal.wgraynext [0]),
	.CLK(WrClk),
	.CLEAR(\fifo_inst/reset_w [1]),
	.Q(\fifo_inst/wptr [0])
);
defparam \fifo_inst/wptr_0_s0 .INIT=1'b0;
DFFC \fifo_inst/Equal.wbin_0_s0  (
	.D(\fifo_inst/Equal.wbinnext_0_8 ),
	.CLK(WrClk),
	.CLEAR(\fifo_inst/reset_w [1]),
	.Q(\fifo_inst/Equal.wbin [0])
);
defparam \fifo_inst/Equal.wbin_0_s0 .INIT=1'b0;
DFFP \fifo_inst/rempty_val1_s0  (
	.D(\fifo_inst/rempty_val ),
	.CLK(RdClk),
	.PRESET(\fifo_inst/n423_3 ),
	.Q(\fifo_inst/rempty_val1 )
);
defparam \fifo_inst/rempty_val1_s0 .INIT=1'b1;
DFFP \fifo_inst/Empty_s0  (
	.D(\fifo_inst/rempty_val1 ),
	.CLK(RdClk),
	.PRESET(\fifo_inst/n423_3 ),
	.Q(Empty)
);
defparam \fifo_inst/Empty_s0 .INIT=1'b1;
DFFP \fifo_inst/reset_r_1_s0  (
	.D(\fifo_inst/reset_r [0]),
	.CLK(\fifo_inst/n4_6 ),
	.PRESET(Reset),
	.Q(\fifo_inst/reset_r [1])
);
defparam \fifo_inst/reset_r_1_s0 .INIT=1'b1;
DFFC \fifo_inst/wfull_val1_s0  (
	.D(\fifo_inst/wfull_val_7 ),
	.CLK(WrClk),
	.CLEAR(\fifo_inst/reset_w [1]),
	.Q(\fifo_inst/wfull_val1_2 )
);
defparam \fifo_inst/wfull_val1_s0 .INIT=1'b0;
DFFP \fifo_inst/wfull_val1_s1  (
	.D(\fifo_inst/wfull_val_7 ),
	.CLK(WrClk),
	.PRESET(\fifo_inst/n538_4 ),
	.Q(\fifo_inst/wfull_val1_3 )
);
defparam \fifo_inst/wfull_val1_s1 .INIT=1'b1;
DFFC \fifo_inst/Full_s0  (
	.D(\fifo_inst/wfull_val1 ),
	.CLK(WrClk),
	.CLEAR(\fifo_inst/reset_w [1]),
	.Q(\fifo_inst/Full_1_2 )
);
defparam \fifo_inst/Full_s0 .INIT=1'b0;
DFFP \fifo_inst/Full_s1  (
	.D(\fifo_inst/wfull_val1 ),
	.CLK(WrClk),
	.PRESET(\fifo_inst/n538_4 ),
	.Q(\fifo_inst/Full_2 )
);
defparam \fifo_inst/Full_s1 .INIT=1'b1;
SDPB \fifo_inst/Equal.mem_Equal.mem_0_0_s  (
	.CLKA(WrClk),
	.CEA(\fifo_inst/n20_5 ),
	.RESETA(GND),
	.CLKB(RdClk),
	.CEB(\fifo_inst/n24_3 ),
	.RESETB(\fifo_inst/reset_r [1]),
	.OCE(GND),
	.BLKSELA({GND, GND, GND}),
	.BLKSELB({GND, GND, GND}),
	.DI({Data[31:0]}),
	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND, GND, GND}),
	.DO({Q[31:0]})
);
defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .READ_MODE=1'b0;
defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_0=32;
defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BIT_WIDTH_1=32;
defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .RESET_MODE="ASYNC";
defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_0=3'b000;
defparam \fifo_inst/Equal.mem_Equal.mem_0_0_s .BLK_SEL_1=3'b000;
SDPB \fifo_inst/Equal.mem_Equal.mem_0_1_s  (
	.CLKA(WrClk),
	.CEA(\fifo_inst/n20_5 ),
	.RESETA(GND),
	.CLKB(RdClk),
	.CEB(\fifo_inst/n24_3 ),
	.RESETB(\fifo_inst/reset_r [1]),
	.OCE(GND),
	.BLKSELA({GND, GND, GND}),
	.BLKSELB({GND, GND, GND}),
	.DI({Data[63:32]}),
	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND, GND, GND}),
	.DO({Q[63:32]})
);
defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .READ_MODE=1'b0;
defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BIT_WIDTH_0=32;
defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BIT_WIDTH_1=32;
defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .RESET_MODE="ASYNC";
defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BLK_SEL_0=3'b000;
defparam \fifo_inst/Equal.mem_Equal.mem_0_1_s .BLK_SEL_1=3'b000;
SDPB \fifo_inst/Equal.mem_Equal.mem_0_2_s  (
	.CLKA(WrClk),
	.CEA(\fifo_inst/n20_5 ),
	.RESETA(GND),
	.CLKB(RdClk),
	.CEB(\fifo_inst/n24_3 ),
	.RESETB(\fifo_inst/reset_r [1]),
	.OCE(GND),
	.BLKSELA({GND, GND, GND}),
	.BLKSELB({GND, GND, GND}),
	.DI({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, Data[79:64]}),
	.ADA({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/Equal.wbin [0], GND, VCC, VCC, VCC, VCC}),
	.ADB({GND, GND, GND, GND, GND, GND, GND, GND, \fifo_inst/rbin_num [0], GND, GND, GND, GND, GND}),
	.DO({\fifo_inst/DO [31:16], Q[79:64]})
);
defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .READ_MODE=1'b0;
defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .BIT_WIDTH_0=32;
defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .BIT_WIDTH_1=32;
defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .RESET_MODE="ASYNC";
defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .BLK_SEL_0=3'b000;
defparam \fifo_inst/Equal.mem_Equal.mem_0_2_s .BLK_SEL_1=3'b000;
INV \fifo_inst/n4_s2  (
	.I(RdClk),
	.O(\fifo_inst/n4_6 )
);
INV \fifo_inst/n9_s2  (
	.I(WrClk),
	.O(\fifo_inst/n9_6 )
);
endmodule